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Journal articles on the topic '8-bit multiplier'

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Published: 5 June 2025

Last updated: 16 July 2025

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Sadaf, Sumaya, and V. Radha Krishna. "Design and Implementation of Area Efficient Low Latency Radix-8 Multiplier on FPGA." International Journal for Research in Applied Science and Engineering Technology 11, no. 10 (2023): 667–78. http://dx.doi.org/10.22214/ijraset.2023.56018.

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Abstract: Electronic systems are widely used by humans nowadays in all aspects of daily life. Today, there is no living for humans on Earth without any electronic products. High Speed, Low Power, and Low Area Electronic Systems are what the current generation needs. In digital systems, a variety of arithmetic circuits are employed. Adder, multiplier, divider, and other arithmetic circuits are some examples. To acquire Products from Multiplier and Multiplicand, there are various multipliers with various methods. One of the multipliers is Radix-4 Multiplier. The Radix-4 Multiplier produces n/2 partial products, where n is the multiplier's bit count. This multiplier has a high operating speed, power dissipation, and surface area. Area, power dissipation, and propagation delay can all be reduced by reducing the number of partial products of the n-bit multiplier. Radix-8 uses n-bit multiplier integers that are n/3 for partial products. The Area, Delay, and Power Dissipation are reduced as a result. 8- bit booth multipliers for Radix-4 and Radix-8 are designed and implemented using FPGA. For both multipliers, delay, power dissipation, and area are compared. According to the comparison, Radix8 Booth Multiplier performs better than Radix-4 Booth Multiplier in terms of delay, power dissipation, and area. Therefore, the Radix-4 Booth Multiplier can be swapped out for the Radix-8 Booth Multiplier.

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Senathipathi, Mr N., R. Rasiha, R. Sadhurya, and S. Sangeetha. "Design of Power Efficient Posit Multiplier using Compressor Based Adder." International Journal for Research in Applied Science and Engineering Technology 11, no. 5 (2023): 2768–73. http://dx.doi.org/10.22214/ijraset.2023.51597.

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Abstract: Posit number system has been used in many applications, especially the deep learning. Because of how well its nonuniform number distribution aligns with deep learning's data distribution, deep learning's training process can be sped up. The hardware multiplier is typically built with the widest mantissa bit-width available due to the flexibility of posit numbers' bitwidth. Such multiplier designs consume a lot of power since the mantissa bit-width is not necessarily the maximum value. This is especially true when the mantissa bit-width is tiny. The mantissa multiplier is still built to have the widest bit-width feasible, but it is broken into numerous smaller multipliers. At run-time, just the necessary tiny multipliers are turned on. The regime bitwidth, which can be used to determine the mantissa bit-width, controls those smaller multipliers. This design technique is applied to 8-bit, 16-bit, and 32-bit posit formats.

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Fu, Chengjie, Xiaolei Zhu, Kejie Huang, and Zheng Gu. "An 8-bit Radix-4 Non-Volatile Parallel Multiplier." Electronics 10, no. 19 (2021): 2358. http://dx.doi.org/10.3390/electronics10192358.

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The data movement between the processing and storage units has been one of the most critical issues in modern computer systems. The emerging Resistive Random Access Memory (RRAM) technology has drawn tremendous attention due to its non-volatile ability and the potential in computation application. These properties make them a perfect choice for application in modern computing systems. In this paper, an 8-bit radix-4 non-volatile parallel multiplier is proposed, with improved computational capabilities. The corresponding booth encoding scheme, read-out circuit, simplified Wallace tree, and Manchester carry chain are presented, which help to short the delay of the proposed multiplier. While the presence of RRAM save computational time and overall power as multiplicand is stored beforehand. The area of the proposed non-volatile multiplier is reduced with improved computing speed. The proposed multiplier has an area of 785.2 μm2 with Generic Processing Design Kit 45 nm process. The simulation results show that the proposed multiplier structure has a low computing power at 161.19 μW and a short delay of 0.83 ns with 1.2 V supply voltage. Comparative analyses are performed to demonstrate the effectiveness of the proposed multiplier design. Compared with conventional booth multipliers, the proposed multiplier structure reduces the energy and delay by more than 70% and 19%, respectively.

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Pinto, Rohan, and Kumara Shama. "Low-Power Modified Shift-Add Multiplier Design Using Parallel Prefix Adder." Journal of Circuits, Systems and Computers 28, no. 02 (2018): 1950019. http://dx.doi.org/10.1142/s0218126619500191.

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Multipliers are the building blocks of every digital signal processor (DSP). The performance of any digital system is dependent on the adder design and to a large extent on the multiplier block. Area and power dissipation are the major considerations in a multiplier design due to its complexity. In this paper, an efficient multiplier “bypass zero feed multiplicand directly,” based on shift-add multiplication, has been proposed for low-power application. As the shift-add multiplication is a repetitive process of addition, the implementation time of an adder is reduced by using the proposed parallel prefix adders designed based on revised Ling equations. The proposed 8-bit, 16-bit and 32-bit multipliers are implemented using 180-nm and 90-nm CMOS technologies. Simulation results reveal that the proposed multiplier is fast and lowers the power by 35% predominantly for a 32-bit multiplier.

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Berezin, N. M., I. E. Chernetskaya, V. S. Panishchev, and A. M. Shabarov. "Development of a device for multiplying numbers by means of FPGA." Journal of Physics: Conference Series 2142, no. 1 (2021): 012001. http://dx.doi.org/10.1088/1742-6596/2142/1/012001.

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Abstract The authors propose the description of the development of a device for multiplying numbers. The device for multiplying numbers on the field-programmable gate array (FPGA) includes two input and one output registers, fifty-six single-digit adders, sixty four logic elements AND, one exclusive OR gate. The main scientific and technical task in developing a device for multiplying numbers is to reduce hardware complexity using single-bit adders and logic elements. Introduction includes description of works of scientists and researchers whose publications are devoted to design and development of multiplier construction methods, multiplier FIR performance improvement by right-shift and addition method on FPGA (field-programmable gate array) basis. The implementation of MAC-block, hardware implementation of binary multiplier on the basis of multi operand adder, multiplier design by right-sliding and addition with control automaton in the FPGA basis is the actual research tasks presented in a number of papers. The description of features of multiplier implementation, high-speed multipliers with variable bit rate, studies of approaches for designing modular multipliers, FPGA image processing using Brown multiplier for performing convolution operation find application in problems of performance and speed. Also, a number of authors describe implementation of conveyorization method, design of dual multiplier, construction method of 8-bit multiplier with reduced delay, 8-bit high-density systolic multiplier arrays on FPGA and development of high-performance 8-bit multiplier using McCMOS technology. A fragment of a developed device for multiplying numbers is presented in the work by the authors. The principle of operation of a device for multiplication is described. The description of connected elements of the device is given. The timing diagrams of operation of a device for multiplication of numbers are presented.

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Raj Narain, B., and Dr T. Sasilatha. "Implementation of reconfigurable galois field multipliers over2m using primitive polynomials." International Journal of Engineering & Technology 7, no. 2.12 (2018): 386. http://dx.doi.org/10.14419/ijet.v7i2.12.11356.

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The Galois field multiplier finds extensive use in cryptographic solutions and applications. The Galois field multiplier can be implemented as fixed bitwise or reconfigurable. For fixed length, the data is restricted to the fixed length. But in reconfigurable GF multipliers, the bit length of the multiplier is flexible and is independent of hardware architecture. This paper proposes a method to implement a reconfigurable GF multiplier for various bit values from 8 to 128 bits. This paper compares the area complexity of various bit size in Xilinx Spartan 3E family FPGA and estimates the resources required for the implementation.

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Bhusare, Saroja S., and V. S. Kanchana Bhaaskaran. "Low-Power High-Accuracy Fixed-Width Radix-8 Booth Multiplier Using Probabilistic Estimation Technique." Journal of Circuits, Systems and Computers 26, no. 05 (2017): 1750079. http://dx.doi.org/10.1142/s0218126617500797.

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In many Multimedia and DSP applications, the fixed-width multipliers are used to avoid infinite growth in the word size. Fixed-width multiplier produces an [Formula: see text]-bit product with two [Formula: see text]-bit inputs. This paper presents probabilistic estimation technique applied for the fixed-width radix-8 Booth multiplier for the generation of the compensation bias circuit. The probabilistic estimation circuit for the fixed-width radix-8 Booth multiplier is derived systematically from theoretical computation in preference to time-consuming exhaustive simulations. Results show that the radix-8 direct truncated multiplier reduces the maximum absolute error by 33%, the average error by 22% and the mean square error by 39% for a 12-bit multiplier compared with the radix-4 direct truncated multiplier. Results also demonstrate that, with the probabilistic estimation technique applied to the fixed-width radix-8 Booth multiplier, there is a reduction of 25% in the maximum absolute error, 13.4% reduction in the average error, and 25.13% reduction in the mean square error have been realized compared with the existing fixed-width radix-4 Booth multiplier with probabilistic estimation technique. Standard EDA design tools are used for simulations.

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Zhang, Yu Long, Guo Chu Shou, Yi Hong Hu, and Zhi Gang Guo. "Low Complexity GF(2^m) Multiplier Based on Iterative Karatsuba Algorithm." Advanced Materials Research 546-547 (July 2012): 1409–14. http://dx.doi.org/10.4028/www.scientific.net/amr.546-547.1409.

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The complexity is one important index for Galois Field multiplier. This paper presents one low complexity GF(2m) multiplier based on iterative Karatsuba algorithm. The multiplication is replaced iteratively by three ones of half-length operands which are performed in parallel. The operands are divided into different width such as 64-bit, 32-bit, 16-bit and so on. For the 2m*2mmultiplier, we take 128 bit-widthGF(2128) multipliers as an example. We implement them on FPGA and count the number of the used LUTs and the used registers. Through analyzing the statistic, we find that, when the width of the two multiplication operands is divided to 8 bit, the multiplier consumes the least resources. Compared with the FPGA implementation of the other previous multiplier, this optimum multiplier can save 50% resources in LUTs and the registers.

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Chandrasekharan, Raji, and Sarappadi Narasimha Prasad. "Fault tolerant design for 8-bit Dadda multiplier for neural network applications." International Journal of Electrical and Computer Engineering (IJECE) 15, no. 3 (2025): 2697. https://doi.org/10.11591/ijece.v15i3.pp2697-2705.

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As digital electronic systems continue to shrink in size, they face increased susceptibility to transient errors, especially in critical applications like neural networks, which are not inherently error-resilient. Multipliers, fundamental components of neural networks, must be both fault tolerant and efficient. However, traditional fault free designs consume excessive power and require substantial silicon real estate. Among existing multiplier architectures, the Dadda multiplier stands out for its speed and efficiency, but it lacks fault tolerance needed for robust neural network applications. Therefore, there is need to design a power efficient and fault free Dadda multiplier that can address these challenges without significantly increasing power consumption or hardware complexity. In this paper a solution involving a fault tolerant Dadda multiplier optimized for neural network applications is proposed. Because of its speed and efficiency when compared to other multipliers Dadda multiplier is used as the base architecture which is designed using carry select adder (CSA) in conjunction with binary to excess one converter to reduce power and complexity. To enhance fault tolerance, self-repairing full adder is used to implement the CSA. This allows the system to detect and correct errors, ensuring robust operation in the presence of transient faults. This combination achieves a power efficient, fault tolerant multiplier with a power consumption of 52.3 mW, reflecting a 3% reduction in power compared to existing designs.

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Madaka, Venkata Subbaiah, and Umamaheswara Reddy Galiveeti. "Delay-efficient 4:3 counter design using two-bit reordering circuit for high-speed Wallace tree multiplier." International Journal of Electrical and Computer Engineering (IJECE) 13, no. 2 (2023): 1367–78. https://doi.org/10.11591/ijece.v13i2.pp1367-1378.

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In many signal processing applications, multiplier is an important functional block that plays a crucial role in computation. It is always a challenging task to design the delay optimized multiplier at the system level. A new and delay-efficient structure for the 4:3 counter is proposed by making use of a two-bit reordering circuit. The proposed 4:3 counter along with the 7:3 counter, full adder (FA), and half adder (HA) circuits are employed in the design of delay-efficient 8-bit and 16-bit Wallace tree multipliers (WTMs). Using Xilinx Vivado 2017.2, the designed circuits are simulated and synthesized by targeting the device ‘xc7s50fgga484-1’ of Spartan 7 family. Further, in terms of lookup table (LUT) count, critical path delay (CPD), total on-chip power, and power-delay-product (PDP), the performance of the proposed multiplier circuit is compared with the existing multipliers.

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S, Skandha Deepsita, Dhayala Kumar M, and Noor Mahammad SK. "Energy Efficient Error Resilient Multiplier Using Low-power Compressors." ACM Transactions on Design Automation of Electronic Systems 27, no. 3 (2022): 1–26. http://dx.doi.org/10.1145/3488837.

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The approximate hardware design can save huge energy at the cost of errors incurred in the design. This article proposes the approximate algorithm for low-power compressors, utilized to build approximate multiplier with low energy and acceptable error profiles. This article presents two design approaches (DA1 and DA2) for higher bit size approximate multipliers. The proposed multiplier of DA1 have no propagation of carry signal from LSB to MSB, resulted in a very high-speed design. The increment in delay, power, and energy are not exponential with increment of multiplier size ( n ) for DA1 multiplier. It can be observed that the maximum combinations lie in the threshold Error Distance of 5% of the maximum value possible for any particular multiplier of size n . The proposed 4-bit DA1 multiplier consumes only 1.3 fJ of energy, which is 87.9%, 78%, 94%, 67.5%, and 58.9% less when compared to M1, M2, LxA, MxA, accurate designs respectively. The DA2 approach is recursive method, i.e., n -bit multiplier built with n/2-bit sub-multipliers. The proposed 8-bit multiplication has 92% energy savings with Mean Relative Error Distance (MRED) of 0.3 for the DA1 approach and at least 11% to 40% of energy savings with MRED of 0.08 for the DA2 approach. The proposed multipliers are employed in the image processing algorithm of DCT, and the quality is evaluated. The standard PSNR metric is 55 dB for less approximation and 35 dB for maximum approximation.

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Shaik, Maznu. "Design and Performance Evaluation of Brent Kung Adder based 8-Bit Vedic Multiplier." International Journal for Research in Applied Science and Engineering Technology 12, no. 12 (2024): 825–30. https://doi.org/10.22214/ijraset.2024.65922.

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Multiplier is an essential functional block of a microprocessor because multiplication is needed to be performed repeatedly in almost all scientific calculations. Therefore, design of fast and low power binary multiplier is very important particularly for Digital Signal Processors. Vedic mathematics has improved the performance of multiplier. Vedic mathematics, a system of ancient Indian mathematics, which has a unique technique of solutions based on only 16 sutras. The novel point is the efficient use of Vedic algorithm (sutras) that reduces the number of computational steps considerably compared with any conventional method. This paper presents design and Performance Evaluation of Brent Kung Adder based 8-Bit Vedic Multiplier. Urdhva Tiryagbhyam sutra has been used for multiplication purpose. The partial product addition in Vedic multiplier is realized using Brent Kung Adder. Simulation results shows that described Brent Kung Adder based 8-Bit Vedic Multiplier is efficiently decreases the Delay, power consumption and Area than other multipliers.

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Tang, Xiqin, Yang Li, Chenxiao Lin, and Delong Shang. "A Low-Power Area-Efficient Precision ScalableMultiplier with an Input Vector Systolic Structure." Electronics 11, no. 17 (2022): 2685. http://dx.doi.org/10.3390/electronics11172685.

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In this paper, a small-area low-power 64-bit integer multiplier is presented, which is suitable for portable devices or wireless applications. To save the area cost and power consumption, an input vector systolic (IVS) structure is proposed based on four 16-bit radix-8 Booth multipliers and a data input scheme is proposed to reduce the number of signal transitions. This structure is similar to a systolic array in matrix multiply units of a Convolutional Neural Network (CNN), but it reduces the number of processing elements by 3/4 concerning the same vector systolic accelerator in reference. The comparison results prove that the IVS multiplier reduces at least 61.9% of the area and 45.18% of the power over its counterparts. To increase the hardware resource utilization, a Transverse Carry Array (TCA) structure for Partial Products Accumulation (PPA) was designed by replacing the 32-bit adders with 3/17-bit adders in the 16-bit multipliers. The experiment results show that the optimization could lead to at least a 6.32% and 13.65% reduction in power consumption and area cost, respectively, compared to the standard 16-bit radix-8 Booth multiplier. In the end, the precise scale of the proposed IVS multiplier is discussed. Benefiting from the modular design, the IVS multiplier can be configured to support sixteen different kinds of multiplications at a step of 16 bits [16b, 32b, 48b, 64b] × [16b, 32b, 48b, 64b].

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MISS., RUTUJA ABHANGRAO, SHILPA JADHAV MISS., PRIYANKA GHODKE MISS, and ALTAAF MULANI PROF. "DESIGN AND IMPLEMENTATION OF 8-BIT VEDIC MULTIPLIER." JournalNX - A Multidisciplinary Peer Reviewed Journal NCMTEE-2K17 (March 26, 2017): 24–26. https://doi.org/10.5281/zenodo.1451178.

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Todays technology has raised demand for fast and real time signal processing operation. Multiplication is one of the most important arithmetic operations. In this paper, we have proposed design of vedic multiplier using Urdhva Tiryagbhyam sutra in Xilinx ISE. This design takes lesser time for operation than currently available multipliers .It encompasses wide era of image processing and digital signal processing in much efficient way with increase in speed and thus leading to higher performance rating. https://journalnx.com

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Ganjikunta, Ganesh Kumar, Sibghatullah I. Khan, and M. Mahaboob Basha. "A High-Performance Signed-Unsigned Multiplier Using Vedic Mathematics." Journal of Low Power Electronics 15, no. 3 (2019): 302–8. http://dx.doi.org/10.1166/jolpe.2019.1616.

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A high speed N × N bit multiplier architecture that supports signed and unsigned multiplication operations is proposed in this paper. This architecture incorporates the modified two's complement circuits and also N × N bit unsigned multiplier circuit. This unsigned multiplier circuit is based on decomposing the multiplier circuit into smaller-precision independent multipliers using Vedic Mathematics. These individual multipliers generate the partial products in parallel for high speed operation, which are combined by using high speed adders and parallel adder to generate the product output. The proposed architecture has regular-shape for the partial product tree that makes easy to implement. Finally, this multiplier architecture is implemented in UMC 65 nm technology for N = 8, 16 and 32 bits. The synthesis results shows that the proposed multiplier architecture improves in terms of speed and also reduces power-delay product (PDP), compared to the architectures in the literature.

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Ch., Praveen Kumar, and Praveen Kumar K. "IMPLEMENTATION OF A 8 BIT HIGH PERFORMANCE MULTIPLIER USING HDL." International Journal of Advances in Engineering & Scientific Research 1, no. 6 (2014): 23–30. https://doi.org/10.5281/zenodo.10725210.

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Abstract This paper presents an area efficient implementation of a 8 bit high performance parallel multiplier.  Radix-8  Booth  multiplier  with  carry  look ahead adder and modified carry look ahead adder are presented here. The design is structured for 8   bit multiplication. Carry Look ahead Adder is used as the final adder to enhance the speed of operation. Finally the performance improvement of the proposed multipliers is validated  by  implementing  a  multiplier  with  modified carry  look  ahead  adder.  The  design  entry  is  done  in Verilog and simulated using Model Sim SE 6.4 design suite from Mentor Graphics. It is then synthesized and implemented using Xilinx ISE 9.2i .   Keywords- HDL; Modified Carry Look-ahead Adder; Carry Save Adder; Wallace Tree; Booth Encoding.

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Panda, Subodh Kumar, and Pragnya Patil. "Design of Multipliers Using Various Methods." Perspectives in Communication, Embedded-systems and Signal-processing - PiCES 5, no. 3 (2021): 49–51. https://doi.org/10.5281/zenodo.5471235.

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Multipliers are highly on demand as they are used in tremendous areas such as digital signal processing applications, image processing application , and in various Microprocessors such as ARM, NVIDIA, Intel, DSP Processors such as DM270,DM320 etc. Many researchers are urging to improve the performance of the multipliers by adopting various methods. Most of the existing papers includes the work on Array multipliers, Wallace tree multiplier, Dadda multiplier and Booth multipliers. And few recent papers include Vedic Mathematics that have implemented most commonly used Urdhva Sutra. In this paper, various methods are implemented to design a multiplier such as Booth multiplier, Modified Booth multiplier, Urdhva multiplier and Nikhilam multiplier. All the methods are used to design for 8 bit signed numbers by coding very efficiently in Verilog. This paper focuses on the design of multipliers that are very simple in structure such that there is no circuit complexity. The design is simulated using Xilinx ISE or ModelSim SE.

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Subbaiah, Madaka Venkata, and Galiveeti Umamaheswara Reddy. "Delay-efficient 4:3 counter design using two-bit reordering circuit for high-speed Wallace tree multiplier." International Journal of Electrical and Computer Engineering (IJECE) 13, no. 2 (2023): 1367. http://dx.doi.org/10.11591/ijece.v13i2.pp1367-1378.

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In many signal processing applications, multiplier is an important functional block that plays a crucial role in computation. It is always a challenging task to design the delay optimized multiplier at the system level. A new and delay-efficient structure for the 4:3 counter is proposed by making use of a two-bit reordering circuit. The proposed 4:3 counter along with the 7:3 counter, full adder (FA), and half adder (HA) circuits are employed in the design of delay-efficient 8-bit and 16-bit Wallace tree multipliers (WTMs). Using Xilinx Vivado 2017.2, the designed circuits are simulated and synthesized by targeting the device ‘xc7s50fgga484-1’ of Spartan 7 family. Further, in terms of lookup table (LUT) count, critical path delay (CPD), total on-chip power, and power-delay-product (PDP), the performance of the proposed multiplier circuit is compared with the existing multipliers.

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Yin, Ningyuan, Wanyuan Pan, Yihe Yu, Chengcheng Tang, and Zhiyi Yu. "Low-Power Pass-Transistor Logic-Based Full Adder and 8-Bit Multiplier." Electronics 12, no. 15 (2023): 3209. http://dx.doi.org/10.3390/electronics12153209.

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With the rapid development of information technology, the demand for high-speed and low-power technology for digital signal processing is increasing. Full adders and multipliers are the basic components of signal processing technology. Pass-transistor logic is a promising method for implementing full adder and multiplier circuits due to the low count of transistors and low-power characteristics. In this paper, we present a novel full adder based on pass transistors. The proposed full adder consists of 18 transistors. The post-layout simulation shows a 13.78% of power reduction compared to conventional CMOS full adders. Moreover, we propose an 8-bit signed multiplier based on the proposed full adder. The post-layout simulation shows an 8% power reduction compared to the multiplier produced by the Design Compiler synthesis tool. Compared to the existing work with a similar process, our work achieved only 19.02% of the power-delay product and 3.5% of the area-power product.

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Crawley, D. G., and G. A. J. Amaratunga. "8 × 8 bit pipelined dadda multiplier in CMOS." IEE Proceedings G (Electronic Circuits and Systems) 135, no. 6 (1988): 231. http://dx.doi.org/10.1049/ip-g-1.1988.0033.

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Padmanabhan, Khamalesh Kumar, Umadevi Seerengasamy, and Abraham Sudharson Ponraj. "High-Speed Grouping and Decomposition Multiplier for Binary Multiplication." Electronics 11, no. 24 (2022): 4202. http://dx.doi.org/10.3390/electronics11244202.

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In the computation systems that are frequently utilized in Digital Signal Processing (DSP)- and Fast Fourier transform (FFT)-based applications, binary multipliers play a crucial role. Multipliers are one of the basic arithmetic components used, and they require more hardware resources and computational time. Due to this, numerous studies have been performed so as to decrease the computational time and hardware requirements. In this research study on reducing the necessary computational time, a high-speed binary multiplier known as the Grouping and Decomposition (GD) multiplieris proposed. The proposed multiplier aims to achieve competency in processing algorithms over existing multiplier architectures through a combination of the parallel grouping of partial products of the same size and the decomposition of each grouped partial-product bit, with the final summation performed using a 5:2 logic adder (5LA). The usage of parallel processing and decomposition logic reduces the number of computation steps and hence achieves a higher speed in multiplication. The front-end and physical design implementation of the proposed GD multiplier have been executed in the 180 nm technology library using the Cadence® Virtuoso and Cadence® Virtuoso Assura tools. From the front-end design of the 8 × 8 proposed GD multiplier, it was observed that the GD multiplier achieves a reduction of approximately 56% in computation time and a reduction of 53% in power–delay product when compared to existing multiplier architectures. A further reduction in the power–delay product is achieved by the physical design implementation of the proposed multiplier due to the internal routing of subsystems with the shortest-path algorithm. The proposed multiplier works better with higher-order multiplication and is suitable for high-end applications.

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Ahmed, Rekib U., Sheba D. Thabah, Mridul Haque, and Prabir Saha. "Efficient Modulo Multiplier." Electronics ETF 27, no. 1 (2023): 18–24. http://dx.doi.org/10.53314/els2327018a.

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The paper presents the methodology to compute modulo multiplication with the moduli set 2n, 2n−1, 2n+1. In addition to this, designs of the modulo multipliers, namely 2n, 2n−1, and 2n+1 (with n = 4, 8, and 16), have been proposed which are based on half adders, full adders, 4:3 compressor, 7:3 compressor, and the multi-column compressor namely 5,5:4. The gate level design of 4:3 compressor is carried out by solving the truth table using the K-map reduction. To verify the functionalities we have implemented the proposed modulo multipliers using VHDL coding in Xilinx 14.2 design suite. Simulation using Virtex-6 device has been performed to estimate delay, power consumption, and power-delay product (PDP). Moreover, the modulo multipliers are simulated in Cadence RC compiler using 0.18 µm technology to estimate the area. One of the major contributions to the arts of this work is in the partial product reduction stage which utilizes the multi-column 5,5:4 compressor to reduce power and area. The modulo 2n−1 multiplier of operand size 4-bit shows an improvement of 66.34% in terms of area over the best-reported paper. On the other hand, the modulo 2n+1 multiplier of operand size 4-bit shows an improvement of 58.59% terms of in area and the same of operand size 8-bit shows an improvement of 22.72% over the best-reported paper. The proposed algorithms of moduli multiplication are applicable to Booth multiplication of signed numbers.

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Pant, Aruna, Adesh Kumar, and Piyush Kuchhal. "Analysis of single layer artificial neural network neuromorphic hardware chip." IAES International Journal of Robotics and Automation (IJRA) 13, no. 4 (2024): 495. http://dx.doi.org/10.11591/ijra.v13i4.pp495-505.

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The neuromorphic architectures are hardware network systems designed with neural functions. Neural networks seen in biology serve as an inspiration for network systems. A synapse connects every node or neuron in an artificial neural network (ANN) to every other node. As in biological brains, the amplitude of the linking between nodes referred to as synaptic weights will regulate the connection. In contrast to conventional design, ANN uses many highly organized dealing pieces that work together to solve real-world issues. The design of the neuromorphic hardware chip is discussed in the paper. The target device used is a Virtex-5 Field Programmable Gate Array (FPGA) and the simulation is taken on Xilinx ModelSim software. This chip is designed for 20 neuron inputs, each of the neuron inputs is 8-bit. Each 20-neuron input is multiplied by 20 input weights and each weight is 8-bit so when these 20 input weights are multiplied by 20 neuron inputs in the multiplier it gives 16-bit output. A control logic is used in this neuromorphic hardware chip design which is used to feed multiplier output to each input of the hidden layer. The system-level outcome of the hidden layer is then given to the multiplexer which has 20 inputs and one single output. The multiplexer is used to select any of the 20 outputs of the control logic. Finally, to gain an understanding of the performance of this neuromorphic hardware chip, we have computed the hardware utilization parameters. These parameters include slices, input/output blocks (IOBs), registers used, memory, and the overall propagation delay used by the hardware chip.

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Pant, Aruna, Adesh Kumar, and Piyush Kuchhal. "Analysis of single layer artificial neural network neuromorphic hardware chip." IAES International Journal of Robotics and Automation 13, no. 4 (2024): 495–505. https://doi.org/10.11591/ijra.v13i4.pp495-505.

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Nittala, Vijay Bhaskar, Anisha Bomma, and M. Ramana Reddy. "Energy Efficient Approximate 8-bit Vedic Multiplier." International Journal for Research in Applied Science and Engineering Technology 10, no. 9 (2022): 1453–65. http://dx.doi.org/10.22214/ijraset.2022.46861.

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Abstract: The digital signal processing and its classification applications on the energy constrained devices should be supported based on efficiency. Because such applications must perform highly complex computations especially complex multiplication processes while exhibiting tolerance for a large amount of noise and for computational errors too. So, comparing all the arithmetic computations, improving the energy efficiency of multiplication is critical. In this project, an energy efficient approximate 8-bit Vedic multiplier is proposed which gives a tradeoff between computational accuracy and energy consumption. The proposed architecture has reduced area compared to other multiplier architectures which process same number of bits. The reduced architecture area reduces the power consumption. Also, the Vedic technology adopted for the multiplication reducesthe delay further. But the approximate architecture output possesses a small amount of computational accuracy which is negligible for DSP applications.

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Jagadeeswara Rao, E., K. Jayaram Kumar, and Dr T. V. Prasad. "Design of high speed Wallace tree multiplier using 8-2 and 4-2 adder compressors." International Journal of Engineering & Technology 7, no. 4 (2018): 2386. http://dx.doi.org/10.14419/ijet.v7i4.12261.

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Multiplication is one of the most common arithmetic operations employed in digital systems such as FIR filters and DSP processors but multipliers are the most time, area, and power consuming circuits. Improvement in any of these parameters can be advantageous for improv-ing the efficiency of the circuit. High-speed multiplier which uses the high-speed adder is designed based on the Wallace tree concept in this paper. In this paper first we present an approach towards the reduction of delay in Wallace tree multipliers by using 8:2 and 4:2 adder com-pressors, in the partial product reduction stage. The proposed design is also compared to the Wallace Tree multiplier which uses 4:2 and 8:2 adder compressors in terms of propagation delay. The proposed design enhances speed of the system by 74.1% compared to the conven-tional Wallace Tree multiplier, while 24.1 % reduction was achieved in the delay of the system relative to Wallace tree multiplier with 16-bit adder with one of the 8-2 adder compressors.

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Lin, Rong. "A Regularly Structured Parallel Multiplier with Low-power Non-binary-logic Counter Circuits." VLSI Design 12, no. 3 (2001): 377–90. http://dx.doi.org/10.1155/2001/97598.

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A highly regular parallel multiplier architecture along with the novel low-power, high-performance CMOS implementation circuits is presented. The superiority is achieved through utilizing a unique scheme for recursive decomposition of partial product matrices and a recently proposed non-binary arithmetic logic as well as the complementary shift switch logic circuits.The proposed 64×64-b parallel multiplier possesses the following distinct features: (1) generating 64 8×8-b partial product matrices instead of a single large one; (2) comprising only four stages of bit reductions: first, by 8×8-b small parallel multipliers, then, by small parallel counters in each of the remaining three stages. A family of shift switch parallel counters, including non-binary (6, 3)∗ and complementary (k, 2) for 2 ≤ k ≤ 8, are proposed for the efficient bit reductions; (3) using a simple final adder.The non-binary logic operates 4-bit state signals (representing integers ranging from (0 to 3), where no more than half of the signal bits are subject to value-change at any logic stage. This and others including minimum transistor counts, fewer inverters, and low-leakage logic structure, significantly reduce circuit power dissipation.

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Rizos, Ioannis, Georgios Papatheodorou, and Aristides Efthymiou. "Designing Approximate Reduced Complexity Wallace Multipliers." Electronics 14, no. 2 (2025): 333. https://doi.org/10.3390/electronics14020333.

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In the nano-scale era, enhancing speed while minimizing power consumption and area is a key objective in integrated circuits. This demand has motivated the development of approximate computing, particularly useful in error-tolerant applications such as multimedia, machine learning, signal processing, and scientific computing. In this research, we present a novel method to create approximate integer multiplier circuits. This work is based on a modification of the well-known Wallace tree multiplier, called the Reduced Complexity Wallace Multiplier (RCWM). Approximation is introduced by replacing conventional Full Adders with approximate ones during the partial product reduction phase. This research investigates the characteristics of 8×8-, 16×16-, and 32×32-bit Approximate Reduced Complexity Wallace Multipliers (ARCWM), evaluating their accuracy, area usage, delay, and power consumption. Given the vast search space created by different combinations and placements of these approximate Adders, a Genetic Algorithm was used to efficiently explore this space and optimize the ARCWMs. The resulting ARCWMs have an area reduction of up to 65% and a power consumption reduction of up to 70%, with no worse delay than the RCWM. Multipliers created with this method can be used in any application that requires parallel multiplication, such as neural accelerators, trading accuracy for area and power reduction. Additionally, an ARCWM can be used alongside a slow shift-and-accumulate multiplier trading off accuracy for faster calculation. This methodology provides valuable guidance for designers in selecting the optimal configuration of approximate Full Adders, tailored to the specific requirements of their applications. Alongside the methodology, we provide all of the tools used to achieve our results as open-source code, including the Register-Transfer Level (RTL) code of the 8×8-, 16×16-, and 32×32-bit Wallace Multipliers.

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Etiemble, Daniel, and Ramzi A. Jaber. "Design of (3,2) and (4,2) CNTFET Ternary Counters for Multipliers." Asian Journal of Research in Computer Science 16, no. 3 (2023): 103–18. http://dx.doi.org/10.9734/ajrcos/2023/v16i3349.

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The reduction trees of combinational multipliers are widely applying counters. To be able to compare the ternary and the binary approaches, Nanotube Field-Effect Transistor (CNTFET) ternary (3,2) and ternary (4,2) counters have been designed. The ternary (4,2) counter is compared with the binary (7,3) counter as both compute approximately the same amount of information. The binary counter is more efficient. However, comparing counters is not enough: in the Wallace reduction tree of the ternary multiplier, there are two times more lines to reduce compared to the binary one, as a 1-trit multiplier generates both product and carry terms. Comparing the Wallace tree of an 8*8-trit multiplier and a 12*12-bit binary one also shows that the binary implementation is the most efficient.

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Dhanasekar, J., and V. K. Sudha. "Implementation of Energy Effective Error Resistant Adders and Multipliers in Image Denoising Applications." Journal of Nanoelectronics and Optoelectronics 18, no. 1 (2023): 33–42. http://dx.doi.org/10.1166/jno.2023.3371.

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The design of digital VLSI circuits must take energy efficiency into consideration. Reducing the circuit’s power consumption, which has been a major issue since 2000, would increase the necessity for energy efficiency. Error-tolerant systems heavily rely on approximate computation methods to increase power efficiency. The key factors of the system’s overall power consumption and area computation are adders and multipliers, which are also crucial in approximate computing. High energy-efficiency adders can be used to create additional multipliers. In order to dramatically minimize power consumption, this work builds and implements 8×8 Dadda multipliers using 1 bit approximation adders. Calculation is sped up by using the Dadda multiplier. In turn, by reducing propagation latency, the suggested design lowers power consumption in digital CMOS circuitry. The proposed multiplier design with approximate adders, which was created in Verilog HDL, simulated in FPGA, and synthesized in FPGA platform, is implemented on an ASIC platform using Cadence 90 nm Technology. The Gaussian filter additionally employs the proposed Dadda multiplier for picture denoising in approximation adder-based image processing applications.

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Satria, Brama Yoga, Munawar Agus Riyadi, and Muhammad Arfan. "PERANCANGAN MULTIPLIER SEKUENSIAL 8-BIT DENGAN TEKNOLOGI 180NM MENGGUNAKAN PERANGKAT LUNAK ELECTRIC." TRANSIENT 6, no. 3 (2017): 476. http://dx.doi.org/10.14710/transient.6.3.476-482.

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Very Large Scale Integration (VLSI) merupakan proses dari pembuatan sirkuit terpadu atau Integrated Circuit (IC) dengan cara menggabungkan ribuan rangkaian berbasis transistor ke dalam sebuah chip atau prosesor. Dengan adanya VLSI, ukuran dari devais elektronik berbasis transistor dapat dimampatkan agar menghemat area, biaya produksi, dan efek parasitik. Prosesor terdiri dari beberapa blok utama sebagai penunjang kerjanya, salah satu blok yang paling penting yaitu Arithmatic Logic Unit (ALU). Salah satu contoh dari ALU sendiri yaitu adalah multiplier. Multiplier sangat penting untuk banyak dasar proses dari sebuah prosesor. Tujuan dari penelitian ini adalah merancang sebuah multiplier sekuensial 8-bit dengan teknologi 180nm. Multiplier dirancang dengan menggabungkan blok-blok pembangun seperti blok counter, adder, shift register, dan lain-lainnya. Penelitian ini menggunakan perangkat lunak electric untuk mendesain layout dan perangkat lunak LT-Spice untuk menguji fungsional, delay, dan kinerja dari hasil ekstraksi layout. Hasil perancangan ini secara fungsional telah berjalan dengan baik. Multiplier yang dirancang memiliki layout sebesar 3.725.150 lambda2 dengan nilai delay sebesar 4,428ns. Selain itu, frekuensi maksimum yang digunakan untuk mendapatkan hasil yang benar dari multiplier sekuensial 8-bit yaitu 50MHz.

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Gonoi, K., I. Honbori, M. Wada, K. Togashi, and Y. Kato. "A GaAs 8×8-bit multiplier/accumulator using JFET DCFL." IEEE Journal of Solid-State Circuits 21, no. 4 (1986): 523–29. http://dx.doi.org/10.1109/jssc.1986.1052566.

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Bermak, A., D. Martinez, and J. L. Noullet. "High-density 16/8/4-bit configurable multiplier." IEE Proceedings - Circuits, Devices and Systems 144, no. 5 (1997): 272. http://dx.doi.org/10.1049/ip-cds:19971478.

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Hatamian, M., та G. L. Cash. "A 70-MHz 8-bit×8-bit parallel pipelined multiplier in 2.5-μm CMOS". IEEE Journal of Solid-State Circuits 21, № 4 (1986): 505–13. http://dx.doi.org/10.1109/jssc.1986.1052564.

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Saha, Aloke, Rahul Pal, and Jayanta Ghosh. "Novel Self-Pipelining Approach for Speed-Power Efficient Reliable Binary Multiplication." Micro and Nanosystems 12, no. 3 (2020): 149–58. http://dx.doi.org/10.2174/1876402911666190916155445.

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Background: The present study explores a novel self-pipelining strategy that can enhance speed-power efficiency as well as the reliability of a binary multiplier as compared to state-of-art register and wavepipelining. Method: Proper synchronization with efficient clocking between the subsequent self-pipelining stages has been assured to design a self-pipelined multiplier. Each self-pipelining stage consists of self-latching leaf cells that are designed, optimized and evaluated by TSMC 0.18μm CMOS technology with 1.8V supply rail and at 25°C temperature. The T-Spice transient response and simulated results for the designed circuits are presented. The proposed idea has been applied to design 4-b×4-b self-pipelined Wallace- tree multiplier. The multiplier was validated for all possible test patterns and the transient response was evaluated. The circuit performance in terms of propagation delay, average power and Power-Delay- Product (PDP) is recorded. Next, the decomposition logic is applied to design a higher-order multiplier (i.e., 8-bit×8-bit and 16-bit×16-bit) based on the proposed strategy using 4-bit×4-bit self-pipelined multiplier. The designed multiplier was also validated through extensive TSpice simulation for all the required test patterns using W-Edit and the evaluated performance is presented. All the designs, optimizations and evaluations performed are based on BSIM3 device parameter of TSMC 0.18μm CMOS technology with 1.8V supply rail at 25°C temperature using S-Edit of Tanner EDA. Results: The reliability was investigated of the proposed 4-b×4-b multiplier in the temperature range - 40°C to 100°C for maximum PDP variation. Conclusion: A benchmarking analysis in terms of speed-power performance with recent competitive design reveals preeminence of the proposed technique.

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Balasubramanian, Padmanabhan, Raunaq Nayar, Okkar Min, and Douglas L. Maskell. "Digital Image Blending by Inexact Multiplication." Electronics 11, no. 18 (2022): 2868. http://dx.doi.org/10.3390/electronics11182868.

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Digital image blending is commonly used in applications such as photo editing and computer graphics where two images are combined to produce a desired blended image. Digital images can be blended by addition or multiplication, and usually exact addition or multiplication is performed for image blending. In this paper, we evaluate the usefulness of inexact multiplication for digital image blending. Towards this, we describe how an exact array multiplier can be made inexact by introducing vertical cut(s) in it and assigning distinct combinations of binary values to the dangling inputs and product bits. We considered many 8-bit digital images for blending and the blended images obtained using exact and inexact multipliers are shown, which demonstrates the usefulness of inexact multiplication for image blending. For 8 × 8 image blending, one of our inexact array multipliers viz. IAM01-VC8 was found to achieve 63.3% reduction in area, 21% reduction in critical path delay, 72.3% reduction in power dissipation, and 78.1% reduction in energy compared to the exact array multiplier. In addition, IAM01-VC8 achieved 60.6% reduction in area, 9.7% reduction in critical path delay, 64.7% reduction in power dissipation, and 68.1% reduction in energy compared to the high-speed exact 8 × 8 multiplier that was automatically synthesized using a logic synthesis tool. The exact and inexact multipliers were physically realized using 32/28 nm CMOS process technology.

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PERRI, STEFANIA, MARIA ANTONIA IACHINO, and PASQUALE CORSONELLO. "SIMD MULTIPLIERS FOR ACCELERATING EMBEDDED PROCESSORS IN FPGAs." Journal of Circuits, Systems and Computers 15, no. 04 (2006): 537–50. http://dx.doi.org/10.1142/s0218126606003210.

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This paper describes a new efficient 32×32 Single Instruction Multiple Data (SIMD) multiplier suitable for the multimedia extension of FPGA-based processors. The proposed circuit can adapt itself to 32-, 16-, and 8-bit operands widths avoiding time and power consuming reconfiguration. When implemented in an XCV400 device, the multiplier here described reaches a running frequency of about 97 MHz with an energy dissipation of just 20 mW/MHz. Comparisons with previously proposed SIMD multipliers for FPGA-based designs demonstrate that the new circuit allows the best area-time-power trade-off to be obtained.

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sundhar, shyam. "Design and FPGA Implementation of 4×4 Vedic Multiplier using Different Architectures." International Scientific Journal of Engineering and Management 03, no. 04 (2024): 1–9. http://dx.doi.org/10.55041/isjem01526.

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The need of high speed multiplier is increasing as the need of high speed processors are increasing. A Multiplier is one of the key hardware blocks in most of the fast processing systems which is not only a high delay block but also a major source of power dissipation. A conventional processor requires substantially more hardware resources and processing time in the multiplication operation, rather than addition and subtraction. This Project describes about the design of 4-bit, 8-bit and 32-bit Vedic multiplier using ancient Vedic mathematics which helps in delay and power reduction. Simulation is done in Xilinx VIVADO software using VHDL and display on LCD. The results for Vedic multiplier using various architecture and their delay comparison are done. Key Words: FPGA (Artix-7), adders, 4x4 Array Multiplier, Vedic Mathematics

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AliAsgar, Syed, and A. Yasmine Begum. "Designing RNS-based FIR filter with Optimal area, Delay, and Power via the use of Swift Adders and Swift Multipliers." International Journal of Electrical and Electronics Research 12, no. 4 (2024): 1211–21. https://doi.org/10.37391/ijeer.120412.

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Based on the Residue Number System (RNS), Finite Impulse Response filters have gained prominence in digital signal processing due to their efficiency in handling complex computations. This work presents a comprehensive analysis on optimizing area, delay, and power in the FIR filter by exploring different adders and multipliers. Three prominent adders, namely Ripple Carry Adder, Kogge Stone Adder, and Proposed Adder, are evaluated for their impact on area and delay. The choice of adder influences the overall performance of the FIR filter, and a careful selection is made based on the trade-offs between area and delay. Furthermore, various multipliers, including Booth, Baugh-Wooley, Braun, and Array, are compared in terms of their efficiency in power consumption. Multipliers contribute significantly to the overall power consumption, and the analysis involves selecting the most suitable multiplier for achieving the desired power optimization. The various arrangements of swift adders and swift multipliers were suggested and executed in the Finite Impulse Response (FIR) filter and then the RNS algorithm was applied to it. The comparison of 8-tap 8-bit of the proposed adder with the array multiplier shows that the area is reduced by 52.70% with other combinations and by comparing the RCA adder with the array multiplier, the critical path delay is reduced by 38.51% and the maximum frequency is produced by the KSA adder with Braun multiplier which is increased by 29.78% with other combinations.

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Jiménez Pérez, Abimael, Marco Antonio Gurrola Navarro, Víctor Manuel Valenzuela De la Cruz, José Antonio Muñoz Góme, and Omar Aguilar Loreto. "VLSI Design and Comparative Analysis of Several Types of Fixed and Simple Precision Floating Point Multipliers." Cultura Científica y Tecnológica 18, no. 1 (2021): 1–9. http://dx.doi.org/10.20983/culcyt.2021.1.2.4.

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Multiplication is an arithmetic operation that has a meaningful impact on the performance of several real-life applications, such as digital signal and image processing. Analysis and comparison of different types of fixed-point multipliers such as Wallace tree, array, and Booth-2 with truncated and non-truncated versions were included in this design. Fixed-point multipliers were used to design floating-point multipliers through a hardware description language. As a result, area and speed values were analyzed. Booth-2 fixed multiplier with truncation and RCA adders present both the longest delay and the largest area consumption. Wallace tree floating-point multiplier required the smallest area and the shortest delay. The 8-bit versions of fixed-point multipliers were physically synthesized, using the Alliance tools, to obtain the layout of the circuits. The integrated circuits were successfully fabricated in a 0.5-μm CMOS technology.

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Lee, J. Y., H. L. Garvin, and C. W. Slayman. "A high-speed high-density silicon 8×8-bit parallel multiplier." IEEE Journal of Solid-State Circuits 22, no. 1 (1987): 35–40. http://dx.doi.org/10.1109/jssc.1987.1052668.

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SATYANARAYANA, JANARDHAN H., and BEHROUZ NOWROUZIAN. "DESIGN AND FPGA IMPLEMENTATION OF DIGIT-SERIAL MODIFIED BOOTH MULTIPLIERS." Journal of Circuits, Systems and Computers 06, no. 05 (1996): 485–501. http://dx.doi.org/10.1142/s0218126696000339.

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This paper presents a comprehensive approach to the ASIC design of general digit-size digit-serial modified Booth multipliers, together with corresponding hardware implementations employing the Actel 1.2 µ FPGA technology. The proposed design is based on a decomposition of the N-bit multiplier and the M-bit multiplicand each into a unique set of D radix-2D components. The decomposed multiplicand components are then combined with the modified Booth encoded multiplier components to form the desired product. Analytical expressions are derived for the total number of gate-equivalents in the corresponding FPGA implementations in terms of D and N. Similarly, by using a critical path analysis, analytical expressions are derived for the maximum possible bit-clock rate in terms of D. These results are then combined to arrive at the efficiency of the implementation quantified by the throughput per unit area as a function of the digit-size D (with the wordlength L being taken as a parameter). It is shown that for wordlengths in the range 16≤L≤22, the digit-size falls somewhere in the range 3≤D≤8 for optimal throughput per unit area, where L=min{M, N}. Viewlogic simulation results are presented to verify the proposed digit-serial modified Booth multipliers.

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Hernández Ortega, Andres Gonzálo, Braian Stiven Avella Rivera, Oscar Fernando Vera, and Jorge Orlando Bareño Quintero. "An in-depth-examination: comparative analysis of multiplication hardware accelerator algorithms in VHDL for 8-Bit Systems (WTM), (PBM) and (BWM) synthesized on an ALTERA-CYCLONE-II-DE1-Board." Ingenieria Solidaria 20, no. 2 (2024): 1–29. https://doi.org/10.16925/2357-6014.2024.02.10.

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This article presents an implementation and comparative analysis of 8-bit Wallace Tree Multiplier (WTM), Parallel Booth Multiplier (PBM), and Baugh-Wooley Multiplier (BWM) algorithms.Introduction: this article results from research conducted for a Master’s degree in Engineering at the Pedagogical and Technological University of Colombia (UPTC) between 2022 and 2024. It analyzes and compares the performan-ce of three multiplication algorithms (WTM, PBM, and BWM), focusing on variables such as operation time and the number of logical elements used.Problem:computing has advanced rapidly, enabling multiple operations on a single chip. This has increased the demand for components that execute tasks quickly while occupying minimal space. Multipliers are crucial in appli-cations such as filters, DSP circuits, and fast Fourier transforms.Objective: to analyze and compare the performance of three multiplication algorithms—WTM, PBM, and BWM—tai-lored for 8-bit systems.Methodology: the research methodology was designed to ensure robustness and reliability. It began with formulating objectives and identifying key variables. Articles were selected based on their contributions to understanding multi-plication algorithms and programming languages. The research included designing and comparing 8-bit multiplier algorithms (WTM, PBM, and BWM).Results:an analysis of the results identified the variables that contributed to significant performance improvements for each algorithm.Conclusions: t h e p r o j e c t s u c c e s s f u l l y i m p r o v e d t h e e f fi c i e n c y o f t h e a l g o r i t h m s b y u t i l i z i n g v a r i o u s r e g i s t e r s h i f t s a n d multipliers based on the operational case that benefited them the most. It achieved improvements in both efficiency and operation time concerning the use of logical elements.Originality: this research formulates strategies for applying and comparing multiplication algorithms, differentiating data processing based on specific data characteristics.Limitations:• The lack of testing systems for the implementations.• The study focused on comparing three multiplication algorithms, limiting generalizability.• Performance metrics.

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Sever, Refik, and Murat Askar. "A 5 GHz 8×8-Bit Multiplier Using Wave Component Sampling Method." Advanced Science Letters 19, no. 5 (2013): 1426–29. http://dx.doi.org/10.1166/asl.2013.4488.

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Dorojevets, M., A. K. Kasperek, N. Yoshikawa, and A. Fujimaki. "20-GHz 8 $\times$ 8-bit Parallel Carry-Save Pipelined RSFQ Multiplier." IEEE Transactions on Applied Superconductivity 23, no. 3 (2013): 1300104. http://dx.doi.org/10.1109/tasc.2012.2227648.

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C, Hema, Shravani G, P. Sivaphaneendra, Sinchana ., and Soundarya L. "Implementation of Hardware and Energy Efficient Approximate Multiplier Architectures Using 4-2 Compressor for Images." International Journal for Research in Applied Science and Engineering Technology 11, no. 4 (2023): 2177–83. http://dx.doi.org/10.22214/ijraset.2023.50528.

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Abstract: Approximate computing is tentatively applied in some digital signal processing applications which have an inherent tolerance for erroneous computing results. The approximate arithmetic blocks are utilized in them to improve the electrical performance of these circuits. Multiplier is one of the fundamental units in computer arithmetic blocks. Moreover, the 4-2 compressors are widely employed in the parallel multipliers to accelerate the compression process of partial products. In this brief, three novel approximate 4-2 compressors are proposed and utilized in 8-bit multipliers. Meanwhile, an error-correcting module (ECM) is presented to promote the error performance of approximate multiplier with the proposed 4-2 compressors. In this brief, the number of the approximate 4-2 compressor’s outputs is innovatively reduced to one, which brings further improvements in the energy-efficiency. This Design is implemented using Verilog HDL and simulated by Modelsim 6.4 c and synthesized by Xilinx tool.

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Bowlyn, Kevin, Sena Hounsinou, and Jordan Tewell. "An efficient Radix-4 butterfly structure based on the complex binary number system and distributed arithmetic." International Journal of Electrical and Computer Engineering (IJECE) 15, no. 1 (2025): 174. http://dx.doi.org/10.11591/ijece.v15i1.pp174-185.

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Complex number arithmetic is pivotal in various applications, requiring the selection of an efficient multiplier for high-performance computations. Fast Fourier transform (FFT)-based multipliers are widely employed for computing complex number products, but their reliance on using dedicated multipliers and treating the real and imaginary parts as two entities significantly add to the cost and complexity of the system. Distributed arithmetic (DA) is a technique that replaces complex multiplications with a bit-level shift and addition mechanism. The complex binary number system (CBNS) utilizes binary arithmetic, which treats the real and imaginary parts as a single entity, which can simplify complex number arithmetic and computations. This paper introduces an approach integrating the CBNS with DA in a Radix-4 decimation in time FFT 8-bit and 16-bit butterfly structure. The proposed design significantly reduces arithmetic computations and eliminates dedicated multipliers, demonstrating a reduction in power consumption, area size, and lookup tables, as well as increasing overall clock performance compared to the conventional FFT architecture on Artix-7, Kintex-7, and Virtex-7 field-programmable gate array chips.

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Adiono, Trio, Hans Herdian, Suksmandhira Harimurti, and Tengku Ahmad Madya Putra. "Design of Compact Modified Radix-4 8-Bit Booth Multiplier." International Journal on Electrical Engineering and Informatics 12, no. 2 (2020): 228–41. http://dx.doi.org/10.15676/ijeei.2020.12.2.4.

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Zhong, Xiongguang, and Mengtian Rong. "An asynchronous 32×8-bit multiplier based on LDCVSPG logic." Wuhan University Journal of Natural Sciences 12, no. 2 (2007): 294–98. http://dx.doi.org/10.1007/s11859-006-0045-x.

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Tan, Tuy Nguyen, and Hanho Lee. "Efficient-Scheduling Parallel Multiplier-Based Ring-LWE Cryptoprocessors." Electronics 8, no. 4 (2019): 413. http://dx.doi.org/10.3390/electronics8040413.

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This paper presents a novel architecture for ring learning with errors (LWE) cryptoprocessors using an efficient approach in encryption and decryption operations. By scheduling multipliers to work in parallel, the encryption and decryption time are significantly reduced. In addition, polynomial multiplications are conducted using radix-2 and radix-8 multiple delay feedback (MDF) architecture-based number theoretic transform (NTT) multipliers to speed up the multiplication operation. To reduce the hardware complexity of an NTT multiplier, three bit-reverse operations during the NTT and inverse NTT (INTT) processes are removed. Polynomial additions in the ring-LWE encryption phase are also arranged to work simultaneously to reduce the latency. As a result, the proposed efficient-scheduling parallel multiplier-based ring-LWE cryptoprocessors can achieve higher throughput and efficiency compared with existing architectures. The proposed ring-LWE cryptoprocessors are synthesized and verified using Xilinx VIVADO on a Virtex-7 field programmable gate array (FPGA) board. With security parameters n = 512 and q = 12,289, the proposed cryptoprocessors using radix-2 single-path delay feedback (SDF), radix-2 MDF, and radix-8 MDF multipliers perform encryption in 4.58 μ s, 1.97 μ s, and 0.89 μ s, and decryption in 4.35 μ s, 1.82 μ s, and 0.71 μ s, respectively. A comparison of the obtained throughput and efficiency with those of previous studies proves that the proposed cryptoprocessors achieve a better performance.

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