Relevant bibliographies by topics / Application to low power graphs algorithm

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Book chapters
  4. Conference papers

Academic literature on the topic 'Application to low power graphs algorithm'

Author: Grafiati
Published: 28 May 2022

Create a spot-on reference in APA, MLA, Chicago, Harvard, and other styles

Select a source type:

Consult the lists of relevant articles, books, theses, conference reports, and other scholarly sources on the topic 'Application to low power graphs algorithm.'

Next to every source in the list of references, there is an 'Add to bibliography' button. Press on it, and we will generate automatically the bibliographic reference to the chosen work in the citation style you need: APA, MLA, Harvard, Chicago, Vancouver, etc.

You can also download the full text of the academic publication as pdf and read online its abstract whenever available in the metadata.

Journal articles on the topic "Application to low power graphs algorithm"

1

Min, Seunghwan, Sung Gwan Park, Kunsoo Park, Dora Giammarresi, Giuseppe F. Italiano, and Wook-Shin Han. "Symmetric continuous subgraph matching with bidirectional dynamic programming." Proceedings of the VLDB Endowment 14, no. 8 (April 2021): 1298–310. http://dx.doi.org/10.14778/3457390.3457395.

Full text
Abstract:
In many real datasets such as social media streams and cyber data sources, graphs change over time through a graph update stream of edge insertions and deletions. Detecting critical patterns in such dynamic graphs plays an important role in various application domains such as fraud detection, cyber security, and recommendation systems for social networks. Given a dynamic data graph and a query graph, the continuous subgraph matching problem is to find all positive matches for each edge insertion and all negative matches for each edge deletion. The state-of-the-art algorithm TurboFlux uses a spanning tree of a query graph for filtering. However, using the spanning tree may have a low pruning power because it does not take into account all edges of the query graph. In this paper, we present a symmetric and much faster algorithm SymBi which maintains an auxiliary data structure based on a directed acyclic graph instead of a spanning tree, which maintains the intermediate results of bidirectional dynamic programming between the query graph and the dynamic graph. Extensive experiments with real and synthetic datasets show that SymBi outperforms the state-of-the-art algorithm by up to three orders of magnitude in terms of the elapsed time.
APA, Harvard, Vancouver, ISO, and other styles
2

Mittal, Varsha, Durgaprasad Gangodkar, and Bhaskar Pant. "K-Graph: Knowledgeable Graph for Text Documents." Journal of KONBiN 51, no. 1 (March 1, 2021): 73–89. http://dx.doi.org/10.2478/jok-2021-0006.

Full text
Abstract:
Abstract Graph databases are applied in many applications, including science and business, due to their low-complexity, low-overheads, and lower time-complexity. The graph-based storage offers the advantage of capturing the semantic and structural information rather than simply using the Bag-of-Words technique. An approach called Knowledgeable graphs (K-Graph) is proposed to capture semantic knowledge. Documents are stored using graph nodes. Thanks to weighted subgraphs, the frequent subgraphs are extracted and stored in the Fast Embedding Referral Table (FERT). The table is maintained at different levels according to the headings and subheadings of the documents. It reduces the memory overhead, retrieval, and access time of the subgraph needed. The authors propose an approach that will reduce the data redundancy to a larger extent. With real-world datasets, K-graph’s performance and power usage are threefold greater than the current methods. Ninety-nine per cent accuracy demonstrates the robustness of the proposed algorithm.
APA, Harvard, Vancouver, ISO, and other styles
3

Tafesse, Bisrat, and Venkatesan Muthukumar. "Framework for Simulation of Heterogeneous MpSoC for Design Space Exploration." VLSI Design 2013 (July 11, 2013): 1–16. http://dx.doi.org/10.1155/2013/936181.

Full text
Abstract:
Due to the ever-growing requirements in high performance data computation, multiprocessor systems have been proposed to solve the bottlenecks in uniprocessor systems. Developing efficient multiprocessor systems requires effective exploration of design choices like application scheduling, mapping, and architecture design. Also, fault tolerance in multiprocessors needs to be addressed. With the advent of nanometer-process technology for chip manufacturing, realization of multiprocessors on SoC (MpSoC) is an active field of research. Developing efficient low power, fault-tolerant task scheduling, and mapping techniques for MpSoCs require optimized algorithms that consider the various scenarios inherent in multiprocessor environments. Therefore there exists a need to develop a simulation framework to explore and evaluate new algorithms on multiprocessor systems. This work proposes a modular framework for the exploration and evaluation of various design algorithms for MpSoC system. This work also proposes new multiprocessor task scheduling and mapping algorithms for MpSoCs. These algorithms are evaluated using the developed simulation framework. The paper also proposes a dynamic fault-tolerant (FT) scheduling and mapping algorithm for robust application processing. The proposed algorithms consider optimizing the power as one of the design constraints. The framework for a heterogeneous multiprocessor simulation was developed using SystemC/C++ language. Various design variations were implemented and evaluated using standard task graphs. Performance evaluation metrics are evaluated and discussed for various design scenarios.
APA, Harvard, Vancouver, ISO, and other styles
4

Lakshmi, B., and A. S. Dhar. "CORDIC Architectures: A Survey." VLSI Design 2010 (March 31, 2010): 1–19. http://dx.doi.org/10.1155/2010/794891.

Full text
Abstract:
In the last decade, CORDIC algorithm has drawn wide attention from academia and industry for various applications such as DSP, biomedical signal processing, software defined radio, neural networks, and MIMO systems to mention just a few. It is an iterative algorithm, requiring simple shift and addition operations, for hardware realization of basic elementary functions. Since CORDIC is used as a building block in various single chip solutions, the critical aspects to be considered are high speed, low power, and low area, for achieving reasonable overall performance. In this paper, we first classify the CORDIC algorithm based on the number system and discuss its importance in the implementation of CORDIC algorithm. Then, we present systematic and comprehensive taxonomy of rotational CORDIC algorithms, which are subsequently discussed in depth. Special attention has been devoted to the higher radix and flat techniques proposed in the literature for reducing the latency. Finally, detailed comparison of various algorithms is presented, which can provide a first-order information to designers looking for either further improvement of performance or selection of rotational CORDIC for a specific application.
APA, Harvard, Vancouver, ISO, and other styles
5

CHOI, YOONSEO, and TAEWHAN KIM. "BINDING ALGORITHM FOR POWER OPTIMIZATION BASED ON NETWORK FLOW METHOD." Journal of Circuits, Systems and Computers 11, no. 03 (June 2002): 259–71. http://dx.doi.org/10.1142/s0218126602000422.

Full text
Abstract:
We propose an efficient binding algorithm for power optimization in behavioral synthesis. In prior work, it has been shown that several binding problems for low-power can be formulated as multi-commodity flow problems (due to an iterative execution of data flow graph) and be solved optimally. However, since the multi-commodity flow problem is NP-hard, the application is limited to a class of small sized problems. To overcome the limitation, we address the problem of how we can effectively make use of the property of efficient flow computations in a network so that it is extensively applicable to practical designs while producing close-to-optimal results. To this end, we propose a two-step procedure, which (1) determines a feasible binding solution by partially utilizing the computation steps for finding a maximum flow of minimum cost in a network and then (2) refines it iteratively. Experiments with a set of benchmark examples show that the proposed algorithm saves the run time significantly while maintaining close-to-optimal bindings in most practical designs.
APA, Harvard, Vancouver, ISO, and other styles
6

Durcek, Viktor, Michal Kuba, and Milan Dado. "Investigation of random-structure regular LDPC codes construction based on progressive edge-growth and algorithms for removal of short cycles." Eastern-European Journal of Enterprise Technologies 4, no. 9(112) (August 31, 2021): 46–53. http://dx.doi.org/10.15587/1729-4061.2021.225852.

Full text
Abstract:
This paper investigates the construction of random-structure LDPC (low-density parity-check) codes using Progressive Edge-Growth (PEG) algorithm and two proposed algorithms for removing short cycles (CB1 and CB2 algorithm; CB stands for Cycle Break). Progressive Edge-Growth is an algorithm for computer-based design of random-structure LDPC codes, the role of which is to generate a Tanner graph (a bipartite graph, which represents a parity-check matrix of an error-correcting channel code) with as few short cycles as possible. Short cycles, especially the shortest ones with a length of 4 edges, in Tanner graphs of LDPC codes can degrade the performance of their decoding algorithm, because after certain number of decoding iterations, the information sent through its edges is no longer independent. The main contribution of this paper is the unique approach to the process of removing short cycles in the form of CB2 algorithm, which erases edges from the code's parity-check matrix without decreasing the minimum Hamming distance of the code. The two cycle-removing algorithms can be used to improve the error-correcting performance of PEG-generated (or any other) LDPC codes and achieved results are provided. All these algorithms were used to create a PEG LDPC code which rivals the best-known PEG-generated LDPC code with similar parameters provided by one of the founders of LDPC codes. The methods for generating the mentioned error-correcting codes are described along with simulations which compare the error-correcting performance of the original codes generated by the PEG algorithm, the PEG codes processed by either CB1 or CB2 algorithm and also external PEG code published by one of the founders of LDPC codes
APA, Harvard, Vancouver, ISO, and other styles
7

Geoff Rideout, D., Jeffrey L. Stein, and Loucas S. Louca. "Systematic Identification of Decoupling in Dynamic System Models." Journal of Dynamic Systems, Measurement, and Control 129, no. 4 (October 24, 2006): 503–13. http://dx.doi.org/10.1115/1.2745859.

Full text
Abstract:
This paper proposes a technique to quantitatively and systematically search for decoupling among elements of a dynamic system model, and to partition models in which decoupling is found. The method can validate simplifying assumptions based on decoupling, determine when decoupling breaks down due to changes in system parameters or inputs, and indicate required model changes. A high-fidelity model is first generated using the bond graph formalism. The relative contributions of the terms of the generalized Kirchoff loop and node equations are computed by calculating and comparing a measure of their power flow. Negligible aggregate bond power at a constraint equation node indicates an unnecessary term, which is then removed from the model by replacing the associated bond by a modulated source of generalized effort or flow. If replacement of all low-power bonds creates separate bond graphs that are joined by modulating signals, then the model can be partitioned into driving and driven subsystems. The partitions are smaller than the original model, have lower-dimension design variable vectors, and can be simulated separately or in parallel. The partitioning algorithm can be employed alongside existing automated modeling techniques to facilitate efficient, accurate simulation-based design of dynamic systems.
APA, Harvard, Vancouver, ISO, and other styles
8

Dai, Lan, and Chengying Chen. "A 69-dB SNR 89-μW AGC for Multifrequency Signal Processing Based on Peak-Statistical Algorithm and Judgment Logic." VLSI Design 2016 (December 29, 2016): 1–7. http://dx.doi.org/10.1155/2016/6708253.

Full text
Abstract:
A novel peak-statistical algorithm and judgment logic (PSJ) for multifrequency signal application of Autogain Control Loop (AGC) in hearing aid SoC is proposed in this paper. Under a condition of multifrequency signal, it tracks the amplitude change and makes statistical data of them. Finally, the judgment is decided and the circuit gain is controlled precisely. The AGC circuit is implemented with 0.13 μm 1P8M CMOS mixed-signal technology. Meanwhile, the low-power circuit topology and noise-optimizing technique are adopted to improve the signal-to-noise ratio (SNR) of our circuit. Under 1 V voltage supply, the peak SNR achieves 69.2 dB and total harmonic distortion (THD) is 65.3 dB with 89 μW power consumption.
APA, Harvard, Vancouver, ISO, and other styles
9

Ibrahim, Atef, Fayez Gebali, Yassine Bouteraa, Usman Tariq, Tariq Ahamad, and Waleed Nazih. "Low-Space Bit-Parallel Systolic Structure for AOP-Based Multiplier Suitable for Resource-Constrained IoT Edge Devices." Mathematics 10, no. 5 (March 4, 2022): 815. http://dx.doi.org/10.3390/math10050815.

Full text
Abstract:
Security and privacy issues with IoT edge devices hinder the application of IoT technology in many applications. Applying cryptographic protocols to edge devices is the perfect solution to security issues. Implementing these protocols on edge devices represents a significant challenge due to their limited resources. Finite-field multiplication is the core operation for most cryptographic protocols, and its efficient implementation has a remarkable impact on their performance. This article offers an efficient low-area and low-power one-dimensional bit-parallel systolic implementation for field multiplication in GF(2n) based on an irreducible all-one polynomial (AOP). We represented the adopted multiplication algorithm in the bit-level form to be able to extract its dependency graph (DG). We choose to apply specific scheduling and projection vectors to the DG to extract the bit-parallel systolic multiplier structure. In contrast with most of the previously published parallel structures, the proposed one has an area complexity of the order O(n) compared to the area complexity of the order of O(n2) for most parallel multiplier structures. The complexity analysis of the proposed multiplier structure shows that it exhibits a meaningful reduction in area compared to most of the compared parallel multipliers. To confirm the results of the complexity analysis, we performed an ASIC implementation of the proposed and the existing efficient multiplier structures using an ASIC CMOS library. The obtained ASIC synthesis report shows that the proposed multiplier structure displays significant savings in terms of its area, power consumption, area-delay product (ADP), and power-delay product (PDP). It offers average savings in space of nearly 33.7%, average savings in power consumption of 39.3%, average savings in ADP of 24.8%, and savings in PDP of 31.2% compared to the competitive existing multiplier structures. The achieved results make the proposed multiplier structure more suitable for utilization in resource-constrained devices such as IoT edge devices, smart cards, and other compact embedded devices.
APA, Harvard, Vancouver, ISO, and other styles
10

Gulakhmadov, Aminjon, Salima Asanova, Damira Asanova, Murodbek Safaraliev, Alexander Tavlintsev, Egor Lyukhanov, Sergey Semenenko, and Ismoil Odinaev. "Power Flows and Losses Calculation in Radial Networks by Representing the Network Topology in the Hierarchical Structure Form." Energies 15, no. 3 (January 21, 2022): 765. http://dx.doi.org/10.3390/en15030765.

Full text
Abstract:
This paper proposes a structured hierarchical-multilevel approach to calculating the power flows and losses of electricity in radial electrical networks with different nominal voltages at given loads and voltages of the power source. The researched electrical networks are characterized by high dimensionality, dynamism of development, but also insufficient completeness and reliability of state information. The approach is based on the representation of the initial network graph in the form of a hierarchical-multilevel structure, divided into two stages with rated voltages Unom≤35 kV and Unom≥35 kV, and using the traditional (manual) engineering two-stage method, where the calculation is performed in a sequence from bottom to top (stage 1) and from top to bottom (stage 2), moving along the structure of the network. The application of the above approach makes it possible to obtain an algorithm for implementation on a computer, which is characterized by universality (for an arbitrary configuration and complexity of the network), high performance and low requirements for the computer memory.
APA, Harvard, Vancouver, ISO, and other styles
More sources

Dissertations / Theses on the topic "Application to low power graphs algorithm"

1

Alsayeg, Khaled. "Synthèse de contrôleurs séquentiels QDI faible consommation prouvés corrects." Grenoble INPG, 2010. http://www.theses.fr/2010INPG0076.

Full text
Abstract:
L'étude des circuits asynchrones est un secteur dans lequel de nombreuses recherches ont été effectuées ces dernières années. Les circuits asynchrones ont démontré plusieurs caractéristiques intéressantes comme la robustesse, l'extensibilité, la faible consommation ou le faible rayonnement électromagnétique. Parmi les différentes classes de circuits asynchrones, les circuits quasi-insensibles aux délais (QDI) ont montré des caractéristiques extrêmement intéressantes en termes de faible consommation et de robustesse aux variations PVT (Process, Voltage, Temperature). L'usage de ces circuits est notamment bien adapté aux applications fonctionnant dans un environnement sévère et pour lesquelles la consommation est un critère primordial. Les travaux de cette thèse s'inscrivent dans ce cadre et visent la conception et la synthèse de machines à états asynchrones (QDI) faiblement consommatrices. Une méthode de synthèse dédiée à des contrôleurs asynchrones à faible consommation a donc été développée. Cette technique s'est montrée particulièrement efficace pour synthétiser les contrôleurs de grande taille. La méthode s'appuie sur une modélisation appropriée des contrôleurs et une technique de synthèse dirigée par la syntaxe utilisant des composants spécifiques appelés séquenceurs. Les circuits obtenus ont été vérifiés formellement afin de s'assurer de leurs propriétés en termes de robustesse et de correction fonctionnelle. A cette occasion, une méthode de vérification formelle a été mise en place pour valider les contrôleurs d'une part, et plus généralement, n'importe quel circuit asynchrone d'autre part. Cette technique fait appel à une modélisation hiérarchique des circuits asynchrones en PSL et à un outil de vérification formelle (RAT)
The study of asynchronous circuits is an area where much research has been conducted in recent years. Asynchronous circuits have shown several interesting features like robustness, scalability, low consumption or low electromagnetic radiation. Among the different classes of asynchronous circuits, Quasi Delay Insensitive circuits (QDI) showed very interesting characteristics in terms of low power consumption and robustness to variations of PVT (Process, Voltage, and Temperature). The use of these circuits is particularly well suited for applications operating in a critical environment and for which consumption is paramount. In this framework, the work of this thesis aims the low power consumption design and synthesis of asynchronous state machines (QDI). A method for synthesizing low-consumption asynchronous sequential controllers has been developed. The method relies on an adequate modeling of controllers and a direct mapping synthesis technique using specific components called sequencers. This technique is suitable for synthesizing large controllers. The circuits obtained are formally verified to ensure their properties in terms of robustness and are proved functionally correct. Thereby, a formal verification method has been implemented to validate the sequential controllers on the one hand, and more generally, any other asynchronous circuit. This technique uses a hierarchical model of asynchronous circuits in PSL and a formal verification tool called RAT
APA, Harvard, Vancouver, ISO, and other styles
2

Burrell, Tina R. "An alternating direction search algorithm for low dimensional optimization : an application to power flow /." This resource online, 1993. http://scholar.lib.vt.edu/theses/available/etd-12162009-020216/.

Full text
APA, Harvard, Vancouver, ISO, and other styles
3

Burrell, Tinal R. "An alternating direction search algorithm for low dimensional optimization: an application to power flow." Thesis, Virginia Tech, 1993. http://hdl.handle.net/10919/46240.

Full text
Abstract:
Presented in this paper is a scheme for minimizing the cost function of a three-source technique to arrive at an approximation point (I,J) that is within one unit of the true minimum. The Line-Step algorithm is applied to several systems and is also compared to other minimization techniques, including the Equal Incremental Loss Algorithm. Variations are made on the Line-Step Algorithm for faster convergence and also to handle inequality constraints.
Master of Science
APA, Harvard, Vancouver, ISO, and other styles
4

Yassin, Yahya H. "ULTRA LOW POWER APPLICATION SPECIFIC INSTRUCTION-SET PROCESSOR DESIGN : for a cardiac beat detector algorithm." Thesis, Norwegian University of Science and Technology, Department of Electronics and Telecommunications, 2009. http://urn.kb.se/resolve?urn=urn:nbn:no:ntnu:diva-9914.

Full text
Abstract:

High efficiency and low power consumption are among the main topics in embedded systems today. For complex applications, off-the-shelf processor cores might not provide the desired goals in terms of power consumption. By optimizing the processor for the application, or a set of applications, one could improve the computing power by introducing special purpose hardware units. The execution cycle count of the application would in this case be reduced significantly, and the resulting processor would consume less power. In this thesis, some research is done in how to optimize a software and hardware development for ultra low power consumption. A cardiac beat detector algorithm is implemented in ANSI C, and optimized for low power consumption, by using several software power optimization techniques. The resulting application is mapped on a basic processor architecture provided by Target Compiler Technologies. This processor is optimized further for ultra low power consumption by applying application specific hardware, and by using several hardware power optimization techniques. A general processor and the optimized processor has been mapped on a chip, using a 90 nm low power TSMC process. Information about power dissipation is extracted through netlist simulation, and the results of both processors have been compared. The optimized processor consume 55% less average power, and the duty cycle of the processor, i.e., the time in which the processor executes its task with respect to the time budget available, has been reduced from 14% to 2.8%. The reduction in the total execution cycle count is 81%. The possibilities of applying power gating, or voltage and frequency scaling are discussed, and it is concluded that further reduction in power consumption is possible by applying these power optimization techniques. For a given case, the average leakage power dissipation is estimated to be reduced by 97.2%.

APA, Harvard, Vancouver, ISO, and other styles

Book chapters on the topic "Application to low power graphs algorithm"

1

Shen, Yilin, Xiang Li, and My T. Thai. "Approximation Algorithms for Optimization Problems in Random Power-Law Graphs." In Combinatorial Optimization and Applications, 343–55. Cham: Springer International Publishing, 2014. http://dx.doi.org/10.1007/978-3-319-12691-3_26.

Full text
APA, Harvard, Vancouver, ISO, and other styles
2

S., Shiyamala, Vijay Soorya J., Sanjay P. S., and Sathappan K. "Network-on-Chip for Low Power MAP Decoder Using Folded Technique and CORDIC Algorithm for 5G Network." In Design Methodologies and Tools for 5G Network Development and Application, 96–108. IGI Global, 2021. http://dx.doi.org/10.4018/978-1-7998-4610-9.ch005.

Full text
Abstract:
With different constraint length (K), time scale, and code rate, modified MAP (maximum a posteriori) decoder architecture using folding technique, which has a linear life time chart, is developed, and dedicated turbo codes will be placed in a network-on-chip for various wireless applications. Folded techniques mitigated the number of latches used in interleaving and deinterleaving unit by adopting forward and backward resource utilizing method to M-2, where M is the number of rows and end-to-end delay get reduced to 2M. By replacing conventional full adder by high speed adder using 2 x 1 multiplexer to calculate the forward state metrics and reverse state metrics will minimize the power consumption utilization in an effective manner. In s similar way, CORDIC (Coordinated ROtation DIgital Computer) algorithm is used to calculate the LLR value and confer a highly precise value with less computational complexity by means of only shifting and adding methods.
APA, Harvard, Vancouver, ISO, and other styles
3

Burch, Michael, Andrei Jalba, and Carl van Dueren den Hollander. "Convolutional Neural Networks for Real-Time Eye Tracking in Interactive Applications." In Advances in Marketing, Customer Relationship Management, and E-Services, 455–73. IGI Global, 2021. http://dx.doi.org/10.4018/978-1-7998-5077-9.ch022.

Full text
Abstract:
Face alignment and eye tracking for interactive applications should be performed with very low latency or users will notice the delay. In this chapter, a face alignment method for real-time applications is introduced featuring a convolutional neural network architecture for face and pose alignment. The performance of the novel method is compared to a face alignment algorithm included in the freely available OpenFace toolkit, which also focuses on real-time applications. The approach exceeds OpenFace's performance on both our own and the 300W test sets in terms of accuracy and robustness but requires significant parallel processing power, currently provided by the GPU. For the eye tracking application, stereo cameras are used as input to determine the position of a user's eyes in three-dimensional space. It does not require synchronized recordings, which may contain redundant information, and instead prefers staggered recordings, which maximize the number of possible model updates.
APA, Harvard, Vancouver, ISO, and other styles
4

Vijayaprabakaran K., Sathiyamurthy K., and Ponniamma M. "Video-Based Human Activity Recognition for Elderly Using Convolutional Neural Network." In Research Anthology on Supporting Healthy Aging in a Digital Society, 1014–27. IGI Global, 2022. http://dx.doi.org/10.4018/978-1-6684-5295-0.ch055.

Full text
Abstract:
A typical healthcare application for elderly people involves monitoring daily activities and providing them with assistance. Automatic analysis and classification of an image by the system is difficult compared to human vision. Several challenging problems for activity recognition from the surveillance video involving the complexity of the scene analysis under observations from irregular lighting and low-quality frames. In this article, the authors system use machine learning algorithms to improve the accuracy of activity recognition. Their system presents a convolutional neural network (CNN), a machine learning algorithm being used for image classification. This system aims to recognize and assist human activities for elderly people using input surveillance videos. The RGB image in the dataset used for training purposes which requires more computational power for classification of the image. By using the CNN network for image classification, the authors obtain a 79.94% accuracy in the experimental part which shows their model obtains good accuracy for image classification when compared with other pre-trained models.
APA, Harvard, Vancouver, ISO, and other styles
5

Sivasaravanababu, S., T. R. Dineshkumar, and G. Saravana Kumar. "Assertion Driven Modified Booth Encoding and Post Computation Model for Speed MAC Applications." In Recent Trends in Intensive Computing. IOS Press, 2021. http://dx.doi.org/10.3233/apc210289.

Full text
Abstract:
The Multiply-Accumulate Unit (MAC) is the core computational block in many DSP and wireless application but comes with more complicated architectures. Moreover the MAC block also decides the energy consumption and the performance of the overall design; due to its lies in the maximal path delay critical propagation. Developing high performance and energy optimized MAC core is essential to optimized DSP core. In this work, a high speed and low power signed booth radix enabled MAC Unit is proposed with highly configurable assertion driven modified booth algorithm (AD-MBE). The proposed booth core is based on core optimized booth radix-4 with hierarchical partial product accumulation design and associated path delay optimization and computational complexity reduction. Here all booth generated partial products are added as post summation adder network which consists of carry select adder (CSA) & carry look ahead (CLA) sequentially which narrow down the energy and computational complexity. Here increasing the operating frequency is achieved by accumulating encoding bits of each of the input operand into assertion unit before generating end results instead of going through the entire partial product accumulation. The FPGA implementation of the proposed signed asserted booth radix-4 based MAC shows significant complexity reduction with improved system performance as compared to the conventional booth unit and conventional array multiplier.
APA, Harvard, Vancouver, ISO, and other styles

Conference papers on the topic "Application to low power graphs algorithm"

1

Jakubik, Tomas, and Jiri Jenicek. "Asymmetric low-power FHSS algorithm." In 2017 IEEE International Workshop of Electronics, Control, Measurement, Signals and their Application to Mechatronics (ECMSM). IEEE, 2017. http://dx.doi.org/10.1109/ecmsm.2017.7945892.

Full text
APA, Harvard, Vancouver, ISO, and other styles
2

Liang, Hao, Weiding Long, Yingqian Song, and Fang Liu. "The Analysis and Application of Energy-Internet in the Low-Carbon Community." In ASME 2010 4th International Conference on Energy Sustainability. ASMEDC, 2010. http://dx.doi.org/10.1115/es2010-90338.

Full text
Abstract:
The energy-Internet is a new energy supply method based on urban compact and densely populated community in a low-carbon city. The principle is to connect small energy generation stations and combined heat and power system (CHP) based on distributed energy technology and renewable energy into a network in the urban district. In this way, the cooling, heating and electricity could all back each other up. Each building of the community could collect the energy and then put that energy into the energy-internet to supply the heating and power to buildings. The power in the energy-internet could also be used for charging electric vehicles. So the energy use in the urban community would be basically self-sufficient. The energy generation stations in the energy-internet could be solar power, wind power, biomass cogeneration (including refuse power generation), household fuel cell, low-grade heat in rivers, lakes, urban sewage and soil. In this way, large-scale renewable energy and unused energy could be fully used and applied in a compact and dense community. If the energy-internet is suitable designed, the equipment capacity, energy consumption and CO2 emission of the community could be greatly reduced, energy efficiency could be optimized and improved and the heat island effect could also be alleviated. This article explores three major problems of the construction of energy internet and their solutions: namely, the location and layout of the energy station, the environmental economic dispatch model of the energy internet with power dispatching as an example, the optimal path design of hot water pipe network combined with graph theory and genetic algorithms.
APA, Harvard, Vancouver, ISO, and other styles
3

Li, Wei, Zibin Dai, and Longmei Nan. "Research and Implementation of a Reconfigurable Low Power E0 Algorithm." In 2008 International Symposium on Intelligent Information Technology Application Workshops. IEEE, 2008. http://dx.doi.org/10.1109/iita.workshops.2008.52.

Full text
APA, Harvard, Vancouver, ISO, and other styles
4

Ren, Na, Xiaofeng Lyu, Dong Cao, Zheng Zuo, and Ruigang Li. "High-Efficiency Multiple-String Linear LED Driver with Genetic Algorithm for Low Power Application." In 2018 IEEE Energy Conversion Congress and Exposition (ECCE). IEEE, 2018. http://dx.doi.org/10.1109/ecce.2018.8557870.

Full text
APA, Harvard, Vancouver, ISO, and other styles
5

Li, Peng, and David J. Lilja. "A low power fault-tolerance architecture for the kernel density estimation based image segmentation algorithm." In 2011 IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP). IEEE, 2011. http://dx.doi.org/10.1109/asap.2011.6043264.

Full text
APA, Harvard, Vancouver, ISO, and other styles
6

Yassin, Yahya H., Per Gunnar Kjeldsberg, Jos Hulzink, Inaki Romero, and Jos Huisken. "Ultra low power application specific instruction-set processor design for a cardiac beat detector algorithm." In 2009 NORCHIP. IEEE, 2009. http://dx.doi.org/10.1109/norchp.2009.5397828.

Full text
APA, Harvard, Vancouver, ISO, and other styles
7

Jiancai, Liu, Yang Wanwan, Zheng Weili, Wang Yafu, Ye Zhihui, Xu Jiakai, and Ning Xinbao. "The improvement of adaptive bit and power loading algorithm with low complexity in MIMO-OFDM systems." In 2009 3rd International Conference on Internet Multimedia Services Architecture and Application (IMSAA). IEEE, 2009. http://dx.doi.org/10.1109/imsaa.2009.5439457.

Full text
APA, Harvard, Vancouver, ISO, and other styles
8

Zhao, Huan, Pei-hong Wang, Jin Qian, and Xian-yong Peng. "An Improved Particle Swarm Algorithm and Its Application in Low NOx Combustion Optimization of Coal-fired Utility Boiler." In 2010 Asia-Pacific Power and Energy Engineering Conference. IEEE, 2010. http://dx.doi.org/10.1109/appeec.2010.5449084.

Full text
APA, Harvard, Vancouver, ISO, and other styles
9

Peng, Xianyong, and Peihong Wang. "An Improved Multiobjective Genetic Algorithm in Optimization and its Application to High Efficiency and Low NOx Emissions Combustion." In 2009 Asia-Pacific Power and Energy Engineering Conference. IEEE, 2009. http://dx.doi.org/10.1109/appeec.2009.4918139.

Full text
APA, Harvard, Vancouver, ISO, and other styles
10

Ashwani, B., Devesh Kandpal, Mayank Srivastava, and Anupam Shukla. "An Efficient Mode Selection Algorithm for H.264 Encoder for Application in Low Computational Power Devices." In 2009 International Conference on Digital Image Processing, ICDIP. IEEE, 2009. http://dx.doi.org/10.1109/icdip.2009.75.

Full text
APA, Harvard, Vancouver, ISO, and other styles
You might also be interested in the extended bibliographies on the topic 'Application to low power graphs algorithm' for particular source types:
Journal articles
We offer discounts on all premium plans for authors whose works are included in thematic literature selections. Contact us to get a unique promo code!

To the bibliography