Relevant bibliographies by topics / Automatic Test Generation and Fault Diagnosis

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers
  6. Reports

Academic literature on the topic 'Automatic Test Generation and Fault Diagnosis'

Author: Grafiati
Published: 4 June 2021
Last updated: 6 February 2022

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Journal articles on the topic "Automatic Test Generation and Fault Diagnosis"

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RRadheesha, Mrs. "Fault diagnosis using automatic test packet generation." International Journal on Recent and Innovation Trends in Computing and Communication 3, no. 3 (2015): 919–22. http://dx.doi.org/10.17762/ijritcc2321-8169.150304.

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Savir, Jacob. "BIST-Based Fault Diagnosis in the Presence of Embedded Memories." VLSI Design 12, no. 4 (January 1, 2001): 487–500. http://dx.doi.org/10.1155/2001/32515.

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An efficient method is described for using fault simulation as a solution to the diagnostic problem created by the presence of embedded memories in BIST designs. The simulation is event-table-driven. Special techniques are described to cope with the faults in the Prelogic, Postlogic, and the logic embedding the memory control or address inputs. It is presumed that the memory itself has been previously tested, using automatic test pattern generation (ATPG) techniques via the correspondence inputs, and has been found to be fault-free.
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Deng, Da Wei, and Bao An Li. "Large Unmanned Aerial Vehicle Ground Testing System." Applied Mechanics and Materials 719-720 (January 2015): 1244–47. http://dx.doi.org/10.4028/www.scientific.net/amm.719-720.1244.

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The traditional high altitude long endurance UAV ground testing system (referred to as: testing system) not only lacks of universality and scalability, also incapable of handling faculties during flying procedure. In the paper, by using the new generation of automatic test system (New ATS), the flight simulation method, embedded technology and fault diagnosis technology, we are able to expand the testing system from ground to the sky, improving the generality of the system and UAV’s testing ability, also ensure the safety and reliability of the UAV flight at the same time.Keywords: Unmanned aerial vehicle; Automatic test system;Fault diagnosis; Embedded bus
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Gao, Zhan, Min-Chun Hu, Santosh Malagi, Joe Swenton, Jos Huisken, Kees Goossens, and Erik Jan Marinissen. "Reducing Library Characterization Time for Cell-aware Test while Maintaining Test Quality." Journal of Electronic Testing 37, no. 2 (April 2021): 161–89. http://dx.doi.org/10.1007/s10836-021-05943-3.

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AbstractCell-aware test (CAT) explicitly targets faults caused by defects inside library cells to improve test quality, compared with conventional automatic test pattern generation (ATPG) approaches, which target faults only at the boundaries of library cells. The CAT methodology consists of two stages. Stage 1, based on dedicated analog simulation, library characterization per cell identifies which cell-level test pattern detects which cell-internal defect; this detection information is encoded in a defect detection matrix (DDM). In Stage 2, with the DDMs as inputs, cell-aware ATPG generates chip-level test patterns per circuit design that is build up of interconnected instances of library cells. This paper focuses on Stage 1, library characterization, as both test quality and cost are determined by the set of cell-internal defects identified and simulated in the CAT tool flow. With the aim to achieve the best test quality, we first propose an approach to identify a comprehensive set, referred to as full set, of potential open- and short-defect locations based on cell layout. However, the full set of defects can be large even for a single cell, making the time cost of the defect simulation in Stage 1 unaffordable. Subsequently, to reduce the simulation time, we collapse the full set to a compact set of defects which serves as input of the defect simulation. The full set is stored for the diagnosis and failure analysis. With inspecting the simulation results, we propose a method to verify the test quality based on the compact set of defects and, if necessary, to compensate the test quality to the same level as that based on the full set of defects. For 351 combinational library cells in Cadence’s GPDK045 45nm library, we simulate only 5.4% defects from the full set to achieve the same test quality based on the full set of defects. In total, the simulation time, via linear extrapolation per cell, would be reduced by 96.4% compared with the time based on the full set of defects.
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Agrawal, Nishant. "Automatic Test Pattern Generation using Grover’s Algorithm." International Journal for Research in Applied Science and Engineering Technology 9, no. VI (June 14, 2021): 2373–79. http://dx.doi.org/10.22214/ijraset.2021.34837.

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Quantum computing is an exciting new field in the intersection of computer science, physics and mathematics. It refines the central concepts from Quantum mechanics into its least difficult structures, peeling away the complications from the physical world. Any combinational circuit that has only one stuck at fault can be tested by applying a set of inputs that drive the circuit to verify the output response. The outputs of that circuit will be different from the one desired if the faults exist. This project describes a method of generating test patterns using the Boolean satisfaction method. First, the Boolean formula is constructed to express the Boolean difference between a fault-free circuit and a faulty circuit. Second, the Boolean satisfaction algorithm is applied to the formula in the previous step. The Grover algorithm is used to solve the Boolean satisfaction problem. The Boolean Satisfiability problem for Automatic Test Pattern Generation(ATPG) is implemented on IBM Quantum Experience. The Python program initially generates the boolean expression from the file and converts it into Conjunctive Normal Form(CNF) which is passed on to Grover Oracle and runs on IBM simulator and produces excellent results on combinational circuits for test pattern generation with a quadratic speedup. Grover’s Algorithm on this problem has a run time of O(√N).
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Cox, H., and J. Rajski. "A method of fault analysis for test generation and fault diagnosis." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 7, no. 7 (July 1988): 813–33. http://dx.doi.org/10.1109/43.3952.

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Nam, Dong Soo, Yong Jin Choe, Yeo Hong Yoon, and En Sup Yoon. "Automatic generation of the symptom tree model for process fault diagnosis." Korean Journal of Chemical Engineering 10, no. 1 (January 1993): 28–35. http://dx.doi.org/10.1007/bf02697374.

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Hu, Wei, Yi Bing Deng, Hong Qi Feng, Qing E. Wu, Bin Tang, and Jian Hua Zou. "A Framework Design of Automatic Fault Diagnosis System." Applied Mechanics and Materials 330 (June 2013): 635–38. http://dx.doi.org/10.4028/www.scientific.net/amm.330.635.

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To resolve a lasting suitable cabin environment for the astronauts, this paper proposes an effective framework design for automatic fault diagnosis system. This framework can implement a real-time online diagnosis and decision support for fault, and carry out an early diagnosis for weak fault. Finally, this paper achieves an online automatic fault diagnosis system by using neural networks self-learning characteristics and expert knowledge. In two-men-two-days simulated manned space flight test, the software of diagnosis system framework worked well, which has been assessed and verified comprehensively.
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Mokhtarnia, Hossein, Shahram Etemadi Borujeni, and Mohammad Saeed Ehsani. "Automatic Test Pattern Generation Through Boolean Satisfiability for Testing Bridging Faults." Journal of Circuits, Systems and Computers 28, no. 14 (February 20, 2019): 1950240. http://dx.doi.org/10.1142/s0218126619502402.

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Automatic test pattern generation (ATPG) is one of the important issues in testing digital circuits. Due to considerable advances made in the past two decades, the ATPG algorithms that are based on Boolean satisfiability have become an integral part of the digital circuits. In this paper, a new method for ATPG for testing bridging faults is introduced. First of all, the application of Boolean satisfiability to circuit modeling is explained. Afterwards, a new method of testing the nonfeedback bridging faults in the combinational circuits is proposed based on Boolean satisfiability. In the proposed method, the faulty circuit is obtained by injecting the faulty gate into the main circuit. Afterwards, the final differential circuit is prepared by using the fault-free and the faulty circuits. Finally, using the resulting differential circuit, the testability of the fault is assessed and the input pattern for detecting the fault in the main circuit is derived. The experimental results presented at the end of this paper indicate the effectiveness and usefulness of this method for testing the bridging faults.
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Li, He Jia, Xue Wang, Hai Feng Xu, Cheng Yao, Wen Ju Gao, and Hui Wang. "Design of Automatic Test Platform for the Gyroscope Group Based on Pertinence Matrix." Applied Mechanics and Materials 556-562 (May 2014): 2567–70. http://dx.doi.org/10.4028/www.scientific.net/amm.556-562.2567.

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Aiming the problem of the armored vehicle's gun control system that there are many kinds of internal devices, complex fault reasons ,but no all-around and online fault diagnosis and state inspection mean, The automatic test platform for the gyroscope group with performance test and fault diagnosis for component and circuit is designed .The platform based on dependency matrix and optimal criterion of the maximum failure feature information entropy optimize test points ,choose optimal test points design. Performance test module is created and provides test result information for fault dictionary in fault diagnosis module. Automatic test platform is able to locate the circuit component failure.The platform is tested by actual vehicle experiment, and the results prove the reliability and validity of the platform.
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Dissertations / Theses on the topic "Automatic Test Generation and Fault Diagnosis"

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Chandrasekar, Maheshwar. "Search State Extensibility based Learning Framework for Model Checking and Test Generation." Diss., Virginia Tech, 2010. http://hdl.handle.net/10919/28978.

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The increasing design complexity and shrinking feature size of hardware designs have created resource intensive design verification and manufacturing test phases in the product life-cycle of a digital system. On the contrary, time-to-market constraints require faster verification and test phases; otherwise it may result in a buggy design or a defective product. This trend in the semiconductor industry has considerably increased the complexity and importance of Design Verification, Manufacturing Test and Silicon Diagnosis phases of a digital system production life-cycle. In this dissertation, we present a generalized learning framework, which can be customized to the common solving technique for problems in these three phases. During Design Verification, the conformance of the final design to its specifications is verified. Simulation-based and Formal verification are the two widely known techniques for design verification. Although the former technique can increase confidence in the design, only the latter can ensure the correctness of a design with respect to a given specification. Originally, Design Verification techniques were based on Binary Decision Diagram (BDD) but now such techniques are based on branch-and-bound procedures to avoid space explosion. However, branch-and-bound procedures may explode in time; thus efficient heuristics and intelligent learning techniques are essential. In this dissertation, we propose a novel extensibility relation between search states and a learning framework that aids in identifying non-trivial redundant search states during the branch-and-bound search procedure. Further, we also propose a probability based heuristic to guide our learning technique. First, we utilize this framework in a branch-and-bound based preimage computation engine. Next, we show that it can be used to perform an upper-approximation based state space traversal, which is essential to handle industrial-scale hardware designs. Finally, we propose a simple but elegant image extraction technique that utilizes our learning framework to compute over-approximate image space. This image computation is later leveraged to create an abstraction-refinement based model checking framework. During Manufacturing Test, test patterns are applied to the fabricated system, in a test environment, to check for the existence of fabrication defects. Such patterns are usually generated by Automatic Test Pattern Generation (ATPG) techniques, which assume certain fault types to model arbitrary defects. The size of fault list and test set has a major impact on the economics of manufacturing test. Towards this end, we propose a fault col lapsing approach to compact the size of target fault list for ATPG techniques. Further, from the very beginning, ATPG techniques were based on branch-and-bound procedures that model the problem in a Boolean domain. However, ATPG is a problem in the multi-valued domain; thus we propose a multi-valued ATPG framework to utilize this underlying nature. We also employ our learning technique for branch-and-bound procedures in this multi-valued framework. To improve the yield for high-volume manufacturing, silicon diagnosis identifies a set of candidate defect locations in a faulty chip. Subsequently physical failure analysis - an extremely time consuming step - utilizes these candidates as an aid to locate the defects. To reduce the number of candidates returned to the physical failure analysis step, efficient diagnostic patterns are essential. Towards this objective, we propose an incremental framework that utilizes our learning technique for a branch-and-bound procedure. Further, it learns from the ATPG phase where detection-patterns are generated and utilizes this information during diagnostic-pattern generation. Finally, we present a probability based heuristic for X-filling of detection-patterns with the objective of enhancing the diagnostic resolution of such patterns. We unify these techniques into a framework for test pattern generation with good detection and diagnostic ability. Overall, we propose a learning framework that can speed up design verification, test and diagnosis steps in the life cycle of a hardware system.
Ph. D.
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Doshi, Alok Shreekant Agrawal Vishwani D. "Independence fault collapsing and concurrent test generation." Auburn, Ala., 2006. http://repo.lib.auburn.edu/2006%20Spring/master's/DOSHI_ALOK_48.pdf.

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Kincl, Zdeněk. "Metody pro testování analogových obvodů." Doctoral thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2013. http://www.nusl.cz/ntk/nusl-233583.

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Práce se zabývá metodami pro testování lineárních analogových obvodů v kmitočtové oblasti. Cílem je navrhnout efektivní metody pro automatické generování testovacího plánu. Snížením počtu měření a výpočetní náročnosti lze výrazně snížit náklady za testování. Práce se zabývá multifrekveční parametrickou poruchovou analýzou, která byla plně implementována do programu Matlab. Vhodnou volbou testovacích kmitočtů lze potlačit chyby měření a chyby způsobené výrobními tolerancemi obvodových prvků. Navržené metody pro optimální volbu kmitočtů byly statisticky ověřeny metodou MonteCarlo. Pro zvýšení přesnosti a snížení výpočetní náročnosti poruchové analýzy byly vyvinuty postupy založené na metodě nejmenších čtverců a přibližné symbolické analýze.
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Gomes, Alfred Vincent. "Alternate Test Generation for Detection of Parametric Faults." Diss., Georgia Institute of Technology, 2003. http://hdl.handle.net/1853/5285.

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Tests for detecting faults in analog and mixed-signal circuits have been traditionally derived from the datasheet speci and #64257;cations. Although these speci and #64257;cations describe important aspects of the device, in many cases these application oriented tests are costly to implement and are inefficient in determining product quality. Increasingly, the gap between speci and #64257;cation test requirements and the capabilities of test equipment has been widening. In this work, a systematic method to generate and evaluate alternate tests for detecting parametric faults is proposed. We recognize that certain aspects of analog test generation problem are not amenable to automation. Additionally, functional features of analog circuits are widely varied and cannot be assumed by the test generator. To overcome these problems, an extended device under test (DUT) model is developed that encapsulates the DUT and the DUT speci and #64257;c tasks. The interface of this model provides a well de and #64257;ned and uniform view of a large class of devices. This permits several simpli and #64257;cations in the test generator. The test generator is uses a search-based procedure that requires evaluation of a large number of candidate tests. Test evaluation is expensive because of complex fault models and slow fault simulation techniques. A tester-resident test evaluation technique is developed to address this issue. This method is not limited by simulation complexity nor does it require an explicit fault model. Making use of these two developments, an efficient and automated test generation method is developed. Theoretical development and a number of examples are used to illustrate various concepts that are presented in this thesis.
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Chabir, Karim. "Diagnostic de défauts de systèmes contrôlés via un réseau." Phd thesis, Université Henri Poincaré - Nancy I, 2011. http://tel.archives-ouvertes.fr/tel-00653836.

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Aujourd'hui, les réseaux de communications sont largement utilisés pour relier les points de ressources, qui permettent la transmission de données à distance, de réduire la complexité dans le cadre de câblage et les coûts de support et de fournir l'aise dans la maintenance. En raison de ces avantages, les réseaux ont été introduits dans les systèmes automatiques au cours de ces dernières décennies et de nouveaux protocoles de réseau industriel ont été également développés pour assurer le contrôle à distance. Les systèmes contrôlés en réseau SCR (Networked Control System NCS) sont des systèmes automatiques traditionnels où les actionneurs, les capteurs, les contrôleurs et des autres composants sont distribués autour d'un réseau de communication, qui peut être partagé ou non avec d'autres applications. Les données de commande et de diagnostic sont échangées entre les composants du système (capteur, contrôleur, actionneur) via ce réseau partagé. Cette nouvelle architecture de système de contrôle introduit des problèmes originaux, en termes de retard variable affectant la transmission, des pertes de paquets, etc. Dans l'objectif de maintenir de bonnes performances du module de diagnostic face à des éventuelles variations introduites par le réseau, il est intéressant d'introduire des nouvelles approches. Nous avons rapporté les résultats relatifs aux techniques d'estimation optimale à base de filtre de Kalman, de façon à constituer un document aussi complet que possible traitant la génération de résidus et l'isolation des défauts dans SCR. Notre contribution consiste, dans un premier temps, à développer un modèle d'état d'un système contrôlé via un réseau. En deuxième temps, nous proposons un générateur de résidus en se basant sur les hypothèses simulant le retard induit par le réseau. Finalement, nous développons un filtre isolateur pour identifier directement les défauts affectant les actionneurs dans un SCR.
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Thavasinadar, Ramalingom. "Test case generation and fault diagnosis methods for communication protocols based on FSM and EFSM models." Thesis, 1994. http://spectrum.library.concordia.ca/4406/1/NN01277.pdf.

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Books on the topic "Automatic Test Generation and Fault Diagnosis"

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Keravnou, E. T. Competent expert systems: Acase study in fault diagnosis. New York: MacGraw-Hill, 1986.

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L, Johnson, ed. Competent expert systems: A case study in fault diagnosis. London: Kogan Page, 1986.

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L, Johnson, ed. Competent expert systems: A case study in fault diagnosis. New York: MacGraw-Hill, 1986.

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1961-, Sheppard John W., ed. System test and diagnosis. Boston: Kluwer Academic, 1994.

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Yang, Bo-Suk. Introduction to intelligent machine fault diagnosis and prognosis. New York: Nova Science Publishers, 2009.

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Achmad, Widodo, ed. Introduction of intelligent machine fault diagnosis and prognosis. New York: Nova Science Publishers, 2009.

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Chang, Robert Ching Wei. Functional fault equivalence and automated diagnositc test generation using conventional ATPG. 2005, 2005.

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Book chapters on the topic "Automatic Test Generation and Fault Diagnosis"

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Chang, Chuei-Tin, Hao-Yeh Lee, and Vincentius Surya Kurnia Adi. "Generation of Test Plans for Fault Diagnosis with Untimed Automata." In Advances in Industrial Control, 253–82. Cham: Springer International Publishing, 2021. http://dx.doi.org/10.1007/978-3-030-70978-5_8.

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Butler, Kenneth M., and M. Ray Mercer. "Automatic Test Pattern Generation." In Assessing Fault Model and Test Quality, 19–26. Boston, MA: Springer US, 1992. http://dx.doi.org/10.1007/978-1-4615-3606-2_4.

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Ubar, R., and M. Brik. "Multi-level test generation and fault diagnosis for finite state machines." In Dependable Computing — EDCC-2, 264–81. Berlin, Heidelberg: Springer Berlin Heidelberg, 1996. http://dx.doi.org/10.1007/3-540-61772-8_43.

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Krauss, Peter A., and Kurt J. Antreich. "Application of Fault Parallelism to the Automatic Test Pattern Generation for Sequential Circuits." In Parallel Computer Architectures, 234–45. Berlin, Heidelberg: Springer Berlin Heidelberg, 1993. http://dx.doi.org/10.1007/978-3-662-21577-7_17.

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Sabena, Davide, Luca Sterpone, and Matteo Sonza Reorda. "On the Automatic Generation of Software-Based Self-Test Programs for Functional Test and Diagnosis of VLIW Processors." In VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design, 162–80. Berlin, Heidelberg: Springer Berlin Heidelberg, 2013. http://dx.doi.org/10.1007/978-3-642-45073-0_9.

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"Electrical Generation Transmission and Distribution 6-245 Wiring Systems and Enclosures 6-246 Wiring Enclosures 6-247 Conduit Capacities 6-248 System Earthing Arrangements 6-251 Inspection and Testing 6-253 The Inspection Process 6-254 Periodic Inspection 6-255 The Inspection Process 6-257 The Testing Process 6-258 With the supply disconnected 6-259 The electrical supply may now be connected or reconnected 6-260 Electrical Test Instruments 6-261 Instrument accuracy 6-261 Calibration 6-261 Low-Resistance Ohmmeter Specification 6-262 Factors affecting accuracy 6-262 Insulation-Resistance Ohmmeter Specification 6-262 Factors affecting accuracy 6-262 Earth Fault Loop Impedance Tester Specification 6-263 Factors affecting accuracy 6-263 RCD Tester Specification 6-263 Factors affecting accuracy 6-263 Certification and Reporting 6-264 Electrical Installation Testing 6-265 Electrical Installation Test Procedures 6-267 Selecting Electrical Test Instruments 6-270 Inspection Testing and Certifying – A Summary Worksheet 6-273 Worksheet 14 (MC Questions) 6-276 Answers to Worksheets 1 to 14 6-284 7 Unit 3 (Level 3) Installation (Buildings and Structures) Fault Diagnosis and Rectification 7-289 Safe Working Procedures Before Undertaking Fault Diagnosis 7-291 Secure Electrical Isolation and Lock Off 7-293 “Proving” Equipment 7-293 On load, Off load Switching Devices 7-293 Restoration of the Supply 7-294 Secure Isolation Procedures 7-295 Safe Working Procedures 7-296 Electrical Faults – Symptoms 7-298." In Electrical Installation Work Curriculum Support Pack, 6. Routledge, 2006. http://dx.doi.org/10.4324/9780080505145-4.

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Conference papers on the topic "Automatic Test Generation and Fault Diagnosis"

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Davison, Craig R., and A. M. Birk. "Automated Fault Diagnosis for Small Gas Turbine Engines." In ASME Turbo Expo 2002: Power for Land, Sea, and Air. ASMEDC, 2002. http://dx.doi.org/10.1115/gt2002-30029.

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In one possible model of distributed power generation a large number of users will operate individual, gas turbine powered, cogeneration systems. These systems will be small, relatively inexpensive, and installed in locations without ready access to gas turbine maintenance experts. Consequently an automated method to monitor the engine and diagnose its health is required. To remain compatible with the low cost of the power system the diagnostics must also be relatively inexpensive to install and operate. Accordingly a minimum number of extra sensors should be used and the analysis performed by a common personal computer system. The current work automates the diagnosis of component faults by comparing the engine’s operating trends to the trends for known faults. This allows the relative percentage chance of each fault occurring to be determined. The likelihood of each fault is then compared, to determine which component is degrading. The technique can be adapted to compare the engines historic operating trend or a single operating point. In this initial work a computer model was used as a test bed and 5 faults were introduced individually. The technique successfully diagnosed the faulty component using either the operating trend or a single operating point.
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Kumar, Ch Narasimha, A. Madhumitha, N. Sesi Preetam, P. Vamsi Gupta, and J. P. Anita. "Fault Diagnosis Using Automatic Test Pattern Generation and Test Power Reduction Technique for VLSI Circuits." In 2019 3rd International Conference on Trends in Electronics and Informatics (ICOEI). IEEE, 2019. http://dx.doi.org/10.1109/icoei.2019.8862751.

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Estores, Rommel, and Karo Vander Gucht. "A Manual Diagnosis Approach Using Targeted Fault Injection and Fault Simulation to Extend ATPG Diagnostic Resolution in Localizing Faults." In ISTFA 2019. ASM International, 2019. http://dx.doi.org/10.31399/asm.cp.istfa2019p0419.

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Abstract This paper discusses a creative manual diagnosis approach, a complementary technique that provides the possibility to extend Automatic Test Pattern Generation (ATPG) beyond its own limits. The authors will discuss this approach in detail using an actual case – a test coverage issue where user-generated ATPG patterns and the resulting ATPG diagnosis isolated the fault to a small part of the digital core. However, traditional fault localization techniques was unable to isolate the fault further. Using the defect candidates from ATPG diagnosis as a starting point, manual diagnosis through fault Injection and fault simulation was performed. Further fault localization was performed using the ‘not detected’ (ND) and/or ‘detected’ (DT) fault classes for each of the available patterns. The result has successfully deduced the defect candidates until the exact faulty net causing the electrical failure was identified. The ability of the FA lab to maximize the use of ATPG in combination with other tools/techniques to investigate failures in detail; is crucial in the fast root cause determination and, in case of a test coverage, aid in having effective test screen method implemented.
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Jing Ye, Xiaolin Zhang, Yu Hu, and Xiaowei Li. "Substantial Fault Pair At-a-Time (SFPAT): An Automatic Diagnostic Pattern Generation Method." In 2010 19th Asian Test Symposium (ATS 2010). IEEE, 2010. http://dx.doi.org/10.1109/ats.2010.42.

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Perdu, Philippe, and Romain Desplats. "From IDDQ Fault Detection to Defect Localization in Logic CMOS Integrated Circuits: Key Issues." In ISTFA 1999. ASM International, 1999. http://dx.doi.org/10.31399/asm.cp.istfa1999p0427.

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Abstract IDDQ testing detects a majority of faults in logic ICs. To improve defect coverage with very short test patterns, IDDQ testing has been integrated in fault simulators embedded with automatic test pattern generation (ATPG) algorithms. Nevertheless, for failure analysis purposes, this progress has not eliminated the complex task of fault isolation at the silicon level of ICs. Defect localization is facilitated with IDDQ testing because the defect is detected as soon as it is activated inside the device. At the failed vector, abnormal IDDQ current is measured and accurate localization of the corresponding defect inside the chip can be performed. Thermally related techniques or emission microscopy can be used for this localization process. Very powerful tools like electron beam testers can also be used to deeply analyze faulty devices by internal contactless testing. In this paper, we will present an application of IDDQ testing for fault detection and some key issues regarding localization of the corresponding defect: • Appropriate techniques, • Switching from electrical testing to fault localization, • Modifying the test pattern to shorten the localization process, • Constructing a localization method based on an IDDQ diagnostic.
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Davison, Craig R., and A. M. Birk. "Automated Fault Diagnosis of a Micro Turbine With Comparison to a Neural Network Technique." In ASME Turbo Expo 2006: Power for Land, Sea, and Air. ASMEDC, 2006. http://dx.doi.org/10.1115/gt2006-91085.

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In the predicted future of distributed power generation, a large number of users will operate gas turbine powered cogeneration systems. These systems will be small, relatively inexpensive, and installed in locations without ready access to experts in gas turbine maintenance. Consequently, an automated system to monitor the engine and diagnose the health of the system is required. To remain compatible with the low cost of the overall system, the diagnostic system must also be relatively inexpensive to install and operate. Therefore, a minimum number of extra sensors and computing power should be used. A statistical technique is presented that compares the engine operation over time to the expected trends for particular faults. The technique ranks the probability that each fault is occurring on the engine. The technique can be used online, with daily data from the engine forming a trend for comparison, or, with less accuracy, based on a single operating point. The use of transient operating data with this technique is also examined. This technique has the advantage of providing an automated numerical result of the probability of a particular mode of degradation occurring, but can also produce visual plots of the engine operation. This allows maintenance staff to remain involved in the process, if they wish, rather than the system operating purely as a black box, and provides an easy to understand aid for discussions with operators. The technique is compared to an off the shelf neural network to determine its usefulness in comparison to other diagnostic methods. The test bed was a micro turbojet engine. The data to test the system was obtained from both experiment and computer modeling of the test engine.
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Bai, Haonan, Lan Yin Lee, Yang Jing, Peter Floyd Salinas, and Kok Keng Chua. "Zynq SOC Low-Voltage and Temperature-Dependent L2 Cache Failure Diagnosis and Defect Localization Case Study." In ISTFA 2017. ASM International, 2017. http://dx.doi.org/10.31399/asm.cp.istfa2017p0322.

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Abstract Failure analysis and defect localization on 28nm All Programmable Zynq System-on-Chip (SoC) device is extremely challenging. While conventional FPGA, which only consists of the Programmable Logic, has greater ease and flexibility in pattern generation during fault isolation, the all programmable SoC device integrates a dual ARM Cortex-A9 cores with Programmable Logic (PL) in a single chip. The cache data access in-between processor and PL is more complex and test methodology has lesser degree of control on cache data flow and stack sequence. This paper introduced an advanced fault isolation test methodology combining Software Development Kit (SDK) with scan based diagnostic test for cache failures. It successfully pinpoint to failure locations with physical defects found. As conventional physical failure analysis approaches using SEM based passive voltage contrast could not observe any abnormalities, current imaging and nano-probing measurement using AFP played critical roles in detecting nano-ampere leakages prior subsequent TEM analysis. The findings were then feedback to the foundry for process improvement. Furthermore, a new screening methodology is innovated where an extreme low-voltage test at high temperature in Automatic Test to detect and eliminate the process marginal leakage failure.
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Amati, L., C. Bolchini, F. Salice, and F. Franzoso. "Improving fault diagnosis accuracy by automatic test set modification." In 2010 IEEE International Test Conference (ITC). IEEE, 2010. http://dx.doi.org/10.1109/test.2010.5699250.

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Wu, Cheng-Hung, Saint James Lee, and Kuen-Jong Lee. "Test and diagnosis pattern generation for dynamic bridging faults and transition delay faults." In 2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC). IEEE, 2016. http://dx.doi.org/10.1109/aspdac.2016.7428102.

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Zhang, Yu, and Vishwani D. Agrawal. "Reduced complexity test generation algorithms for transition fault diagnosis." In 2011 IEEE 29th International Conference on Computer Design (ICCD 2011). IEEE, 2011. http://dx.doi.org/10.1109/iccd.2011.6081382.

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Reports on the topic "Automatic Test Generation and Fault Diagnosis"

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Johnson, Barry W., D. T. Smith, and Todd A. DeLong. VHDL Fault Simulation and Automatic Test Pattern Generation Requirements Document. Fort Belvoir, VA: Defense Technical Information Center, January 1996. http://dx.doi.org/10.21236/ada304358.

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