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Journal articles on the topic 'Carry look-ahead (CLA) adders'

Author: Grafiati

Published: 2 June 2025

Last updated: 31 July 2025

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1

Balasubramanian, Padmanabhan, and Nikos E. Mastorakis. "High-Speed and Energy-Efficient Carry Look-Ahead Adder." Journal of Low Power Electronics and Applications 12, no. 3 (2022): 46. http://dx.doi.org/10.3390/jlpea12030046.

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The carry look-ahead adder (CLA) is well known among the family of high-speed adders. However, a conventional CLA is not faster than other high-speed adders such as a conditional sum adder (CSA), a carry-select adder (CSLA), and the Kogge–Stone adder (KSA), which is the fastest parallel-prefix adder. Further, in terms of power-delay product (PDP) that characterizes the energy of digital circuits, the conventional CLA is not efficient compared to CSLA and KSA. In this context, this paper presents a high-speed and energy-efficient architecture for the CLA. Many adders ranging from ripple carry t

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2

Dr., Anuradha M. Sandi. "VERIFICATION OF CARRY LOOK AHEAD ADDER USING CONSTRAINED RANDOMIZED LAYERED TEST BENCH." International Journal of Engineering Technologies and Management Research 6, no. 6 (2019): 40–50. https://doi.org/10.5281/zenodo.3245207.

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In processors and in digital circuit designs, adder is an important component. As a result, adder is the main area of research in VLSI system design for improving the performance of a digital system. The performance depends on power consumption and delay. Adders are not only used for arithmetic operations, but also for calculating addresses and indices. In digital design we have half adder and full adder, by using these adders we can implement ripple carry adder (RCA). RCA is used to perform any number of additions. In this RCA is serial adder and it has propagation delay problem. With increas

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3

Kamaraju, M., P. Ashok Babu, P. Himasri, and S. Akshitha. "Power and Area Efficient Four-Bit Vedic Multiplier Implemented Using a Modified Five-Bit Adder with CMOS and TG Configuration." Journal of Controller and Converters 9, no. 1 (2024): 27–36. http://dx.doi.org/10.46610/jcc.2024.v090i01.005.

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Vedic multipliers are incredibly fast, efficient, and flexible, perfect for efficiently handling tasks like signal processing. Vedic multipliers are the go-to choice for maximizing performance and efficiency in digital designs, as the existing method adders like Carry Look-Ahead Adder (CLA), a Carry Skip Adder (CSA), or a Ripple Carry Adder (RCA) have more delay, area and power. The project proposal presents a novel 4-bit Vedic multiplier essential to system functionality. Optimizing the balancing area and delay is necessary for improving the system as a whole. This project aims to strike this

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4

Hari Kishore, K., B. K. V.Prasad, Y. Manoj Sai Teja, D. Akhila, K. Nikhil Sai, and P. Sravan Kumar. "Design and comparative analysis of inexact speculative adder and multiplier." International Journal of Engineering & Technology 7, no. 2.8 (2018): 413. http://dx.doi.org/10.14419/ijet.v7i2.8.10472.

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A Carry look ahead adder is a sort of the summer used in the logic design of the digital systems. The CLA boost up the speed by decreasing the measure of duration needed to calculate the carry bits. The CLA based outline of the inexact speculative adder is pipelined architecture to incorporate couple of logic paths along its basic way and in this manner, improving the recurrence of operation. This paper presents the comparative analysis of the pipelined inexact speculative adder and the general carry look ahead adder and showed that the delay is reduced to 48.27% when compared to carry look ah

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5

Sandi, Anuradha. "VERIFICATION OF CARRY LOOK AHEAD ADDER USING CONSTRAINED RANDOMIZED LAYERED TEST BENCH." International Journal of Engineering Technologies and Management Research 6, no. 6 (2020): 40–50. http://dx.doi.org/10.29121/ijetmr.v6.i6.2019.392.

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In processors and in digital circuit designs, adder is an important component. As a result, adder is the main area of research in VLSI system design for improving the performance of a digital system. The performance depends on power consumption and delay. Adders are not only used for arithmetic operations, but also for calculating addresses and indices. In digital design we have half adder and full adder, by using these adders we can implement ripple carry adder (RCA). RCA is used to perform any number of additions. In this RCA is serial adder and it has propagation delay problem. With increas

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6

Ziouzios, Dimitris, Dimitris Tsiktsiris, Nikolaos Baras, Stamatia Bibi, and Minas Dasygenis. "A generator tool for Carry Look-ahead Adders (CLA)." SHS Web of Conferences 102 (2021): 04021. http://dx.doi.org/10.1051/shsconf/202110204021.

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A carry look-ahead adder (CLA) is a digital circuit which is used widely used in any electronic computational device to improve speed calculation by reducing the time required to define carry bits. Despite the fact that CLA is used massively in modern digital systems, there is no online tool to automatically generate the HDL description. For this reason we developed a cloud based tool to automate the design of optimized CLA and provide custom testbenches to verify their correctness for singed and unsigned numbers. It is also can be used by the students to create and understand deeply the way C

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7

Balasubramanian, Padmanabhan, and Weichen Liu. "High-speed and energy-efficient asynchronous carry look-ahead adder." PLOS ONE 18, no. 10 (2023): e0289569. http://dx.doi.org/10.1371/journal.pone.0289569.

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Addition is a fundamental computer arithmetic operation that is widely performed in microprocessors, digital signal processors, and application-specific processors. The design of a high-speed and energy-efficient adder is thus useful and important for practical applications. In this context, this paper presents the designs of novel asynchronous carry look-ahead adders (CLAs) viz. a standard CLA (SCLA) and a block CLA (BCLA). The proposed CLAs are monotonic, dual-rail encoded, and are realized according to return-to-zero handshake (RZH) and return-to-one handshake (ROH) protocols using a 28-nm

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8

Saini, Vikas K., Shamim Akhter, and Tanuj Chauhan. "Implementation, Test Pattern Generation, and Comparative Analysis of Different Adder Circuits." VLSI Design 2016 (June 8, 2016): 1–8. http://dx.doi.org/10.1155/2016/1260879.

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Addition usually affects the overall performance of digital systems and an arithmetic function. Adders are most widely used in applications like multipliers, DSP (i.e., FFT, FIR, and IIR). In digital adders, the speed of addition is constrained by the time required to propagate a carry through the adder. Various techniques have been proposed to design fast adders. We have derived architectures for carry-select adder (CSA), Common Boolean Logic (CBL) based adders, ripple carry adder (RCA), and Carry Look-Ahead Adder (CLA) for 8-, 16-, 32-, and 64-bit length. In this work we have done comparativ

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9

S., Nithin, and Ramesh K.B. "Design of High Speed Carry Select Adder Using Kogge-Stone and Carry-Lookahead Adders." Recent Trends in Analog Design and Digital Devices 7, no. 3 (2024): 23–33. https://doi.org/10.5281/zenodo.13709580.

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<em>The adder is acknowledged as the fundamental component in various arithmetic and logical operations. In efforts to enhance operational efficiency, the Carry Select Adder (CSLA) has been devised. By integrating multiple high-speed adder logics within a conventional CSLA framework, operational speed is further enhanced. This study presents the design of a hybrid CSLA that amalgamates the advantages of both Kogge Stone Adder and Look Ahead Adder (CLA) methodologies to achieve superior performance. Kogge Stone Adder, distinguished for its rapid carry generation, is incorporated to bolster spee

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10

Rout, Shasanka Sekhar, Rajesh Kumar Patjoshi, Sarmila Garnaik, and Ranjita Rout. "Comparative Analysis of Heterogeneous Adders: Evaluating Performance across 12-bit, 14-bit, and 16-bit Configurations." Journal of Information Assurance and Security 19, no. 4 (2024): 136–45. https://doi.org/10.2478/ias-2024-0010.

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Abstract Digital Signal Processing (DSP) heavily relies on repetitive addition and multiplication operations, making adders a crucial component in DSP systems. Likewise, in processor design, an efficient adder circuit is essential for optimizing compactness, achieving high speed, and minimizing power consumption, particularly when utilizing Xilinx technology. This study delves into the exploration and design of an effective adder architecture by examining various parallel, synchronous adders and proposing a novel combination. The presented research introduces heterogeneous adders composed of c

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Bhavani, M., M. Siva Kumar, and K. Srinivas Rao. "Delay Comparison for 16x16 Vedic Multiplier Using RCA and CLA." International Journal of Electrical and Computer Engineering (IJECE) 6, no. 3 (2016): 1205. http://dx.doi.org/10.11591/ijece.v6i3.9457.

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<p>In any integrated chip compulsory adders are required because first they are fast and second are the less power consumption and delay. And at the same time multiplication process is also used in various applications. So as the speed of multiplier increases then the speed of processor also increases. And hence we are proposing the Vedic multiplier using these adders. Vedic multiplier is an ancient mathematics which uses mainly 16 sutras for its operation. In this project we are using “urdhva triyagbhyam” sutra to do our process. This paper proposes the Vedic multiplier using the adders

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Bhavani, M., M. Siva Kumar, and K. Srinivas Rao. "Delay Comparison for 16x16 Vedic Multiplier Using RCA and CLA." International Journal of Electrical and Computer Engineering (IJECE) 6, no. 3 (2016): 1205. http://dx.doi.org/10.11591/ijece.v6i3.pp1205-1212.

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<p>In any integrated chip compulsory adders are required because first they are fast and second are the less power consumption and delay. And at the same time multiplication process is also used in various applications. So as the speed of multiplier increases then the speed of processor also increases. And hence we are proposing the Vedic multiplier using these adders. Vedic multiplier is an ancient mathematics which uses mainly 16 sutras for its operation. In this project we are using “urdhva triyagbhyam” sutra to do our process. This paper proposes the Vedic multiplier using the adders

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13

Maroju, SaiKumar, and P. Samundiswary Dr. "Design and Performance Analysis of Various Adders using Verilog." International Journal of Computer Science and Mobile Computing 2, no. 9 (2013): 128–38. https://doi.org/10.5281/zenodo.32564.

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Adders are one of the most widely digital components in the digital integrated circuit design and are the necessary part of Digital Signal Processing (DSP) applications. With the advances in technology, researchers have tried and are trying to design adders which offer either high speed, low power consumption, less area or the combination of them. In this paper, the design of various adders such as Ripple Carry Adder (RCA), Carry Skip Adder (CSkA), Carry Increment Adder (CIA), Carry Look Ahead Adder (CLaA), Carry Save Adder (CSA), Carry Select Adder (CSlA), Carry Bypass Add

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14

Odugu, Dr Venkata Krishna, Dr B. Janardhana Rao, and Dr G. Harish Babu. "Area-Delay-Power Efficient VLSI Architecture 2D FIR Filter using Modified Multipliers and Adders." CVR Journal of Science and Technology 26, no. 1 (2024): 47–53. http://dx.doi.org/10.32377/cvrjst2608.

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In this paper, a low power, area, and delay 2D Finite Impulse Response (FIR) filter architecture is derived from an analysis of a memory-efficient design. The completely direct-form 2D FIR filter is where the idea of parallel processing is first presented. As a result, the FIR filter may make better use of its memory by reusing its contents. With a block size of L and a filter length of N, a non-separable 2D FIR filter structure is developed and implemented. The FIR filter's arithmetic module makes use of high-speed, low-power multipliers and Carry Look Ahead (CLA) adders, with the output calc

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15

Gharajeh, Mohammad, and Majid Haghparast. "Novel reversible CLA, optimized RCA and parallel adder/subtractor circuits." Serbian Journal of Electrical Engineering 17, no. 3 (2020): 259–83. http://dx.doi.org/10.2298/sjee2003259g.

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This paper proposes reversible circuit designs of the three most commonly used adders: carry look-ahead adder (CLA adder), ripple carry adder (RCA adder), and parallel adder/subtractor. The n-bit reversible CLA adder, called CLA-GH, is designed using the Peres and Fredkin gates. The n-bit optimized reversible RCA adder, called ORCA-GH, is designed using the reversible circuit of a parity-preserving reversible full adder. Both circuits reduce the quantum cost. However, the ORCA-GH circuit also improves the number of constant inputs. Furthermore, the n-bit reversible parallel adder/subtractor, c

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16

Shishir, A. Bagal, R. Asamwar Saikiran, and Dhengre Sujal. "An Exhaustive Review on Optimization of Carry-Look-Ahead Adder Using Hybrid Logic." International Journal of Innovative Science and Research Technology (IJISRT) 10, no. 2 (2025): 1548–54. https://doi.org/10.5281/zenodo.14964543.

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A revolutionary method for designing contemporary digital circuits is the use of hybrid logic in the creation of carry-look ahead adders (CLAs), which combine CMOS and memristor technology. By combining the scalability and dependability of CMOS technology with the special qualities of memristors—such as their small size, low power consumption, and non-volatile nature—this review paper investigates developments in CLA architectures. The compiled studies demonstrate how hybrid memristor-CMOS designs can be used to get around drawbacks in conventional CLA implementations, such as decr

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Hossain, Muhammad Saddam, and Farhadur Arifin. "Design and Evaluation of a 32-bit Carry Select Adder using 4-bit Hybrid CLA Adder." AIUB Journal of Science and Engineering (AJSE) 20, no. 2 (2021): 1–7. http://dx.doi.org/10.53799/ajse.v20i2.119.

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Adder circuits play a remarkable role in modern microprocessor. Adders are widely used in critical paths of arithmetic operation such as multiplication and subtraction. A Carry Select Adder (CSA) design methodology using a modified 4-bit Carry Look-Ahead (CLA) Adder has been proposed in this research. The proposed 4-bit CLA used hybrid logic style based logic circuits for Carry Generate (Gi) and Carry Propagate (Pi) functions in order to improve performance and reduce the number of transistor used. The modified 4-bit CLA is used as the basic unit for implementation of 32-bit CSA. The proposed

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18

Mohsin, Syed, Rahul J. Gowda, Asha CN, and Sumalatha S. "Physical Design of 64-bit Multiplier and Accumulator (MAC) Unit Using Vedic Multiplier and CLA Adder." Journal of Electrical Engineering and Electronics Design 1, no. 1 (2023): 5–9. http://dx.doi.org/10.48001/joeeed.2023.115-9.

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In digital signal processing, communication systems and many other applications, multiplier and accumulator units play a crucial role. This work presents an overview of 64-bit MAC Unit, where Vedic multiplier is used as multiplier unit and compared Carry select adders (CSA) and Carry look-ahead adder (CLA) which must be used for adder unit, accumulator unit consist of Parallel in parallel out (PIPO) shift registers. As a result, CLA adder to be more effective in terms of lower delay by comparing with other adders. The MAC Unit was modelled using Verilog-HDL, where its functional verification a

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19

Afridi, Shaik Mahammad Ameer. "4-bit Carry Look Ahead Adder Using MGDI Technique." International Journal for Research in Applied Science and Engineering Technology 9, no. 9 (2021): 855–60. http://dx.doi.org/10.22214/ijraset.2021.38075.

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Abstract: Today's high-performance processor is built with arithmetic logic units that add and subtract key components. Design considerations related to low power and high performance digital VLSI circuits have become more prevalent in today's world. In order to develop low-power and high-performance processors, the designers need to design their adder circuits with the required speed and power dissipation for their applications. This topic introduces the concept of a adder using MGDI Technique. The Exact Speculative Carry Look Ahead Adder the use of the Modified-GDI (Modified-Gate Diffusion I

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20

S, Pragadeswaran, Vasanthi M, Veera Boopathy E, et al. "OPTIMIZING VLSI ARCHITECTURE WITH CARRY LOOK AHEAD TECHNOLOGY BASED HIGH-SPEED, INEXACT SPECULATIVE ADDER." Archives for Technical Sciences 2, no. 31 (2024): 220–29. https://doi.org/10.70102/afts.2024.1631.220.

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This paper describes the design of the Carry Look-ahead Adder (CLA), which uses the Inexact Speculative Adder (ISA). The speculative adder is designed for high-speed VLSI architecture and features advanced compensation techniques and optimized hardware efficiency. Considered to be the adder's critical path, it is finely pipelined to contain a few logic gates along its carry propagation chain. This increases the frequency of operation by employing CLA, which is pipelined with some logic gates. To lower the model's power consumption, a separate planned ISA stage has been clocked gated. The Field

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B Gowda, Ranjith, and R. M Banakar. "Design of high speed low power optimized square root BK adder." International Journal of Engineering & Technology 7, no. 2.12 (2018): 240. http://dx.doi.org/10.14419/ijet.v7i2.12.11289.

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Adder is a basic building block in almost all the digital circuits used in todays digital world. Adders are used for address calculation, incrementing operation, table indices calculations and many other operations in digital processors. These operations require fast adders with reasonable design cost. Ripple carry adder (RCA) is the cheapest and most straight forward design but takes more computation time. For high speed applications Carry Look-ahead Adder (CLA) is preferred, but it has the limitation of increase in the total area of the design. Hence an adder which compromise between these t

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22

Chu, Shunan. "Comparative Analysis of Optimization Schemes of Carry Look-ahead Adder." Journal of Physics: Conference Series 2290, no. 1 (2022): 012008. http://dx.doi.org/10.1088/1742-6596/2290/1/012008.

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Abstract Conventional CLA adder has has a large number of transistors and high input impedance, which affects various performance aspects, resulting in high delay and power consumption. Therefore, to increase the performance and reduce delay, several optimized structures of CLA are proposed. From the perspective of structure and power, this paper selects four different design schemes and uses Cadence Virtuoso 90nm technology to compare and analyze the optimization results in aspects of circuit area, delay and power consumption. The analysis results show that the conventional 4-bit adder struct

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23

Akbari, Omid, Mehdi Kamal, Ali Afzali-Kusha, and Massoud Pedram. "RAP-CLA: A Reconfigurable Approximate Carry Look-Ahead Adder." IEEE Transactions on Circuits and Systems II: Express Briefs 65, no. 8 (2018): 1089–93. http://dx.doi.org/10.1109/tcsii.2016.2633307.

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24

Neeraj, Jain, Gour Puran, and Shrman Brahmi. "A High Speed Low Power Adder in Multi Output Domino Logic." International Journal of Computer Applications 105, no. 7 (2014): 30–33. https://doi.org/10.5281/zenodo.33240.

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Speed and power is the major constraint in modern digital design so it is required to design the high speed, less number of transistors as a prime consideration. The low power carry look ahead adder using static CMOS transmission gate logic that overcomes the limitation of series connected pass transistors in the carry propagation path. In this approach it is required to find the longest critical paths in the multi-bit adders and then shortening the path to reduce the total critical path delay. The design simulation on microwind layout tool shows the worst-case delay in ns and total power cons

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25

RH, Naik, Ganesh D, Lakshmi Tirupathamma M, Siva Sai K, and Venkateswarlu D. "Optimized FFA-Based 3-Parallel Polyphase FIR Filter Using Modified Brent-Kung Adder and Booth Multiplier for VLSI Applications." International Journal for Modern Trends in Science and Technology 11, no. 03 (2025): 128–35. https://doi.org/10.5281/zenodo.15084889.

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Digital Signal Processing (DSP) plays a crucial role in biomedical applications, as well as in voice and image processing. Digital filters serve as fundamental building blocks for DSP applications, signal analysis, and estimation. With advancements in VLSI technology, the complexity of designing digital filters has been significantly reduced, enabling efficient on-chip architectures for DSP applications.Finite Impulse Response (FIR) filters, which have a finite-duration impulse response, are widely used in DSP systems due to their stability and linear-phase characteristics, in contrast to Infi

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26

Alkurwy, Salah Hasan, and Isam Salah Hameed. "A novel pipelined carry adder design based on half adder." Indonesian Journal of Electrical Engineering and Computer Science 25, no. 2 (2022): 763–70. https://doi.org/10.11591/ijeecs.v25.i2.pp763-770.

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A new design of binary parallel adder circuit is presented in this paper. The pipeline technique is applied to implement a group of a half adder (HA) blocks to architect the proposed adder. The pipelined carry adder (PCA) method is suitable for carrying out the desired adder by using the HA circuits of XOR and AND gates. The applied technique reduces the critical path delay by 27% compared with the ripple carry adder (RCA) and relatively lowers logic gates by 55% compared with the carry look-ahead adder (CLA). The coded design of the proposed circuit is implemented and simulated on the Cyclone

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27

Simarpreet, Singh Chawla, Aggarwal Swapnil, Anshika, and Goel Nidhi. "Design and Analysis of a High Speed Carry Select Adder." International Daily journal, Discovery Publication 44, no. 201 (2015): 33–39. https://doi.org/10.5281/zenodo.32686.

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An optimal high-speed and low-power VLSI architecture requires an efficient arithmetic processing unit that is optimized for speed and power consumption. Adders are one of the widely used in digital integrated circuit and system design. High speed adder is the necessary component in a data path, e.g. Microprocessors and a Digital signal processor. The present paper proposes a novel high-speed adder by combining the advantages of Carry Look Ahead Adder (CLAA) and Carry Select Adder (CSA), devising a hybrid CSA. In the proposed adder, CSA uses CLAA technology to generate the carry bits for each

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Simarpreet, Singh Chawla, Aggarwal Swapnil, Anshika, and Goel Nidhi. "Design and Analysis of a High Speed Carry Select Adder." Discovery The International Daily journal 44, no. 201 (2015): 33–39. https://doi.org/10.5281/zenodo.33104.

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An optimal high-speed and low-power VLSI architecture requires an efficient arithmetic processing unit that is optimized for speed and power consumption. Adders are one of the widely used in digital integrated circuit and system design.High speed adder is the necessary component in a data path, e.g. Microprocessors and a Digital signal processor. The present paper proposes a novel high-speed adder by combining the advantages of Carry Look Ahead Adder (CLAA) and Carry Select Adder (CSA), devising a hybrid CSA. In the proposed adder, CSA uses CLAA technology to generate the carry bits for each s

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RamakrishnaReddy, Eamani, Nallathambi Vinodhkumar, and Asaithambi Sasikumar. "A low-power high speed full adder cell using carbon nanotube field effect transistors." A low-power high speed full adder cell using carbon nanotube field effect transistors 31, no. 1 (2023): 134–42. https://doi.org/10.11591/ijeecs.v31.i1.pp134-142.

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The adder circuit is basic component of arithmetic logic design and that is the most important block of processor architecture. Moreover, power consumption is the main concern for real-time digital systems. In recent times, carbon nanotube field effect transistors (CNTFET) used for arithmetic circuit designs with high performance. A creative substitute for highspeed, less power, and small size in area designs is the CNTFET. This paper presents 1- bit full adder with CNTFETs for low power and high performance. Using the computer aided design (CAD) tool the proposed 1-bit full adder design model

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Akbar, Muhammad Ali, Bo Wang, and Amine Bermak. "A High-Speed Parallel Architecture for Ripple Carry Adder with Fault Detection and Localization." Electronics 10, no. 15 (2021): 1791. http://dx.doi.org/10.3390/electronics10151791.

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Ripple-carry adder (RCA) is among the most common type of adder. However, it is not preferred in many applications because of its high latency. In this paper, two architectures of high-speed parallel RCA (PRCA) along with fault detection and localization are proposed, with reduced overhead as compared with carry look-ahead adder (CLA). In the proposed approach, RCA is divided into blocks, where the initial carry input for each block will be generated by a carry look-ahead logic unit. The delay is reduced by 43.81% as compared with the conventional 64-bit RCA design. The delay is further reduce

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31

Swami G, Narayan, Bhuvana D T, Keerthana M R, Ankita B, and Manoja E. "Optimization of Delay and Area for Approximate Radix-8 Booth Multiplier." INTERANTIONAL JOURNAL OF SCIENTIFIC RESEARCH IN ENGINEERING AND MANAGEMENT 08, no. 12 (2024): 1–6. https://doi.org/10.55041/ijsrem39405.

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This paper investigates the optimization of Radix-8 Booth Multipliers, which are essential for efficient arithmetic operations in modern digital systems, particularly in applications such as digital signal processing, telecommunications, and image processing where rapid and accurate calculations are crucial. The study aims to enhance performance by focusing on reducing both delay and area while ensuring that acceptable accuracy levels are maintained for error-tolerant applications. To achieve these optimization goals, we compare three methodologies: the Carry Save Adder (CSA), the Kogge Stone

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32

Eppili, Jaya, Sri B. Sai, Kumar P. Akshay, Kumar O. Hem, D. Sunil, and R. Rajesh. "VLSI implementation of Kogge-Stone Adder for low-power applications." i-manager's Journal on Digital Signal Processing 11, no. 1 (2023): 9. http://dx.doi.org/10.26634/jdp.11.1.19372.

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The adder is a vital part of the Central Processing Unit (CPU) that can perform computational operations. It is used in digital components, mainly in the design of integrated circuits. Recent decades have seen a sharp rise in demand for mobile electronics, which has increased the need for highly efficient Very Large-Scale Integration (VLSI) structures. All operations must be computed using low-power, space-efficient designs that run faster. The Kogge-Stone adder (KSA) is an extension of the carry look-ahead adder which is used for performing fast addition in high-performance computing systems.

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33

Alkurwy, Salah Hasan, and Isam Salah Hameed. "A novel pipelined carry adder design based on half adder." Indonesian Journal of Electrical Engineering and Computer Science 25, no. 2 (2022): 763. http://dx.doi.org/10.11591/ijeecs.v25.i2.pp763-770.

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<span lang="EN-US">A new design of binary parallel adder circuit is presented in this paper. The pipeline technique is applied to implement a group of a half adder (HA) blocks to architect the proposed adder. The pipelined carry adder (PCA) method is suitable for carrying out the desired adder by using the HA circuits of XOR and AND gates. The applied technique reduces the critical path delay by 27% compared with the ripple carry adder (RCA) and relatively lowers logic gates by 55% compared with the carry look-ahead adder (CLA). The coded design of the proposed circuit is implemented and

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Gurusamy, L., Muhammad Kashif, and Norhuzaimin Julai. "Design and Implementation of an Efficient Hybrid Parallel-Prefix Ling Adder Using 0.18micron CMOS Technology in Standard Cell Library." Applied Mechanics and Materials 833 (April 2016): 149–56. http://dx.doi.org/10.4028/www.scientific.net/amm.833.149.

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This This paper addresses a novel technique in implementing hybrid parallel-prefix adder (HPA) incorporating prefix-tree structure with Carry Select Adder (CSEA). Ling’s algorithm is used to optimise the pre-processing blocks (white nodes) and intermediate Generate-Propagate blocks (Black nodes) of the prefix tree to minimise the congestion of wires which contributes to reduction in chip size and to improve performance. The resulting prefix-tree arrangement is then merged into a sequence of modified CSEA. Experimental results show that HPA has speed improvement of 62% and 13% power reduction i

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Chirag, M., and K.B.Ramesh. "Design and Implementation of 4-bit Multiplier using Vedic System." Journal of VLSI Design and its Advancement 7, no. 2 (2024): 38–44. https://doi.org/10.5281/zenodo.12635137.

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<em>An efficient and fast 4-bit multiplier is designed, analyzed and presented. It is achieved using a Carry-Look Ahead adder, in short CLA adder, circuit. The ancient technique known presently as ‘Vedic Mathematics’ and is based on </em><em>'Urdhva Tiryakbhyam sutra' algorithm. This type of modification increases the speed of the asked multiplication by nearly 45%. It further delves into the differences between the traditional method and the proposed method. This article expands further about all the topics mentioned above.</em>

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V. Kumaravel, M. Pooja, S. Gayathri Priya, J. Jagan Babu,. "Low Power and Area Efficient Borrow Save Adder for MAC Unit in VLSI Application." INFORMATION TECHNOLOGY IN INDUSTRY 9, no. 2 (2021): 828–34. http://dx.doi.org/10.17762/itii.v9i2.420.

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In hypercompetitive embedded system environment, to develop the unique characteristic of machine learning computation for more efficient MAC design for reduced both the area and power. In this paper, Multiply–accumulate (MAC) computations account for a large part of machine learning accelerator operations use in pipelined structure is usually adopted to improve the performance by reducing the number of adder circuits. The proposed a pipelining method that eliminates some of the flip-flops in carry look adder in selectively. Here, introduce the applying the Feed forward-Cutset-Free (FCF) pipeli

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Xuan, Hong Wei, Ruo Yu Yu, and Hai Huang. "CORDIC Based Fast Algorithm for Power of Two Point DCT." Applied Mechanics and Materials 427-429 (September 2013): 1870–73. http://dx.doi.org/10.4028/www.scientific.net/amm.427-429.1870.

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In this paper, we present a coordinate rotation digital computer (CORDIC) based fast algorithm for power of two point DCT. The proposed algorithm has some distinguish advantages, such as regular data flow like the Cooley-Tukey FFT, identical post-scaling factor, and the rotation angles of the CORDICs in DCT are arithmetic sequence. By using the sum formula and double angle formula, we dramatically reduce the CORDIC types in the proposed algorithm. For the purpose of gain fast speed, we use Carry Save Adder (CSA) as the basic cell of each part and Carry Look-ahead Adder (CLA) to produce the out

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Reddy Eamani, Ramakrishna, Vinodhkumar Nallathambi, and Sasikumar Asaithambi. "A low-power high speed full adder cell using carbon nanotube field effect transistors." Indonesian Journal of Electrical Engineering and Computer Science 31, no. 1 (2023): 134. http://dx.doi.org/10.11591/ijeecs.v31.i1.pp134-142.

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The adder circuit is basic component of arithmetic logic design and that is the most important block of processor architecture. Moreover, power consumption is the main concern for real-time digital systems. In recent times, carbon nanotube field effect transistors (CNTFET) used for arithmetic circuit designs with high performance. A creative substitute for highspeed, less power, and small size in area designs is the CNTFET. This paper presents 1- bit full adder with CNTFETs for low power and high performance. Using the computer aided design (CAD) tool the proposed 1-bit full adder design model

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.Sravanthi, M. "Design of Low POWER CLA using Coding-Based Partial MRF Method." INTERNATIONAL JOURNAL OF SCIENTIFIC RESEARCH IN ENGINEERING AND MANAGEMENT 09, no. 04 (2025): 1–9. https://doi.org/10.55041/ijsrem44997.

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One of the biggest challenges in designing circuits with low power consumption is reliability. It is common practice to employ Markov Random Field (MRF) approaches to deal with random noise in circuits operating at very low voltages. For smaller, simpler circuits, these function well, but for larger, more intricate designs, they become challenging. This work presents a novel method known as coding-based partial MRF (CPMRF). The CPMRF pair, which utilizes a shared MRF network to conserve space, is a unit that combines several logic processes. Additionally, by employing a coding technique that r

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Sasipriya, P., and V. S Kanchana Bhaaskaran. "Low power combinational and sequential logic circuits using clocked differential cascode adiabatic logic (CDCAL)." International Journal of Engineering & Technology 7, no. 3 (2018): 1548. http://dx.doi.org/10.14419/ijet.v7i3.14632.

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This paper presents the Clocked Differential Cascode Adiabatic Logic (CDCAL), the quasi-adiabatic dynamic logic that can operate efficiently at GHz-class frequencies. It is operated by two phase sinusoidal power clock signal for the adiabatic pipeline. The proposed logic uses clocked control transistor in addition to the less complex differential cascode logic structure to achieve low power and high speed operation. To show the feasibility of implementation of both combinational and sequential logic circuits using the proposed logic, the CLA adder and counter have been selected. To evaluate th

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CHANG, ROBERT C., PO-CHUNG HUNG, and HSIN-LEI LIN. "LOW POWER ENERGY RECOVERY COMPLEMENTARY PASS-TRANSISTOR LOGIC." Journal of Circuits, Systems and Computers 15, no. 04 (2006): 491–504. http://dx.doi.org/10.1142/s0218126606003271.

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A proposed adiabatic logic called Energy Recovery Complementary Pass-transistor Logic (ERCPL) is presented in this paper. It operates with a two-phase nonoverlapping power-clock supply. It uses bootstrapping to achieve efficient power saving and eliminates any nonadiabatic losses on the charge-steering devices. A scheme is used to recover part of the energy trapped in the bootstrapping nodes. We compare the energy dissipation between ERCPL and other logic circuits by simulation. Simulation results show that a pipelined ERCPL carry look-ahead adder can achieve a power reduction of 80% over the

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N B V V S S Mani Manjari and Dr. S V R K RAO. "High Throughput DWT Architecture for Signal Processing." International Journal of Scientific Research in Science and Technology 11, no. 4 (2024): 79–88. http://dx.doi.org/10.32628/ijsrst24114109.

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The Discrete Wavelet Transform (DWT) is essential in signal processing systems because it is capable of accurately recording both frequency and time-domain features. Nevertheless, the computational intricacy of DWT presents notable obstacles to processing in real-time, particularly in circumstances with large data consumption. This study presents a VLSI technology designed to accelerate DWT processing utilizing CMOS gates. The goal is to improve throughput while maintaining area efficiency. The architecture utilizes parallelism and pipelining techniques to take use of the fundamental redundanc

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Sasipriya, P., and V. S. Kanchana Bhaaskaran. "Design of Low Power VLSI Circuits Using Two Phase Adiabatic Dynamic Logic (2PADL)." Journal of Circuits, Systems and Computers 27, no. 04 (2017): 1850052. http://dx.doi.org/10.1142/s0218126618500524.

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This paper presents the quasi-adiabatic logic for low power powered by two phase sinusoidal clock signal. The proposed logic called two phase adiabatic dynamic logic (2PADL) realizes the advantages of energy efficiency through the use of gate overdrive and reduced switching power. It has a single rail output and the proposed logic does not require the complementary input signals for any of its variables. The 2PADL logic is operated by two complementary clock signals acting as power supply. The validation of the proposed logic is carried out through practical circuits such as (i) sequential cir

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Saini, Jitendra Kumar, Avireni Srinivasulu, and Renu Kumawat. "A Low Power - High Speed CNTFETs Based Full Adder Cell With Overflow Detection." Micro and Nanosystems 11, no. 1 (2019): 80–87. http://dx.doi.org/10.2174/1876402911666190211154634.

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The transformation from the development of enabling technology to mass production of consumer-centric semiconductor products has empowered the designers to consider characteristics like robustness, compactness, efficiency, and scalability of the product as implicit pre-cursors. The Carbon Nanotube Field Effect Transistor (CNFET) is the present day technology. In this manuscript, we have used CNFET as the enabling technology to design a 1-bit Full Adder (1b-FA16) with overflow detection. The proposed 1b-FA16 is designed using 16 transistors. Finally, the proposed 1b-FA16 is further used to desi

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Barik, Ranjan Kumar, Manoranjan Pradhan, and Rutuparna Panda. "Efficient Conversion Technique from Redundant Binary to NonRedundant Binary Representation." Journal of Circuits, Systems and Computers 26, no. 09 (2017): 1750135. http://dx.doi.org/10.1142/s0218126617501353.

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Redundant Binary (RB) to Two’s Complement (TC) converter offers nonredundant representation. However, the sign bit of TC representation has to be handled using nonstandard hardware blocks. The concept of Inverted encoding of negative weighted bits (IEN) eliminates the need of sign extension and offers design only using predefined hardware blocks. NonRedundant Binary (NRB) representation refers to both conventional and IEN representations. The NRB representation is also useful considering problem related to shifting in Carry Save (CS) representation of a RB number. In this paper, we have propos

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Nikhita, Matti*1 Rohini Hongal 2. R. B. Shettar 3. "PERFORMANCE ANALYSIS OF DIFFERENT N-BIT ADDERS USING REVERSIBLE LOGIC ON FPGA BOARD USING CHIPSCOPE." INTERNATIONAL JOURNAL OF ENGINEERING SCIENCES & RESEARCH TECHNOLOGY 6, no. 8 (2017): 307–18. https://doi.org/10.5281/zenodo.843985.

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In current scenario, high-performance chips releasing large amounts of heat impose practical limitation. Reversible circuits that conserve information, by uncomputing bits instead of throwing them away. Reversible logic design attracting more interest due to its low power consumption. The paper gives brief idea to build variety of n-bit adders like Ripple carry adder, Carry look ahead adder, Carry save adder, Carry skip adder and Carry select adder circuits using the basic reversible gate like Peres gate, TSG, MTS, Taffoli, HNG etc. The designed adders are verified using chipscope on FPGA plat

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Bhati, Satyandra, Neeraj Sharma, and Meetu Nag. "Performance Analysis of High Speed and Low Power Binary Adders." IOP Conference Series: Materials Science and Engineering 1224, no. 1 (2022): 012026. http://dx.doi.org/10.1088/1757-899x/1224/1/012026.

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Abstract In all the arithmetic operations, addition is one of the most important and initial operations used in most of the mathematical equations. The operation is performed by many adders present in the digital world. These adders give us carries with preferred delay and power. The three main features like structure, logic, and compact circuit layout help design a better adder. This Paper aims to analyse and compare various additions for high-speed, low-power and fast calculation. The various adder designs seen in digital signal processing applications require computationally efficient addin

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Efstathiou, Costas, Zaher Owda, and Yiorgos Tsiatouhas. "New High-Speed Multioutput Carry Look-Ahead Adders." IEEE Transactions on Circuits and Systems II: Express Briefs 60, no. 10 (2013): 667–71. http://dx.doi.org/10.1109/tcsii.2013.2278088.

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Becker, Bernd, and Reiner Kolla. "On the Construction of Optimal Time Adders." Fundamenta Informaticae 12, no. 2 (1989): 205–20. http://dx.doi.org/10.3233/fi-1989-12207.

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In this paper we present the design of a novel optimal time adder: the conditional carry adder. In order to perform addition a tree-like combination of multiplexer cells is used in the carry computation part. We show that, for the complete conditional carry adder, this results in an overall computation time which seems to be substantially shorter than for any other known (optimal time) adder (e.g. carry look ahead adders ([5]) or conditional sum adders ([12])). The second part of this paper contains a uniform approach to the computation of the carry function resulting in seven different classe

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HAMDI, Belgacem, Khaled Ben Khalifa, and Aymen FRADI. "HYBRID-CMOS LOGIC STYLE DESIGN FOR FAST SELF-CHECKING ADDERS DATA PATHS." INTERNATIONAL JOURNAL OF COMPUTERS & TECHNOLOGY 10, no. 6 (2013): 1771–78. http://dx.doi.org/10.24297/ijct.v10i6.7025.

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In this paper we present an efficient design for self-checking fast adders data paths. We investigate the implementation of concurrent error detection fast adders: carry look-ahead, Carry skip, Carry-select and Conditional-Sum adders. To achieve a low overhead, low power design, we use hybrid-CMOS logic style and combine Conventional CMOS and CMOS Pass transistor Logic (CPL). The proposed schemes are Totally Self-Checking (TSC). They are fully differential and checked by dual-rail and parity codes.

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