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Journal articles on the topic 'Cascaded Integrator Comb filters'

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Published: 3 June 2025

Last updated: 20 July 2025

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Amrane, Raouf, Youcef Brik, Samir Zeghlache, Mohamed Ladjal, and Djamel Chicouche. "Sampling Rate Optimization for Improving the Cascaded Integrator Comb Filter Characteristics." Traitement du Signal 38, no. 1 (2021): 97–103. http://dx.doi.org/10.18280/ts.380110.

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The cascaded integrator comb (CIC) filters are characterized by coefficient less and reduced hardware requirement, which make them an economical finite impulse response (FIR) class in many signal processing applications. They consist of an integrator section working at the high sampling rate and a comb section working at the low sampling rate. However, they don’t have well defined frequency response. To remedy this problem, several structures have been proposed but the performance is still unsatisfactory. Thence, this paper deals with the improvement of the CIC filter characteristics by optimizing its sampling rate. This solution increases the performance characteristics of CIC filters by improving the stopband attenuation and ripple as well as the passband droop. Also, this paper presents a comparison of the proposed method with some other existing structures such as the conventional CIC, the sharpened CIC, and the modified sharpened CIC filters, which has proven the effectiveness of the proposed method.

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Kwentus, A. Y., Zhongnong Jiang, and A. N. Willson. "Application of filter sharpening to cascaded integrator-comb decimation filters." IEEE Transactions on Signal Processing 45, no. 2 (1997): 457–67. http://dx.doi.org/10.1109/78.554309.

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Dudarin, A., G. Molnar, and M. Vucic. "Optimum multiplierless compensators for sharpened cascaded‐integrator‐comb decimation filters." Electronics Letters 54, no. 16 (2018): 971–72. http://dx.doi.org/10.1049/el.2018.5114.

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Babic, Djordje, and Markku Renfors. "Decimation by non-integer factor in software radio receivers." Facta universitatis - series: Electronics and Energetics 16, no. 3 (2003): 365–75. http://dx.doi.org/10.2298/fuee0303365b.

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The sampling rate conversion is a critical functionality of the software radio receiver. Because the signals of different system standards have incommensurate symbol/sampling rates and a common Analog-to Digital Converter (ADC) is to be used for all supported standards, the decimation factor may become very difficult non-integer number. This paper gives overviews and comparisons of two efficient fractional decimator structures based on Cascaded Integrator-Comb (CIC) filters and low order polynomialbased interpolation filters.

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Agarwal, Ashok, and Lakshmi Bopanna. "Low Latency Area-Efficient Distributed Arithmetic Based Multi-Rate Filter Architecture for SDR Receivers." Journal of Circuits, Systems and Computers 27, no. 08 (2018): 1850133. http://dx.doi.org/10.1142/s0218126618501335.

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In software defined radio (SDR) receivers, sample rate conversion (SRC) and channelization are two computational intensive tasks. Coefficient-less cascaded-integrator-comb (CIC) filters achieve SRC with low computational complexity, but the design of its gain droop compensation filter involves coefficients. These coefficients vary with the change in radio standards. In this paper, an architecture for variable digital filter (VDF) for gain droop compensation employing a set of fixed coefficient sub-filters and multi-dimensional polynomials in terms of spectral parameters is realized based on distributed arithmetic (DA). As the coefficients in the sub-filters are fixed, the proposed method uses ROM-based LUTs giving rise to low computational complexity. The proposed DA–VDF filter is synthesized on an application specific integrated circuit (ASIC) employing CMOS 90[Formula: see text]nm technology using Synopsis Design Complier. The proposed architecture achieves low latency at a reduced area delay product (ADP) of 78% and an efficiency of 72% in energy per sample (EPS) when compared with the conventional MAC-based architecture.

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Sengar, Suverna. "Performance Evaluation of Cascaded Integrator-Comb (CIC) Filter." IOSR Journal of Engineering 02, no. 02 (2012): 222–28. http://dx.doi.org/10.9790/3021-0202222228.

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Stošić, Biljana P., and Vlastimir D. Pavlović. "Using Cascaded Non-Identical CIC Sections to Improve Insertion Loss." Journal of Circuits, Systems and Computers 24, no. 06 (2015): 1550092. http://dx.doi.org/10.1142/s0218126615500929.

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A novel class of cascaded-integrator-comb (CIC) filter functions, which preserve the CIC filter simplicity avoiding the multipliers, is proposed in this paper. The proposed class is designed using several cascaded non-identical CIC sections. The paper provides its non-recursive and recursive forms, as well as frequency response. Compared with classical CIC finite impulse response (FIR) filters designed novel class shows excellent performances in term of insertion loss in stopband and selectivity. To verify the behavior of the proposed novel class of CIC FIR filter functions, several illustrative examples are provided. Also, comparisons of the novel filter class with existing classical CIC structures and some recent improvements given in the literature are provided. For the same level of a constant group delay of 31.5 s, a classical CIC filter function has insertion loss of 115.176 dB, and proposed novel filter function has 136.757 dB. It has achieved significant improvement of 21.581 dB or approximately about 20%.

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Srivastava, Ajeet Kumar, and Krishna Raj. "DESIGN OF AN OPTIMIZED CIC COMPENSATION FILTER USING A FIR FILTER BASED ON CSD GROUPING." ICTACT Journal on Microelectronics 8, no. 4 (2023): 1455–61. https://doi.org/10.21917/ijme.2023.0251.

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In high-speed signal processing, the multirate transformation is a widely used method for decimation and interpolation. The comb-based decimation filters with low complexity and strong alias rejection are preferably used in wireless applications. A linear phase FIR filter namely a cascaded-integrator-comb (CIC) filter can be used as a decimation filter. Since this filter doesn't contain a multiplier, it occupies less area and has a higher speed than other decimation filters. In digital systems, the redundant number system is frequently used to enhance the computational efficiency, which can then be further improved by an architectural change made at the circuit level. However, the frequency characteristics are also optimized by reducing the passband droop and increasing attenuation in the folding band using a compensation FIR filter. In this paper, a design of a CIC filter by using a signed digit (SD) number system-based compensation filter has been proposed and analyzed. The analysis of delay and hardware requirements in filter operation was performed. The results show improvements in average operating frequency and a reduction in LUTs of 12.32% and 15.65%, respectively, in comparison to other techniques. Further, the analysis of frequency characteristics of the proposed filter design shows that the average passband droop is reduced by 24.60% and attenuation in the folding band is increased by 22.01% in comparison to binary based filter structures.

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Zheng, Qiang, and Cheng Ma. "The Design of Lock-in Amplifier Based on DSP Builder." Advanced Materials Research 718-720 (July 2013): 733–38. http://dx.doi.org/10.4028/www.scientific.net/amr.718-720.733.

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Lock-in amplifier is widely used to detect weak signals from significant background noise. In this paper, an FPGA-based Lock-in amplifier is implemented on the DSP Builder platform to measure impedance between biological cells and electrodes. To improve the measuring accuracy, a narrow band low pass filter with low cut off frequency was implemented. This low pass filter consists of a five-stage cascaded integrator-comb filter, two half band filters and a FIR low pass filter. Simulation shows that with a system clock of 10MHz, the cut off frequency of the low pass filter is lower than 20Hz. Experiments demonstrate that the implemented lock-in amplifier is able to detect weak signal with strong noise, making it an attractive approach to implement lock-in amplifiers which is more flexible and can meet the needs for specified measurements.

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Yang, Jieyu, Guang Chen, Lidan Lu, et al. "Flexibly Reconfigurable Kerr Micro-Comb Based on Cascaded Si3N4 Micro-Ring Filters." Photonics 12, no. 7 (2025): 661. https://doi.org/10.3390/photonics12070661.

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In recent years, micro-combs, due to their compact structure and high efficiency, have proven to be a practical solution for optical sources. In this paper, an approach to flexibly modulating micro-combs is proposed, and a simulation platform based on Si3N4 micro-combs with highly integrated, tunable, and reconfigurable features is built. By means of the Lugiato–Lefever equation model, the dynamic evolution process of micro-combs is analyzed, and a micro-ring resonator is designed with a free spectral range of 7.24 nm, an effective mode area of 1.0829µm2, and coherent comb lines spanning over 125 THz. Cascaded silicon nitride micro-ring filters are utilized to obtain reconfigurable modulation effects for Kerr-frequency micro-combs. Due to the significance of flexibly controlled optical sources with high-repetition rates and multiple channels for system-on-chip, our proposal has potential in photonic integrated circuit systems, such as high-density photonic computing and large-capacity optical communications, in the future.

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Mohammed, Khalid Khaleel, and Mohammed Idrees Dawod. "Design and Implementation of Decimation Filter for 13-bit Sigma-Delta ADC Based on FPGA." Tikrit Journal of Engineering Sciences 23, no. 2 (2022): 21–28. http://dx.doi.org/10.25130/tjes.23.2.03.

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A 13 bit Sigma-Delta ADC for a signal band of 40K Hz is designed in MATLAB Simulink and then implemented using Xilinx system generator tool. The first order Sigma-Delta modulator is designed to work at a signal band of 40 KHz at an oversampling ratio (OSR) of 256 with a sampling frequency of 20.48 MHz. The proposed decimation filter design is consists of a second order Cascaded Integrator Comb filter (CIC) followed by two finite impulse response (FIR) filters. This architecture reduces the need for multiplication which is need very large area. This architecture implements a decimation ratio of 256 and allows a maximum resolution of 13 bits in the output of the filter. The decimation filter was designed and tested in Xilinx system generator tool which reduces the design cycle by directly generating efficient VHDL code. The results obtained show that the overall Sigma-Delta ADC is able to achieve an ENOB (Effective Number Of Bit) of 13.71 bits and SNR of 84.3 dB.

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Takei, Hironobu, Shogo Nakamura, Hiroto Saitoh, and I. Nyoman Sukadana. "An implementation of realtime speech speed control system using hierarchical cascaded integrator and comb filters." Journal of the Acoustical Society of America 120, no. 5 (2006): 3216. http://dx.doi.org/10.1121/1.4788159.

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Meyer-Baese, U., S. Rao, J. Ramírez, and A. García. "Cost-effective Hogenauer cascaded integrator comb decimator filter design for custom ICs." Electronics Letters 41, no. 3 (2005): 158. http://dx.doi.org/10.1049/el:20057000.

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Guan, Yanhao, Yi Lu, and Guolin Shao. "Accelerated cascade integrator comb filter with a new non-recursive GPU implementation." Journal of Combinatorial Mathematics and Combinatorial Computing 124 (March 16, 2025): 59–74. https://doi.org/10.61091/jcmcc124-04.

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The Cascaded Integrator Comb (CIC) decimation filter is a pivotal technology extensively employed in digital signal processing (DSP). This paper delves into a comprehensive examination of the CIC algorithm within software-defined radio (SDR) systems from the perspective of parallel computing and introduces a novel Non-Recursive Implementation (NR-I) on an NVIDIA GPU using CUDA. The NR-I approach significantly reduces computational load by unfolding the recursive CIC structure with pre-derived Unfold Factors. Further optimization was achieved through data-transfer enhancements using PM Implementation (PM-I) and ODT Implementation (ODT-I). Experimental results demonstrate that NR-I achieves a speedup of over 449.48. Additionally, the data-transfer optimizations resulted in substantial performance improvements, with PM-I and ODT-I reducing execution time by 43.24% and 64.22%, respectively. The GPU implementation’s speedup is significantly greater than that of OpenMP, ranging from 3.34 to 10.22 times. These results underscore the effectiveness of the proposed Non-Recursive Implementation in accelerating time-intensive and data-intensive computations.

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Gear, Kyle W., Alfonso Sánchez-Macián, and Juan Antonio Maestro. "Reduced length redundancy adaptive protection for the cascaded integrator-comb interpolation filter on FPGA." Microelectronics Reliability 118 (March 2021): 114043. http://dx.doi.org/10.1016/j.microrel.2021.114043.

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Fernandez-Vazquez, Alfonso, and Gordana Jovanovic Dolecek. "On Passband and Stopband Cascaded-Integrator-Comb Improvements Using a Second Order IIR Filter." TELKOMNIKA (Telecommunication Computing Electronics and Control) 10, no. 1 (2012): 61. http://dx.doi.org/10.12928/telkomnika.v10i1.760.

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Tang, Wenming, Guixiong Liu, and Ruobo Lin. "Design of Polyphase Cascaded Integrator Comb Interpolator Filter for Ultrasonic Phased Array Time Delays." International Journal of Engineering and Technology 9, no. 4 (2017): 304–9. http://dx.doi.org/10.7763/ijet.2017.v9.988.

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Han, Mangi, and Youngmin Kim. "Efficient Implementation of Multichannel FM and T-DMB Repeater in FPGA with Automatic Gain Controller." Electronics 8, no. 5 (2019): 482. http://dx.doi.org/10.3390/electronics8050482.

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In this study, we implemented a high-performance multichannel repeater, both for FM and T-Digital Multimedia Broadcasting (DMB) signals using a Field Programmable Gate Array (FPGA). In a system for providing services using wireless communication, a radio-shaded area is inevitably generated due to various obstacles. Thus, an electronic device that receives weak or low-level signals and retransmits them at a higher level is crucial. In addition, parallel implementation of digital filters and gain controllers is necessary for a multichannel repeater. When power level is too low or too high, the repeater is required to compensate the power level and ensure a stable signal. However, analog- and software-based repeaters are expensive and they are difficult to install. They also cannot effectively process multichannel in parallel. The proposed system exploits various digital signal-processing algorithms, which include modulation, demodulation, Cascaded Integrator Comb (CIC) filters, Finite Impulse Response (FIR) filters, Interpolated Second Ordered Polynomials (ISOP) filters, and Automatic Gain Controllers (AGCs). The newly proposed AGC is more efficient than others in terms of computation amount and throughput. The designed digital circuit was implemented by using Verilog HDL, and tested using a Xilinx Kintex 7 device. As a result, the proposed repeater can simultaneously handle 40 FM channels and 6 DMB channels in parallel. Output power level is also always maintained by the AGC.

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Li, Pengbo, Guanyu Lin, Jianbo Chen, and Jianing Wang. "Off-Axis Integral Cavity Carbon Dioxide Gas Sensor Based on Machine-Learning-Based Optimization." Sensors 24, no. 16 (2024): 5226. http://dx.doi.org/10.3390/s24165226.

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Accurately detecting atmospheric carbon dioxide is a vital part of responding to the global greenhouse effect. Conventional off-axis integral cavity detection systems are computationally intensive and susceptible to environmental factors. This study deploys an Extreme Learning Machine model incorporating a cascaded integrator comb (CIC) filter into the off-axis integrating cavity. It is shown that appropriate parameters can effectively improve the performance of the instrument in terms of lower detection limit, accuracy, and root mean square deviation. The proposed method is incorporated successfully into a monitoring station situated near an industrial area for detecting atmospheric carbon dioxide (CO2) concentration daily.

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Gear, Kyle W., Alfonso Sánchez-Macián, Francisco Garcia-Herrero, and Juan Antonio Maestro. "Two Behavioural Error Detection Techniques for the Cascaded Integrator–Comb Interpolation Filter Implemented on FPGA." Circuits, Systems, and Signal Processing 39, no. 11 (2020): 5529–42. http://dx.doi.org/10.1007/s00034-020-01418-6.

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Kang, A. S., Er Vishal Sharma, and Prof Renu Vig. "Performance analysis of CIC multirate filter in cognitive radio for efficient pulse shaping in wireless domain." International Journal of Informatics and Communication Technology (IJ-ICT) 8, no. 3 (2019): 184. http://dx.doi.org/10.11591/ijict.v8i3.pp184-190.

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<span>In this paper, the Performance Analysis of Cascade Integrator Comb Filter in context of Filter Bank Multicarrier Transmission has been presented for Cognitive radio. A benefit of the chosen technique is that, a CIC filter can be designed with a slight adjustment in parameters of interest. The entire performance of the filters designed is analyzed and evaluated by analyzing Normalized Amplitude versus Normalized Frequency plots at typical K and N values. The roll off factor plays a significant role in performance analysis of CIC filter. The results shown are a useful advance for rf design engineers working in the domain of multirate signal processing in wireless communication. To ensure the acceptable performance of Enhanced FBMC, computational complexity, and transmission burst length need to be reduced. The effect of Stop band attenuation on the edges of Magnitude and Frequency responses has been studied under constraints such as Lp, K and M during different simulation runs</span>.

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A., S. Kang, Sharma Vishal, and Vig Renu. "Performance analysis of CIC multirate filter in cognitive radio for efficient pulse shaping in wireless domain." International Journal of Informatics and Communication Technology (IJ-ICT) 8, no. 3 (2019): 184–90. https://doi.org/10.11591/ijict.v8i3.pp184-190.

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In this paper, the Performance Analysis of Cascade Integrator Comb Filter in context of Filter Bank Multicarrier Transmission has been presented for Cognitive radio. A benefit of the chosen technique is that, a CIC filter can be designed with a slight adjustment in parameters of interest. The entire performance of the filters designed is analyzed and evaluated by analyzing Normalized Amplitude versus Normalized Frequency plots at typical K and N values. The roll off factor plays a significant role in performance analysis of CIC filter. The results shown are a useful advance for rf design engineers working in the domain of multirate signal processing in wireless communication. To ensure the acceptable performance of Enhanced FBMC, computational complexity, and transmission burst length need to be reduced. The effect of Stop band attenuation on the edges of Magnitude and Frequency responses has been studied under constraints such as Lp, K and M during different simulation runs.

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Jain, Vivek, and Navneet Agrawal. "Implement Multichannel Fractional Sample Rate Convertor using Genetic Algorithm." International Journal of Multimedia Data Engineering and Management 8, no. 2 (2017): 10–21. http://dx.doi.org/10.4018/ijmdem.2017040102.

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In this paper reduce power of multichannel fractional sample rate convertor by minimized hamming distance between consecutive coefficients of filter using Genetic algorithm. The main component of multichannel fractional sample rate convertor is Cascaded multiple architecture finite impulse response filter (CMFIR filter). CMFIR is implemented by cascading of cascaded integrator-comb (CIC) & multiply accumulate architecture (MAC) FIR filter. Genetic algorithm minimizes the hamming distance between consecutive coefficients of CMFIR filter. By Minimizing the hamming distance of consecutive filter coefficient reduces the transaction from 0 to 1 or 1 to 0. These techniques reduce the switching activity of CMOS transistor which is directly reduces Dynamic power consumption by multichannel sample rate convertor, it also minimizes the total power consumption of multichannel fractional sample rate convertor. later than use genetic algorithm on 1 to 128 channel Down sample rate convertor total power reduced by 3.44% to 61.56%, dynamic power reduced by 9.09% to 56.25% .1 to 128 channel Up sample rate convertor total power reduced by 2.81% to 45.42%, dynamic power reduced by 4.76% to 56%, 1 to 128 channel fractional sample rate convertor total power reduced by 1.44% to 17.17%, dynamic power reduced by 6.25% to 19.92%.

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Teymourzaedh, Rozita. "VLSI Implementation of Novel Class of High Speed Pipelined Digital Signal Processing Filter for Wireless Receivers." American Journal of Engineering and Applied Sciences.vISSN 1941-7020 3, no. 4 (2010): 663–69. https://doi.org/10.5281/zenodo.1239903.

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The need for high performance transceiver with high Signal to Noise Ratio (SNR) has driven the communication system to utilize latest technique identified as over sampling systems. It was the most economical modulator and decimation in communication system. It has been proven to increase the SNR and is used in many high performance systems such as in the Analog to Digital Converter (ADC) for wireless transceiver. This research work presented the design of the novel class of decimation and its VLSI implementation which was the sub-component in the over sampling technique. The design and realization of main unit of decimation stage that was the Cascaded Integrator Comb (CIC) filter, the associated half band filters and the droop correction are also designed. The Verilog HDL code in Xilinx ISE environment has been derived to describe the proposed advanced CIC filter properties. Consequently, Virtex-II FPGA board was used to implement and test the design on the real hardware. The ASIC design implementation was performed accordingly and resulted power and area measurement on chip core layout. The proposed design focused on the trade-off between the high speed and the low power consumption as well as the silicon area and high resolution for the chip implementation which satisfies wireless communication systems. The synthesis report illustrates the maximum clock frequency of 332 MHz with the active core area of 0.308×0.308 mm2. It can be concluded that VLSI implementation of proposed filter architecture is an enabler in solving problems that affect communication capability in DSP application.

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Ye, Mao, Zitong Liu, and Yiqiang Zhao. "Design of a Sigma-Delta Analog-to-Digital Converter Cascade Decimation Filter." Electronics 13, no. 11 (2024): 2090. http://dx.doi.org/10.3390/electronics13112090.

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As the current mainstream high-precision ADC architecture, sigma-delta ADC is extensively employed in a wide range of domains and applications. This paper presents the design of a highly efficient cascaded digital decimation filter for sigma-delta ADCs, emphasizing the suppression of high folding band noise and the achievement of a flat passband. Additionally, this study addresses the critical balance between filter performance and power consumption. An inserting zero (IZ) filter is incorporated into a cascaded integrator comb (CIC) filter to enhance aliasing suppression. The IZ filter and compensation filter are optimized using the particle swarm optimization (PSO) algorithm to achieve greater noise attenuation and smaller passband ripple. The designed filter achieves a noise attenuation of 93.4 dB in the folding band and exhibits an overall passband ripple of 0.0477 dB within a bandwidth of 20 KHz. To decrease the power consumption in the filter design, polyphase decomposition has been applied. The filter structure is implemented on an FPGA, processing a 5-bit stream from a 64-times oversampling rate and third-order sigma-delta modulator. The signal-to-noise ratio (SNR) of the output signal reaches 91.7 dB. For ASIC design, the filter utilizes 180 nm CMOS technology with a power consumption of 0.217 mW and occupies a layout area of 0.72 mm2. The post-layout simulation result indicates that the SNR remains at 91.7 dB.

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Song, Xinrun. "Microcontroller Hardware Design and Signal Processing Optimization." Journal of Computing and Electronic Information Management 17, no. 2 (2025): 42–46. https://doi.org/10.54097/hddrb865.

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The current work outlines an in-depth methodology for designing microcontroller-based signal processing systems with significant performance improvements through the use of integrated hardware-software co-optimized techniques. The proposed architecture employs an ARM Cortex-M4F processor running at 168 MHz with optimized peripherals, including a 16-bit SAR ADC and a 12-channel DMA controller, carefully designed to support real-time signal acquisition and processing while ensuring maximum CPU efficiency. The use of cascaded integrator-comb decimation filters in conjunction with adaptive applications of normalized least mean squares algorithms achieves a significant improvement in signal-to-noise ratio, at 48.3 dB, while ensuring computational efficiency through the adoption of block processing schemes. Realization of the four-layer printed circuit board incorporates electromagnetic interference suppression mechanisms and uses differential routing schemes, resulting in a measured noise floor of -96 dBV across the operating frequency range. Empirical testing confirms a 42% reduction in power consumption compared to conventional digital signal processing solutions, with processing latencies consistently restricted to under 50 microseconds for real-time application demands. The system achieves a computational efficiency of 3.8 GFLOPS/W while supporting multiple signal processing channels simultaneously, thus supporting its relevance for resource-restricted embedded environments in industrial control and the Internet of Things.The analysis validates that the adopted design achieves a balanced trade-off among performance metrics, energy consumption, and cost for next-generation embedded signal processing systems.

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Wan, Renzhuo, Yuandong Li, Chengde Tian, et al. "Design and Implementation of Sigma-Delta ADC Filter." Electronics 11, no. 24 (2022): 4229. http://dx.doi.org/10.3390/electronics11244229.

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This paper presents a digital decimation filter based on a third-order four-bit Sigma-Delta modulator. The digital decimation filter is an important part of the Sigma-Delta ADC and is designed to make the Sigma-Delta ADC (Analog-to-Digital Converter) meets the requirements of Signal-to-Noise Ratio (SNR) not less than 120 dB and Equivalent Number of Bits (ENOB) not less than 20 bits. It adopts a three-stages cascaded structure including a Cascaded Integrator Comb (CIC) decimation filter, a Finite Impulse Response (FIR) compensation filter, and a half-band (HB) filter. This structure effectively reduces about 13% multiplier cells and memory cells. The coefficient symmetry technique and CSD (Canonic Signed Digit) coding technique are used to optimize the parameters of the filter, which further reduces the computational complexity. After optimization, the circuit area is reduced by about 15%, and the logic resources are decreased by about 23%. The Verilog hardware description language is used to describe the behavior of the digital decimation filter, and the simulation is carried out based on the VCS (Verilog Compile Simulator) platform. At the same time, the prototype verification is implemented on the Xilinx Artix-7 series FPGA, and the ADC achieves 113 dB SNR and 18.5 bits ENOB. Finally, the Sigma-Delta ADC is fabricated on SMIC 0.18 μm CMOS process with the layout area of 714.8 μm × 628.4 μm and the power consumption of 11.2 mW. The more tests for the fabricated prototypes will be performed in the future to verify that the Sigma-Delta ADC complies with the design specifications.

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Park, Chester Sungchung, Sunwoo Kim, Jooho Wang, and Sungkyung Park. "Design and Implementation of a Farrow-Interpolator-Based Digital Front-End in LTE Receivers for Carrier Aggregation." Electronics 10, no. 3 (2021): 231. http://dx.doi.org/10.3390/electronics10030231.

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A digital front-end decimation chain based on both Farrow interpolator for fractional sample-rate conversion and a digital mixer is proposed in order to comply with the long-term evolution standards in radio receivers with ten frequency modes. Design requirement specifications with adjacent channel selectivity, inband blockers, and narrowband blockers are all satisfied so that the proposed digital front-end is 3GPP-compliant. Furthermore, the proposed digital front-end addresses carrier aggregation in the standards via appropriate frequency translations. The digital front-end has a cascaded integrator comb filter prior to Farrow interpolator and also has a per-carrier carrier aggregation filter and channel selection filter following the digital mixer. A Farrow interpolator with an integrate-and-dump circuitry controlled by a condition signal is proposed and also a digital mixer with periodic reset to prevent phase error accumulation is proposed. From the standpoint of design methodology, three models are all developed for the overall digital front-end, namely, functional models, cycle-accurate models, and bit-accurate models. Performance is verified by means of the cycle-accurate model and subsequently, by means of a special C++ class, the bitwidths are minimized in a methodic manner for area minimization. For system-level performance verification, the orthogonal frequency division multiplexing receiver is also modeled. The critical path delay of each building block is analyzed and the spectral-domain view is obtained for each building block of the digital front-end circuitry. The proposed digital front-end circuitry is simulated, designed, and both synthesized in a 180 nm CMOS application-specific integrated circuit technology and implemented in the Xilinx XC6VLX550T field-programmable gate array (Xilinx, San Jose, CA, USA).

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Kalamani, M., and S. Deepthi. "Built-In Error Resilient FPGA Based CIC Filter Design for Satellite Communication." Applied Mechanics and Materials 926 (April 23, 2025): 139–49. https://doi.org/10.4028/p-j0bbi4.

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Single-event and multi-bit effects are the result of radiation and ionized particles in extreme settings like space, which can lead to random failures on any electronic component. To keep the functionality of the device unaltered, these must be reduced. FPGA plays a vital role in satellite and aerospace applications in which dynamic reconfiguration essential. Cascaded Integration Comb (CIC) filters are mostly utilized in multidata signal processing and satellite communication systems as low pass filters in rate converter modules. The configuration memory of FPGA used to design CIC filter is affected with soft errors with single and multi-bit due to high radiation in higher altitude and different environment regions. The methods like triple modular redundancy (TMR) is very effective in overcoming single event transients and single-event upsets, but incur area three times of the original module. Scrubbing is a serial process method that goes over each word in memory in search of mistakes that need to be fixed. It entails a non-negligible Time to Detect (TTD) prior to repair, in which time further functionality could happen parallely and jeopardize the system. Thus, effective multi-bit error detection correction of configuration memory in FPGA is essential in maintaining the application to work for an extended time. In this research, built-in multi-bit error correction for FPGA configuration memory is proposed. The proposed work can replace time consuming scrubbing process and high area utilizing TMR for error tolerant design. To safeguard FPGA, a multi-bit error detection and correction system is performed by using multi dimensional parity with minimum area overhead. Furthermore, the suggested method can identify and rectify error when triggered by an interrupt manager reducing time to detect (TTD).

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Mewada, Hiren K., and Jitendra Chaudhari. "Low computation digital down converter using polyphase IIR filter." Circuit World 45, no. 3 (2019): 169–78. http://dx.doi.org/10.1108/cw-02-2019-0015.

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Purpose The digital down converter (DDC) is a principal component in modern communication systems. The DDC process traditionally entails quadrature down conversion, bandwidth reducing filters and commensurate sample rate reduction. To avoid group delay, distortion linear phase FIR filters are used in the DDC. The filter performance specifications related to deep stopband attenuation, small in-band ripple and narrow transition bandwidth lead to filters with a large number of coefficients. To reduce the computational workload of the filtering process, filtering is often performed as a two-stage process, the first stage being a down sampling Hoegenauer (or cascade-integrated comb) filter and a reduced sample rate FIR filter. An alternative option is an M-Path polyphase partition of a band cantered FIR filter. Even though IIR filters offer reduced workload to implement a specific filtering task, the authors avoid using them because of their poor group delay characteristics. This paper aims to propose the design of M-path, approximately linear phase IIR filters as an alternative option to the M-path FIR filter. Design/methodology/approach Two filter designs are presented in the paper. The first approach uses linear phase IIR low pass structure to reduce the filter’s coefficient. Whereas the second approach uses multipath polyphase structure to design approximately linear phase IIR filter in DDC. Findings The authors have compared the performance and workload of the proposed polyphase structured IIR filters with state-of-the-art filter design used in DDC. The proposed design is seen to satisfy tight design specification with a significant reduction in arithmetic operations and required power consumption. Originality/value The proposed design is an alternate solution to the M-path polyphase FIR filter offering very less number of coefficients in the filter design. Proposed DDC using polyphase structured IIR filter satisfies the requirement of linear phase with the least number of computation cost in comparison with other DDC structure.

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Romero, David Ernesto Troncoso. "Simplifying Zero Rotations in Cascaded Integrator-Comb Decimators [Tips & Tricks]." IEEE Signal Processing Magazine 40, no. 3 (2023): 50–58. http://dx.doi.org/10.1109/msp.2023.3236772.

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Troncoso Romero, David Ernesto, Miriam Guadalupe Cruz Jimenez, and Uwe Meyer-Baese. "Alternative Data Paths for the Cascaded Integrator-Comb Decimator [Tips & Tricks]." IEEE Signal Processing Magazine 38, no. 3 (2021): 194–200. http://dx.doi.org/10.1109/msp.2021.3052752.

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Song, Ya Dong, and Can Mei Yang. "A Simple Method for Power System Harmonic Analysis." Applied Mechanics and Materials 556-562 (May 2014): 1932–38. http://dx.doi.org/10.4028/www.scientific.net/amm.556-562.1932.

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With the increasing use of non-linear electrical loads in power system, the harmonic pollution has become a severe problem. In this paper, we proposed a simple method for power system harmonic analysis. Cascaded adaptive comb filter is designed specifically to suppress the electric harmonic pollution. And a high-precision but easily implemented frequency estimation algorithm is presented based on least square estimation method. So the electric signal frequency fluctuation can be real-time tracked, and coefficients of the comb filters can be adaptively updated with this algorithm.

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Bu, Wen Shao, and Lei Lei Xu. "Improved Virtual-Flux-Linkage Observation Method of PWM Rectifier." Applied Mechanics and Materials 678 (October 2014): 528–32. http://dx.doi.org/10.4028/www.scientific.net/amm.678.528.

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In order to improve the virtual flux oriented vector control performance of PWM rectifier, an improved observation method of virtual flux-linkage is proposed. To avoid the relevant problems of pure integrator, and to achieve the accurate observation of the grid voltage’s phase, three first order low-pass filters are cascaded to displace the pure integrator. Based on the SVPWM modulation module and the presented algorithm, grid voltage sensorless control system of three-phase PWM rectifier is given. Simulation results have shown that: either in rectifying or inverting status, the amplitude and phase of virtual flux-linkage can be observed accurately, i.e. the control system of PWM rectifier can operate reliably without the grid voltage sensors; the presented estimation method of virtual flux-linkage is effective.

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Lan, Xiaohong, Yang Jiang, Jing Xu, et al. "All-optical microwave envelope integrator based on two cascaded 2-tap microwave photonic filters." Optics & Laser Technology 183 (May 2025): 112229. https://doi.org/10.1016/j.optlastec.2024.112229.

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ZHOU Jun, 周骏, 苑红伟 YUAN Hong-wei, 徐铁峰 XU Tie-feng, 张玲芬 ZHANG Ling-fen, and 马伟涛 MA Wei-tao. "Design of Optical Comb Filters Based on Cascaded Phase-Shifted Linearly Chirped Fiber Gratings." ACTA PHOTONICA SINICA 39, no. 6 (2010): 961–66. http://dx.doi.org/10.3788/gzxb20103906.0961.

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Jovanovic Dolecek, Gordana, and Gabriel Alejandro Martinez Novelo. "Design and FPGA Implementation of Compensator for Sharpening CIC Filter." IOP Conference Series: Materials Science and Engineering 1298, no. 1 (2023): 012017. http://dx.doi.org/10.1088/1757-899x/1298/1/012017.

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Abstract This paper presents a novel compensator design for sharpened CIC (cascade-integrator-comb) proposed in the literature. Sharpened CIC provides higher aliasing attenuation than the CIC filter. However, its passband droop is higher than the corresponding CIC filter and must be compensated. Our motivation was to design a decimator with better compensation than the one proposed in the literature. The proposed decimation filter has two coefficients and six adders. The coefficients are determined using particle swarm optimization (PSO) in MATLAB. Two designs are presented. The first one has two multipliers and six adders. The second is a multiplierless design obtained by presenting optimal coefficients in the signed power-of-two (SPT) form. The proposed design is compared with the design from the literature. The designed compensator is implemented in a field-programmable gate array (FPGA). Details of the implementation are described in the paper.

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Gupta, Subham, and Mukesh Kumar Ojha. "Real-Time Audio Enchancement: CIC Filter Design for Improved FIR Filter Performance in Digital Signal Processing." International Journal of Microsystems and IoT 2, no. 8 (2024): 1076–83. https://doi.org/10.5281/zenodo.13365586.

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The fusion of cascading integrator-comb (CIC) and finite impulse response (FIR) filters to improve audio signals in real time. The development and implementation of an operational audio enhancement system is the main goal. The CIC filter's intrinsic elegance and low computing complexity are utilized for effective decimation or interpolation. Achieving significant rate variations inside the pass band with a flat response to frequency is the key objective. After that, the FIR filter is carefully included to improve performance even more by offering increased frequency shaping and customization to satisfy particular needs for audio improvement. Choosing the right filter order, coefficients, and decimation and interpolated coefficients for the CIC filter, as well as smoothly combining it alongside the FIR filter in a current processing pipeline, are all part of the design stage. The suggested process entails establishing the needs for the system, creating and executing the two filters, and carrying out exhaustive testing and optimization. By providing a thorough method that strikes a balance between computing efficiency, latency, and<strong> </strong>performance, the work advances the area of immediate fashion sound processing and tackles the difficulties associated with audio improvement in digital systems. The proposed CIC-FIR method achieves a signal-to-noise ratio (SNR) of 12.41 dB, showcasing its performance in maintaining signal fidelity and noise levels. This SNR value serves as a key metric for evaluating the effectiveness of the proposed CIC-FIR approach.

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Liu, Can, Shenghao Gu, Mingming Sun, Ya Liu, Ying Zhang, and Jiaguang Han. "Theoretical Investigation of Terahertz Spoof Surface-Plasmon-Polariton Devices Based on Ring Resonators." Photonics 12, no. 1 (2025): 70. https://doi.org/10.3390/photonics12010070.

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Terahertz is one of the most promising technologies for high-speed communication and large-scale data transmission. As a classical optical component, ring resonators are extensively utilized in the design of band-pass and frequency-selective devices across various wavebands, owing to their unique characteristics, including optical comb generation, compactness, and low manufacturing cost. While substantial progress has been made in the study of ring resonators, their application in terahertz surface wave systems remains less than fully optimized. This paper presents several spoof surface plasmon polariton-based devices, which were realized using ring resonators at terahertz frequencies. The influence of both the radius of the ring resonator and the width of the waveguide coupling gap on the coupling coefficient are investigated. The band-stop filters based on the cascaded ring resonator exhibit a 0.005 THz broader frequency bandwidth compared to the single-ring resonator filter and achieve a minimum stopband attenuation of 28 dB. The add–drop multiplexers based on the asymmetric ring resonator enable selective surface wave outputs at different ports by rotating the ring resonator. The devices designed in this study offer valuable insights for the development of on-chip terahertz components.

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LI Guolin, 李国林, 蒋庆志 JIANG Qingzhi, 马坤 MA Kun, 焦月 JIAO Yue та 季文海 JI Wenhai. "基于CIC的数字正交锁相放大器的甲烷检测实验研究". ACTA PHOTONICA SINICA 50, № 2 (2021): 122. http://dx.doi.org/10.3788/gzxb20215002.0212001.

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Teymourzadeh, Rozita. "Design an Advance computer-aided tool for Image Authentication and Classification." American Journal of Applied Sciences Published Online ISSN: 1546-9239 10, no. 7 (2013): 696–705. https://doi.org/10.3844/ajassp.2013.696.705.

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Over the years, advancements in the fields of digital image processing and artificial intelligence have been applied in solving many real-life problems. This could be seen in facial image recognition for security systems, identity registrations. Hence a bottleneck of identity registration is image processing. These are carried out in form of image preprocessing, image region extraction by cropping, feature extraction using Principal Component Analysis (PCA) and image compression using Discrete Cosine Transform (DCT). Other processing includes filtering and histogram equalization using contrast stretching is performed while enhancing the image as part of the analytical tool. Hence, this research work presents a universal integration image forgery detection analysis tool with image facial recognition using Back Propagation Neural Network (BPNN) processor. The proposed designed tool is a multi-function smart tool with the novel architecture of programmable error goal and light intensity. Furthermore, its advance dual database increases the efficiency of a high-performance application. With the fact that, the facial image recognition will always, give a matching output or closest possible output image for every input image irrespective of the authenticity, the universal smart GUI tool is proposed and designed to perform image forgery detection with the high accuracy of ±2% error rate. Meanwhile, a novel structure that provides efficient automatic image forgery detection for all input test images for the BPNN recognition is presented. Hence, an input image will be authenticated before being fed into the recognition tool.

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Teymourzadeh, Rozita. "On-chip Implementation of High Resolution High Speed Low Area Floating point Adder Subtractor for OFDM Applications." American Journal of Engineering and Applied Sciences ISSN: 1941-7020. 3, no. 1 (2010): 25–30. https://doi.org/10.5281/zenodo.1239895.

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Fast Fourier transform (FFT) is widely applied in OFDM trance-receiver communications system. Hence Efficient FFT algorithm is always considered. This paper proposed FPGA realization of high-resolution high-speed low latency floating point adder/subtractor for FFT in OFDM trance-receiver. The design was implemented for 32 bit pipelined adder/subtractor which satisfied IEEE-754 Standard for Floating-point Arithmetic. The design was focused on the trade-off between the latency and speed improvement as well as resolution and silicon area for the chip implementation. In order to reduce the critical path and decrease the latency, the novel structure was designed and investigated. Consequently, synthesis report indicated the latency of 4 clock cycles due to each stage operated within just one clock cycle. The unique structure of designed adder well thought out resulted in 6691 equivalent gate count and lead us to obtain low area on the chip. The synthesis Xilinx ISE software provided results representing the estimated area and delay for design when it is pipelined to various depths. The report shows the minimum delay of 3.592 ns or maximum frequency of 278.42 MHz

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Teymourzadeh, Rozita. "On-Chip Implementation of Pipeline Digit-Slicing Multiplier-Less Butterfly for FFT Architecture." American Journal of Engineering and Applied Sciences. ISSN 1941-7020 3, no. 4 (2010): 757–64. https://doi.org/10.5281/zenodo.1239897.

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The need for wireless communication has driven the communication systems to high performance. However, the main bottleneck that affects the communication capability is the Fast Fourier Transform (FFT), which is the core of most modulators. This study presents an on-chip implementation of pipeline digit-slicing multiplier-less butterfly for FFT structure. The approach is taken; in order to reduce computation complexity in the butterfly, digit-slicing multiplier-less single constant technique was utilized in the critical path of Radix-2 Decimation In Time (DIT) FFT structure. The proposed design focused on the trade-off between the speed and active silicon area for the chip implementation. The new architecture was investigated and simulated with MATLAB software. The Verilog HDL code in Xilinx ISE environment was derived to describe the FFT Butterfly functionality and was downloaded to Virtex II FPGA board. Consequently, the Virtex-II FG456 Proto board was used to implement and test the design on the real hardware. As a result, from the findings, the synthesis report indicates the maximum clock frequency of 549.75 MHz with the total equivalent gate count of 31,159 is a marked and significant improvement over Radix 2 FFT butterfly. In comparison with the conventional butterfly architecture, the design that can only run at a maximum clock frequency of 198.987 MHz and the conventional multiplier can only run at a maximum clock frequency of 220.160 MHz, the proposed system exhibits better results. The resulting maximum clock frequency increases by about 276.28% for the FFT butterfly and about 277.06% for the multiplier. It can be concluded that on-chip implementation of pipeline digit-slicing multiplier-less butterfly for FFT structure is an enabler in solving problems that affect communications capability in FFT and possesses huge potentials for future related works and research areas.

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Dudarin, Aljosa, Goran Molnar, and Mladen Vucic. "Optimum multiplierless sharpened cascaded-integrator-comb filters." Digital Signal Processing, April 2022, 103564. http://dx.doi.org/10.1016/j.dsp.2022.103564.

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GUPTA, PURU, and TARUN KUMAR RAWAT. "A VLSI DSP DESIGN AND IMPLEMENTATION OF COMB FILTER USING UN-FOLDING METHODOLOGY." International Journal of Electronics Signals and Systems, October 2012, 72–77. http://dx.doi.org/10.47893/ijess.2012.1085.

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In signal processing, a comb filter adds a delayed version of a signal to itself, causing constructive and destructive interference. Comb filters are used in a variety of signal processing applications that is Cascaded Integrator-Comb filters, Audio effects, including echo, flanging, and digital waveguide synthesis and various other applications. Comb filter when implemented has lower through-put as the sample period can not be achieved equal to the iteration bound because node computation time of comb filter is larger than the iteration bound. Hence throughput remains less. This paper present the comb filter using one of the methodology needed to design custom or semi custom VLSI circuits named as Un-Folding which increases the throughput of the comb filter. Un-Folding is a transformation technique that can be applied to a DSP program to create a new program describing more than one iteration of the original program. It can unravel hidden con-currency in digital signal processing systems described by DFGs. Therefore, unfolding has been used for the sample period reduction of the comb filter for its higher throughput.

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Jain, Vivek, Prasun Chakrabarti, Massimo Mitolo, et al. "A Power-Efficient Multichannel Low-Pass Filter Based on the Cascaded Multiple Accumulate Finite Impulse Response (CMFIR) Structure for Digital Image Processing." Circuits, Systems, and Signal Processing, February 10, 2022. http://dx.doi.org/10.1007/s00034-022-01960-5.

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AbstractThe author offers a power-efficient multichannel low-pass filter for digital image processing based on the cascade multiple accumulate finite impulse response (CMFIR) structure in this study. The CMFIR filter was created using the outputs of a linear time-invariant system (LTI), which was built using a cascaded integrator comb (CIC) and a MAC low-pass filter. The sample rate convertor based on CIC filters effectively conducts decimation or interpolation. The sample rate convertor with the CIC filter can only accommodate narrowband transmissions and so cannot be utilized for wideband signals. The MAC architecture-based sample rate convertor is a good solution for high-bandwidth signals, but it uses more resources like registers and flip-flops, which increases power consumption. Here, the CMFIR low-pass filter acts as an interpolator, introducing a sample to boost the image's resolution. CMFIR is a useful tool for addressing the issue of aliasing during sampling. In addition, the genetic algorithm was used to increase the filter's resource utilization and power consumption efficiency.

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Shukla, Manoj Kumar, Ela Chandel, and Parul Goel. "Design of Cascaded-Integrator-Comb Filter for PSK Modem." SSRN Electronic Journal, 2005. http://dx.doi.org/10.2139/ssrn.1955820.

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Kar, Foo Chong, K. Gopalakrishnan Pradeep, and Hui Teo T. "Low Power Approach for Decimation Filter Hardware Realization." June 26, 2008. https://doi.org/10.5281/zenodo.1084984.

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There are multiple ways to implement a decimator filter. This paper addresses usage of CIC (cascaded-integrator-comb) filter and HB (half band) filter as the decimator filter to reduce the frequency sample rate by factor of 64 and detail of the implementation step to realize this design in hardware. Low power design approach for CIC filter and half band filter will be discussed. The filter design is implemented through MATLAB system modeling, ASIC (application specific integrated circuit) design flow and verified using a FPGA (field programmable gate array) board and MATLAB analysis.

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Kumaaran, Siva, and Lee Lini. "LOW POWER CIC FILTER DESIGN FOR DELTA SIGMA ADC." e-Academia Journal 7, SI-TeMIC18 (2019). http://dx.doi.org/10.24191/e-aj.v7isi-temic18.5487.

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This paper presents the power-optimized third-order Cascaded Integrator Comb (CIC) Filter for the DeltaSigma (Δ-∑) Analog-to-Digital Converter (ADC). The CIC Filter refers to a type of decimation filter used in ADC to remove quantization error caused by the modulator. It also occupies less area, when compared to other decimation filter, due to the absence of multiplier. In Δ-∑ ADC, the power consumption is mainly driven by the decimation filter. Hence, careful optimization of the decimation filter is necessary to design an ADC with low power. In this paper, the True Single Phase Clocked (TSPC) D-Flip Flop, which is made up of split-output latches, was applied as the register, instead of conventional D-Flip Flops. The proposed design displayed a significant reduction in power consumption. The proposed architecture was realized by using the CMOS 0.13µm technology. At 256kHz of sampling rate, the CIC Filter only consumed 47.99µW power. The supply voltage used at 1.5V and 13-bit of resolution had been achieved by using 32 oversampling ratio. The layout for 1-bit third-order CIC Filter was also realized with the size of 105.580 × 29.930µm2 . Keywords: Δ-∑ Analog to Digital Converter, Decimation Filter, Cascaded Integrator Comb, Integrator, Differentiator

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Babu, E. Vijaya, Sri Rama Yerra, K. V. Balarama krishna, Sanjana Mohite, Prodduturi Siri Chandana, and Amgoth Bhoomika. "VLSI Design and Implementation of CIC (Cascaded Integrator Comb) Filter." Telecommunications and Radio Engineering, 2025. https://doi.org/10.1615/telecomradeng.2025056312.

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