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1
Wang, Qiong. "Design of Extreme Efficiency Active Rectifier for More-electric Aircrafts." Thesis, Virginia Tech, 2015. http://hdl.handle.net/10919/78147.
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The More-electric aircraft (MEA) concept has been raised since 1990s in order to increase fuel economy and reduce environmental impact of aircrafts. The fundamental of the concept is to replace pneumatic, hydraulic and mechanical systems in conventional aircrafts with its electrical equivalent that is lighter and more reliable. In this movement, power electronics technology plays a key role in interfacing the new types of electrical loads to the new aircraft electrical power system. One of the major tasks for power electronics circuits in MEA is to transfer aircraft variable frequency AC voltage into DC voltage, which could be conveniently utilized by different types of loads or power buses. The converters carrying out the task is commonly known as "rectifiers". This work aims at designing and constructing rectifiers that can work efficiently and reliably in more-electric aircrafts.
One of the major challenge for these rectifiers comes from the complex aircraft environment. The ambient temperature could be as high as 70 ºC. Moreover, active cooling for converters may not be desirable. To deal with this, rectifiers should achieve extreme efficiency (especially at full load) so that all the components are not overheated without active cooling. This work aims at achieving extreme converter efficiency through advanced converter topologies and design. Both single-phase and three-phase rectifiers are discussed in this work.
For single-phase rectifiers, this work focused on boost-type power factor correction (PFC) converters due to the promising efficiency and good PFC characteristics. The well-known two-level semi-bridgeless PFC boost rectifier, together with its interleaved and three-level counterparts, are studied and compared in this work. The operation principles of the converters are analyzed. Models and methods for converter efficiency evaluation are discussed. The efficiency evaluation of the topologies shows the advantage of three-level topologies and interleaved topologies in achieving higher efficiency and better thermal management.
For three-phase rectifiers, two-level boost rectifier, three-level neutral point clamped (NPC) rectifier and Vienna rectifier are investigated. The evaluation shows the advantage of Vienna rectifier in achieving high efficiency due to reduced switching loss.
Based on the evaluation of single-phase and three-phase active rectifiers, the author selected interleaved Vienna rectifier to achieve extreme efficiency and avoid overheating problem. The operation principle of the interleaved Vienna rectifier is introduced, with particular attention paid to the circulating current generated by interleaving operation. The design procedure for achieving maximum efficiency is described. Finally, a prototype of the proposed converter is constructed, which achieves 99.26% efficiency at nominal load.<br>Master of Science
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Mohd, Mukhtar Nurhakimah. "Efficiency Improvement Techniques for Isolated Flyback and Forward Bidirectional DC-DC Converters." Thesis, University of Sydney, 2020. https://hdl.handle.net/2123/23127.
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The information age introduced myriad means for individuals and organisations to stay connected and feel informed. Among those means, email arose as one of the most successful and ubiquitous communication technologies to be enabled via internet access. Today it continues to grow in both the volume of traffic and users each year. We now know that this has resulted in an overabundance of information, which is proving difficult for people to mentally process and productively manage. This is known as “Information overload” and email’s part in this has been termed “email overload”. Among this surplus of communication, important time-related information (temporal information) can easily become buried. This makes information recognition and retrieval an issue and it can cause late appointments, incomplete tasks and missed deadlines, the result of which is increasing stress and cognitive burden. Email applications and related technologies struggle to provide their users with adequate means for identifying and managing temporal information, which arrives embedded within email messages. Despite the sequential nature of time and task obligations received in email messages, email applications offer little to no native support for organising temporal information. It is assumed that users will utilise calendar and task-list applications to manage their time instead. In this research we conducted seven mixed method studies ranging from interviews through to A/B testing to understand the obstacles and opportunities that exist in facilitating temporal information management in email. Among our findings, we observed that the reliance on calendaring was creating distraction, dissuasion and a flawed mental representation of time. We combined our initial results with our background readings to devise solutions to these problems. We tested these solutions by creating a series of increasing-fidelity prototypes that were evaluated by users. The results informed the recommendations we arrived at for improving temporal information awareness and management in email and similar technologies. As a result of conducting a prolonged research project utilising the Research Through Design (RTD) framework, we also contribute a synthesised model of the Design process that articulates lateral thinking by Designers. Finally we contribute a functional prototype that demonstrates the phenomenological advantage in applied research methodologies. In doing so we contribute further knowledge and offer practical recommendations for the Design of temporal information in User Interfaces. We also further discourse on the diverse mental faculties employed during an iterative Design process and the value of prototypes as a conduit for Design knowledge generation.
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Wang, Xiangcheng. "HIGH SLEW RATE HIGH-EFFICIENCY DC-DC CONVERTER." Doctoral diss., University of Central Florida, 2006. http://digital.library.ucf.edu/cdm/ref/collection/ETD/id/3196.
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Active transient voltage compensator (ATVC) has been proposed to improve VR transient response at high slew rate load, which engages in transient periods operating in MHZ to inject high slew rate current in step up load and recovers energy in step down load. Main VR operates in low switching frequency mainly providing DC current. Parallel ATVC has largely reduced conduction and switching losses. Parallel ATVC also reduces the number of VR bulk capacitors. Combined linear and adaptive nonlinear control has been proposed to reduce delay times in the actual controller, which injects one nonlinear signal in transient periods and simplifies the linear controller design. Switching mode current compensator with nonlinear control in secondary side is proposed to eliminate the effect of opotocoupler, which reduces response times and simplifies the linear controller design in isolated DC-DC converters. A novel control method has been carried out in two-stage isolated DC-DC converter to simplify the control scheme and improve the transient response, allowing for high duty cycle operation and large step-down voltage ratio with high efficiency. A balancing winding network composed of small power rating components is used to mitigate the double pole-zero effect in complementary-controlled isolated DC-DC converter, which simplifies the linear control design and improves the transient response without delay time. A parallel post regulator (PPR) is proposed for wide range input isolated DC-DC converter with secondary side control, which provides small part of output power and most of them are handled by unregulated rectifier with high efficiency. PPR is easy to achieve ZVS in primary side both in wide range input and full load range due to 0.5 duty cycle. PPR has reduced conduction loss and reduced voltage rating in the secondary side due to high turn ratio transformer, resulting in up to 8 percent efficiency improvement in the prototype compared to conventional methods.<br>Ph.D.<br>School of Electrical Engineering and Computer Science<br>Engineering and Computer Science<br>Electrical Engineering
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Mushenya, John. "Energy efficiency analysis of converter-fed induction motors." Master's thesis, University of Cape Town, 2018. http://hdl.handle.net/11427/29301.
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Electric motor systems are the largest consumers of industrial electrical energy. As Variable Speed Drives continue to dominate various industrial processes, there is need for stakeholders to fully understand and quantify the converter-fed motor losses over a wide range of operating conditions. Such knowledge is crucial for both manufacturers and end-users in performing energy-efficiency optimizations for motor-drive applications. Although there is an increase in legislative activities, particularly in Europe, toward classification and improvement of energy efficiency of electric motor-drive systems, the available standards for quantifying the various losses are still in their early stages of development. None of these standards have yet passed through all the required phases for them to be considered full international standards, owing to a lack of consensus on many technical issues. Therefore, the need for researchers to provide feedback to the relevant standards committees cannot be over-emphasized. One of the most challenging issues in estimating the efficiency of converter-fed motors is the accurate determination of additional harmonic losses due to the PWM voltages and currents. Although the recently introduced IEC 60034-2-3 Technical Specification has proposed a method of determining these losses through experimental testing, the approach is still undergoing validation. Moreover, it only considers the rated motor frequency and voltage whereas induction motor drives are usually operated over a wide range of speed and torque. The main emphasis of the work presented in this dissertation was to develop a thorough understanding of various converter-fed induction motor losses, and hence efficiency, when fed from a 2-level Voltage Source Inverter. In particular, the dissertation provides a healthy questioning of some concepts in the proposed IEC method, with a view to providing useful feedback for improving the standard. Comparisons are also drawn between the related standards to identify areas for improvement. This study further attempts to explain some conflicting reports cited in literature regarding the nature of additional harmonic losses. The experimental results obtained by testing three induction motors demonstrate some of the technical issues associated with the determination of additional harmonic losses. To mitigate the adverse effect of varying technical skill and competence levels on efficiency test results, an automated testing procedure was developed and implemented on the 110kW test rig in the UCT Machines Lab. The test rig, which boasts of a Genesis 7i high-speed Data Acquisition System, also provides an energy-efficient platform for investigating the steadystate and dynamic characteristics of converter-fed motors. By utilizing the capability of the Data Acquisition System to segregate the fundamental and harmonic components of measured input electrical power, it was found that a PWM power supply can be used in place of a conventional Variac to estimate the sinusoidal supply efficiency of an induction motor. This is a welcome development for both laboratory and field efficiency testing applications.
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Tolstoy, Georg. "High-Efficiency SiC Power Conversion : Base Drivers for Bipolar Junction Transistors and Performance Impacts on Series-Resonant Converters." Doctoral thesis, KTH, Elektrisk energiomvandling, 2015. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-168163.
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This thesis aims to bring an understanding to the silicon carbide (SiC) bipolar junction transistor (BJT). SiC power devices are superior to the silicon IGBT in several ways. They are for instance, able to operate with higher efficiency, at higher frequencies, and at higher junction temperatures. From a system point of view the SiC power device could decrease the cost and complexity of cooling, reduce the size and weight of the system, and enable the system to endure harsher environments. The three main SiC power device designs are discussed with a focus on the BJT. The SiC BJT is compared to the SiC junction field-effect transistor (JFET) and the metal-oxide semiconductor field-effect transistor (MOSFET). The potential of employing SiC power devices in applications, ranging from induction heating to high-voltage direct current (HVDC), is presented. The theory behind the state-of-the-art dual-source (2SRC) base driver that was presented by Rabkowski et al. a few years ago is described. This concept of proportional base drivers is introduced with a focus on the discretized proportional base drivers (DPBD). By implementing the DPBD concept and building a prototype it is shown that the steady-state consumption of the base driver can be reduced considerably. The aspects of the reverse conduction of the SiC BJT are presented. It is shown to be of importance to consider the reduced voltage drop over the base-emitter junction. Last the impact of SiC unipolar and bipolar devices in series-resonant (SLR) converters is presented. Two full-bridges are designed and constructed, one with SiC MOSFETs utilizing the body diode for reverse conduction during the dead-time, and the second with SiC BJTs with anti-parallel SiC Schottky diodes. It is found that the SiC power devices, with their absence of tail current, are ideal devices to fully utilize the soft-switching properties that the SLR converters offer. The SiC MOSFET benefits from its possibility to utilize reverse conduction with a low voltage drop. It is also found that the size of capacitance of the snubbers can be reduced compare to state-of-the-art silicon technology. High switching frequencies of 200 kHz are possible while still keeping the losses low. A dead-time control strategy for each device is presented. The dual control (DuC) algorithm is tested with the SiC devices and compared to frequency modulation (FM). The analytical investigations presented in this thesis are confirmed by experimental results on several laboratory prototype converters.<br><p>QC 20150529</p>
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Trubitsyn, Aleksey. "High efficiency DC/AC power converter for photovoltaic applications." Thesis, Massachusetts Institute of Technology, 2010. http://hdl.handle.net/1721.1/60190.
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Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2010.<br>Includes bibliographical references (p. 217-218).<br>This thesis presents the development of a microinverter for single-phase photovoltaic applications that is suitable for conversion from low-voltage (25-40V) DC to high voltage AC (e.g. 240VAC,RMS). The circuit topology is based on a full-bridge series resonant inverter, a high-frequency transformer, and a novel half-wave cyclo-converter. The operational characteristics are analyzed, and a multidimensional control technique is utilized to achieve high efficiency, encompassing frequency control and inverter and cyclo-converter phase shift control. An experimental prototype is demonstrated in DC/DC conversion mode for a wide range of output voltages. The proposed control strategy is shown to allow for accurate power delivery with minimal steps taken towards correction. The prototype achieves a CEC averaged efficiency of approximately 95.1%. Guidelines for optimization are presented along with experimental results which validate the method.<br>by Aleksey Trubitsyn.<br>S.M.
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ABDELHAMID, ESLAM. "Innovative Digital dc-dc Architectures for High-Frequency High-Efficiency Applications." Doctoral thesis, Università degli studi di Padova, 2018. http://hdl.handle.net/11577/3427310.
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The new generation of automotive controllers requires a space-constrained and high-efficiency step-down architecture. Hence, recently a potential alternative for the conventional step-down topologies is highly demanded. The new architecture should meet the high power density, high efficiency, wide operating ranges, high EMI capabilities, and low-cost requirements. This thesis, developed at the University of Padova and sponsored by Infineon Technologies, aims at investigating potential candidate topologies for automotive step-down conversion capable of eliminating or offsetting some of the common shortcomings of conventional solutions currently in use. Many research effort is paid for the soft switching quasi-resonant topologies in order to miniaturize the passive components through the switching frequency increase. However, the variable switching frequency, increased components count, and narrow operating ranges prevent the wide adoption of the quasi-resonant topologies in the target application. The first objective of this project is to investigate the quasi-resonant buck converter topology in order to stand on the limitations and operating conditions boundaries of such topology. The digital efficiency optimization technique, which is developed in this work, extends the operating ranges in addition to reduce operating frequency variations. On the other hand, the multilevel hybrid topologies are potentially able to meet the aforementioned requirements. By multiplying ripple frequency and fractioning voltage across the switching node the multilevel topologies have the direct advantage of reduced passive components. Moreover, multilevel topologies have many other attractive features include reduced MOSFET voltage rating, fast transient response, a Buck-like wide range voltage conversion ratio, and improved efficiency. These features candidate the multilevel topologies, in particular, the three-level flying-capacitor converter, as an innovative alternative for the conventional topologies for the target application. Accordingly, the three-level flying-capacitor converter (3LFC) is investigated as a second objective for this project. Flying-capacitor (FC) voltage balancing in such topology is quite challenging. The 3LFC under valley current mode control shows an interesting performance, where the FC voltage is self-balanced. In this work, the stability of the converter under valley and peak current mode control is studied and a simplified stability criterion is proposed. The proposed criterion address both current loop static stability and FC voltage stability. The valley current mode modulator results to be inherently stable as soon as the current static instability is compensated with an external ramp. On contrary, the FC voltage in peak current mode control (P-CMC) will never be balanced unless the converter operated with relatively high static peak-to-peak inductor current ripple. Since P-CMC has an inherent over-current protection feature, P-CMC based architectures are widely used in the industrial applications. However, in practice the peak current controlled three-level converter is inherently unstable. Consequently, the instability of the P-CMC 3LFC is addressed. A sensorless stabilizing approach, with two implementation methodologies, is developed in this work. The proposed technique eliminates the instability associated with the FC voltage runaway, in addition to FC voltage self-balancing. Moreover, the proposed methodology offers reduced size, less complexity, and input voltage independent operation. Besides, the proposed approach can be extended to system with a higher number of voltage levels with minimal hardware complexity. The proposed techniques and methodologies in this work are validated using simulation models and experimentally. Finally, in the conclusions the results of the Ph.D. activity are summarized and recommendations for the further development are outlined.
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Wan, Hongmei. "High Efficiency DC-DC Converter for EV Battery Charger Using Hybrid Resonant and PWM Technique." Thesis, Virginia Tech, 2012. http://hdl.handle.net/10919/32343.
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The battery charger plays an important role in the development of electric vehicles (EVs) and plug-in hybrid electric vehicles (PHEVs).This thesis focuses on the DC-DC converter for high voltage battery charger and is divided into four chapters. The background related to EV battery charger is introduced, and the topologies of isolated DC-DC converter possibly applied in battery charge are sketched in Chapter 1. Since the EV battery charger is high voltage high power, the phase-shifted full bridge and LLC converters, which are popularly used in high power applications, are discussed in detail in Chapter 2. They are generally considered as high efficiency, high power density and high reliability, but their prominent features are also limited in certain range of operation. To make full use of the advantages and to avoid the limitation of the phase-shifted full bridge and LLC converters, a novel hybrid resonant and PWM converter combining resonant LLC half-bridge and phase shifted full-bridge topology is proposed and is described in Chapter 3. The converter achieves high efficiency and true soft switching for the entire operation range, which is very important for high voltage EV battery charger application. A 3.4 kW hardware prototype has been designed, implemented and tested to verify that the proposed hybrid converter truly avoids the disadvantages of LLC and phase-shifted full bridge converters while maintaining their advantages. In this proposed hybrid converter, the utilization efficiency of the auxiliary transformer is not that ideal. When the duty cycle is large, LLC converter charges one of the capacitors but the energy stored in the capacitor has no chance to be transferred to the output, resulting in the low utilization efficiency of the auxiliary transformer. To utilize the auxiliary transformer fully while keeping all the prominent features of the previous hybrid converter in Chapter 3, an improved hybrid resonant and PWM converter is proposed in Chapter 4. The idea has been verified with simulations. The last chapter is the conclusion which summaries the key features and findings of the two proposed hybrid converters.<br>Master of Science
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Inam, Wardah. "High efficiency resonant dc/dc converter for solar power applications." Thesis, Massachusetts Institute of Technology, 2013. http://hdl.handle.net/1721.1/79153.
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Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2013.<br>This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.<br>Cataloged from student-submitted PDF version of thesis.<br>Includes bibliographical references (p. 109).<br>This thesis presents a new topology for a high efficiency dc/dc resonant power converter that utilizes a resistance compression network to provide simultaneous zero voltage switching and near zero current switching across a wide range of input voltage, output voltage and power level. The resistance compression network maintains desired current waveforms over a wide range of voltage operating conditions. The use of on/off control in conjunction with narrowband frequency control enables high efficiency to be maintained across a wide range of power levels. The converter implementation provides galvanic isolation and enables large (greater than 1:10) voltage conversion ratios, making the system suitable for large step-up conversion in applications such as distributed photovoltaic converters. Three 200 W prototypes were designed, built and tested. The first prototype was made as a proof of concept and operated at a switching frequency of 100 kHz. It had an efficiency of 93.5% (at 25 V input and 400 V output). The second prototype was operated at a switching frequency of 500 kHz and had an efficiency of 93% (at 25 V input and 400 V output). The high frequency losses caused by the ringing in voltage and current due to the resonating parasitics of the transformer were removed with the help of a matching network in the third prototype. This final prototype operated at a switching frequency of 500 kHz and showed that over 95% efficiency is maintained across an input voltage range of 25 V - 40 V (at 400 V output) and over 93.7 % efficiency across a wide output voltage range of 250 V - 400 V (at 25 V input). These experimental results demonstrated the effectiveness of the proposed design.<br>by Wardah Inam.<br>S.M.
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Zhao, Xiaonan. "A High-efficiency Isolated Hybrid Series Resonant Microconverter for Photovoltaic Applications." Thesis, Virginia Tech, 2016. http://hdl.handle.net/10919/78312.
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Solar energy as one type of the renewable energy becomes more and more popular which has led to increase the photovoltaic (PV) installations recently. One of the PV installations is the power conditioning system which is to convert the maximum available power output of the PV modules to the utility grid. Single-phase microinverters are commonly used to integrate the power to utility grid in modular power conditioning system. In the two-stage microinverter, each PV module is connected with a power converter which can transfer higher output power due to the tracking maximum power point (MPP) capability. However, it also has the disadvantages of lower power conversion efficiency due to the increased number of power electronics converters. The primary objective of this thesis is to develop a high-efficiency microconverter to increase the output power capability of the modular power conditioning systems.
A topology with hybrid modes of operation are proposed to achieve wide-input regulation while achieving high efficiency. Two operating modes are introduced in details. Under high-input conditions, the converter acts like a buck converter, whereas the converter behaves as a boost converter under low-input conditions. The converter operates as the series resonant converter with normal-input voltage to achieve the highest efficiency. With this topology, the converter can achieve zero-voltage switching (ZVS) and/or zero-current switching (ZCS) of the primary side MOSFETs, ZCS and/or ZVS of the secondary side MOSFETs and ZCS of output diodes under all operational conditions. The experimental results based on a 300 W prototype are given with 98.1% of peak power stage efficiency and 97.6% of weighted California Energy Commission (CEC) efficiency including all auxiliary and control power under the normal-input voltage condition.<br>Master of Science
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Manh, Vir Varinder. "An Integrated High Efficiency DC-DC Converter in 65 nm CMOS." Thesis, Linköpings universitet, Elektroniksystem, 2010. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-61237.
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This thesis work describes the implementation perspective of an integrated high efficiency DC-DC converter implemented in 65 nm CMOS. The implemented system employs the Buck converter topology to down-convert the input battery voltages. This converter offers its use as a power management unit in portable battery operated devices. This thesis work includes the description of a basic Buck converter along with the various key equations involved which describe the Buck operation as well as are used to deduce the requirements for the various internal building blocks of the system. A detailed description of the operation as well as the design of each of the building blocks is included. The implemented system can convert the input battery voltage in the range of 2.3 V to 3.6 V into an output supply voltage of 1.6 V. The system uses dual-mode feedback control to maintain the output voltage at 1.6 V. For the low load currents the PFM feedback control is used and for the higher load currents the PWM feedback control is used. This converter can supply load currents from 0 to 300 mA with efficiency above 85%. The static line regulation of the system is < 0.1% and the load regulation of the system is < 0.3%. A digital soft-start circuit is implemented in this system. The system also includes the capability to trim the output voltage in ~14 mV steps depending on the 4-bit input digital code.
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Liu, Ya. "High Efficiency Optimization of LLC Resonant Converter for Wide Load Range." Thesis, Virginia Tech, 2007. http://hdl.handle.net/10919/30990.
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As information technology advances, so does the demand for power management of telecom and computing equipment. High efficiency and high power density are still the key technology drivers for power management for these applications. In order to save energy, in 2005, the U.S. Environmental Protection Agency (EPA) announced the first draft of its proposed revision to its ENERGY STAR specification for computers. The draft specification separately addresses efficiency requirements for laptop, desktop, workstation and server computers. The draft specification also proposes a minimum power supply efficiency of 80% for PCs and 75% to 83% for desktop derived servers, depending on loading condition and server type. Furthermore, recently some industry companies came out with a much higher efficiency target for the whole AC/DC front-end converter over a wide load range.
Distributed power systems are widely adopted in the telecom and computing applications for the reason of high performance and high reliability. As one of the key building blocks in distributed power systems, DC/DC converters in the front-end converter are also under the pressure of increasing efficiency and power density. Due to the hold-up time requirement, PWM DC/DC converters cannot achieve high efficiency for well known reasons when they are designed for wide input voltage range.
As a promising topology for this application, LLC resonant converters can achieve both high efficiency and wide input voltage range capability because of its voltage gain characteristics and small switching loss. However, the efficiency of LLC resonant converter with diode rectifier still cannot meet the recent efficiency target from industry. In order to further improve efficiency of LLC resonant converters, synchronous rectification must be used. The complete solution of synchronous rectification of LLC resonant converters is discussed in this thesis. The driving of the synchronous rectifier can be realized by sensing the voltage Vds of the SR. The turn-on of the SR can be triggered by the body-diode conduction of the SR. With the Vds compensation network, the precise voltage drop on Rds_on can be achieved, thus the SR can be turned off at the right time. Moreover, efficiency optimization at normal operation over wide load range is discussed. It is revealed that power loss at normal operation is solely determined by the magnetizing inductance while the magnetizing inductor is designed according to dead-time td selection. The mathematic equations for the relationship between power loss and dead-time are developed. For the first time, the relationship between power loss and dead-time is used as a tool for efficiency optimization. With this tool, the efficiency optimization of the LLC resonant converter can be made according to efficiency requirement over a wide load range. With the expectation to achieve high efficiency at ultra-light load, the green mode operation of LLC resonant converters is addressed. The rationale of the issue with the conventional control algorithm is revealed and a preliminary solution is proposed.<br>Master of Science
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Gu, Bin. "Power Converter and Control Design for High-Efficiency Electrolyte-Free Microinverters." Diss., Virginia Tech, 2014. http://hdl.handle.net/10919/25236.
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Microinverter has become a new trend for photovoltaic (PV) grid-tie systems due to its advantages which include greater energy harvest, simplified system installation, enhanced safety, and flexible expansion. Since an individual microinverter system is typically attached to the back of a PV module, it is desirable that it has a long lifespan that can match PV modules, which routinely warrant 25 years of operation. In order to increase the life expectancy and improve the long-term reliability, electrolytic capacitors must be avoided in microinverters because they have been identified as an unreliable component. One solution to avoid electrolytic capacitors in microinverters is using a two-stage architecture, where the high voltage direct current (DC) bus can work as a double line ripple buffer.
For two-stage electrolyte-free microinverters, a high boost ratio dc-dc converter is required to increase the low PV module voltage to a high DC bus voltage required to run the inverter at the second stage. New high boost ratio dc-dc converter topologies using the hybrid transformer concept are presented in this dissertation. The proposed converters have improved magnetic and device utilization. Combine these features with the converter's reduced switching losses which results in a low cost, simple structure system with high efficiency. Using the California Energy Commission (CEC) efficiency standards a 250 W prototype was tested achieving an overall system efficiency of 97.3%.
The power inversion stage of electrolyte-free microinverters requires a high efficiency grid-tie inverter. A transformerless inverter topology with low electro-magnetic interference (EMI) and leakage current is presented. It has the ability to use modern superjunction MOSFETs in conjunction with zero-reverse-recovery silicon carbide (SiC) diodes to achieve ultrahigh efficiency. The performance of the topology was experimentally verified with a tested CEC efficiency of 98.6%.
Due to the relatively low energy density of film capacitors compared to electrolytic counterparts, less capacitance is used on the DC bus in order to lower the cost and reduce the volume of electrolyte-free microinverters. The reduced capacitance leads to high double line ripple voltage oscillation on DC bus. If the double line oscillation propagates back into the PV module, the maximum power point tracking (MPPT) performance would be compromised. A control method which prevents the double line oscillation from going to the PV modules, thus improving the MPPT performance was proposed.
Finally, a control technique using a single microcontroller with low sampling frequency was presented to effectively eliminate electrolyte capacitors in two-stage microinverters without any added penalties. The effectiveness of this control technique was validated both by simulation and experimental results.<br>Ph. D.
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Mirabella, Michele. "Digitally Adjustable Step Up Converter." Master's thesis, Alma Mater Studiorum - Università di Bologna, 2021.
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DC-DC converters are electronic devices used to change DC electrical power efficiently from one voltage level to another. Complex systems like an industrial printer require accurate high
voltage levels to let the print head nozzles spit out the ink in the proper way, according to the pattern to be printed.
Creadigit, product of System S.p.a, is a high precision printing system used in decorations for ceramic products. It is actually powered by a couple of rack mounted AC-DC converters, which
offer simple powering solution at low cost.
Nevertheless, the total system efficiency can be sensibly increased with the introduction of a DC-DC Step UP converter in place of the AC-DC supply.
This thesis is focused on the analysis, modeling, design and implementation of a Boost converter for such application. One project goal is to provide the converter the ability to digitally adjust the output voltage according to the requirements of each printing head, thus leading to a consistent power saving of the entire system.
The work structure is so arranged: first of all, it is explained the architecture of the printing system and the inkjet printing mechanism so as to understand why high voltage supplies are required.
Secondly, the power amplifier system is analyzed through simulation in LTSpice environment. During these simulations, there will be an analysis of potential power savings introduced by the adoption of the adjustable DC-DC converter.
It follows the Boost converter theory, necessary to understand the operation of the key element of this project. Moreover, a detailed study of the complex world of capacitors is developed. In fact, the output capacitor selection is one of the trickiest part in the design of a switching DC-DC converter.
In this thesis, a short theoretical study about EMC in SMPS converters is accompanied by simulations that could anticipate the results of in-field studies. In the end, some results of a first DC-DC converter prototype will be presented.
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Qin, Yaxiao. "High Efficiency SEPIC Converter For High Brightness Light Emitting Diodes (LEDs) System." Thesis, Virginia Tech, 2012. http://hdl.handle.net/10919/44422.
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This thesis presents an investigation into the characteristics of and driving methods for light emitting diode (LED) lamp system. A comprehensive overview on the lighting development is proposed. The characteristic of the light emitting diode (LED) lamp is described and the requirements of the ballast for the light emitting diode (LED) lamp are presented.
Although LED lamps have longer lifetime than fluorescent lamps, the short lifetime limitation of LED driver imposed by electrolytic capacitor has to be resolved. Therefore, an LED driver without electrolytic capacitor in the whole power conversion process is preferred. In this thesis, a single phase, power factor correction converter without electrolytic capacitors for LED lighting applications is proposed, which is a modified SEPIC converter working in discontinuous conduction mode (DCM). Different with a conventional SEPIC converter, the middle capacitor is replaced with a valley-fill circuit. The valley-fill circuit could reduce the voltage stress of output diode and middle capacitor under the same power factor condition, thus achieving higher efficiency. Instead of using an electrolytic capacitor for the filter, a polyester capacitor of better lifetime expectancy is used.
An interleaved power factor correction SEPIC with valley fill circuit is proposed to further increase the efficiency and to reduce the input and output filter size and cost. The interleaved converter shows the features such as ripple cancellation, good thermal distribution and scalability.<br>Master of Science
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Chaour, Issam, Ahmed Fakhfakh, and Olfa Kanoun. "Enhanced Passive RF-DC Converter Circuit Efficiency for Low RF Energy Harvesting." Universitätsbibliothek Chemnitz, 2017. http://nbn-resolving.de/urn:nbn:de:bsz:ch1-qucosa-224264.
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For radio frequency energy transmission, the conversion efficiency of the receiver is decisive not only for reducing sending power, but also for enabling energy transmission over long and variable distances. In this contribution, we present a passive RF-DC converter for energy harvesting at ultra-low input power at 868 MHz. The novel converter consists of a reactive matching circuit and a combined voltage multiplier and rectifier. The stored energy in the input inductor and capacitance, during the negative wave, is conveyed to the output capacitance during the positive one. Although Dickson and Villard topologies have principally comparable efficiency for multi-stage voltage multipliers, the Dickson topology reaches a better efficiency within the novel ultra-low input power converter concept. At the output stage, a low-pass filter is introduced to reduce ripple at high frequencies in order to realize a stable DC signal. The proposed rectifier enables harvesting energy at even a low input power from −40 dBm for a resistive load of 50 kΩ. It realizes a significant improvement in comparison with state of the art solutions
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Yao, Yanmei. "Study of Induction Machines with Rotating Power Electronic Converter." Doctoral thesis, KTH, Elkraftteknik, 2016. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-196054.
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This thesis investigates a novel induction machine topology that uses a rotating power electronic converter. Steady-state and dynamic performance of the topology is studied to understand its operational principle. Furthermore the potential of improving its efficiency and power factor is investigated. The topology is referred to as wound rotor induction machine with rotating power electronic converter (WRIM-RPEC). The WRIM-RPEC topology offers the possibility to magnetize the induction machine from the rotor side by introducing a reactive voltage in the rotor. Thus, the power factor of the machine can be improved. Constant speed variable load operation can be achieved by setting the frequency of the introduced voltage. Two options of rotor winding and converter configuration in the WRIM-RPEC system are investigated. The wound rotor windings can either be open-ended and fed by a three-phase back-to-back converter or Y-connected and fed by a single three-phase converter. The dc-link in both converter configurations contains only a floating capacitor. These two configurations give different dc-link voltages at the same torque and speed. Two analytical steady-state models of the topology are developed in this thesis. The first model can be used to analyze the operating condition of the motor at specific speed and torque. Particularly, the operating range of speed and torque of the topology is investigated. The second model is used to analyze variable power factor operation, including unity power factor operation. Analytical calculations and measurements are carried out on a 4-pole, 1.8kW induction machine and the results are compared. A dynamic mathematic model is then developed for the WRIM-RPEC system for the back-to-back converter configuration. The mathematic model is then applied in Matlab/Simulink to study the dynamic performance of the system including starting, loading and phase-shifting. The simulation results are compared with measurements on the 4-pole, 1.8kW induction machine. Moreover, the simulation model using the existing Simulink blocks are studied to compare with the results obtained from the mathematic model. Furthermore, the dynamic performance of the WRIM-RPEC system with the single converter configuration is investigated. In addition, harmonic spectra analysis is conducted for the stator and rotor currents. In the last part of the thesis, efficiency improvement is investigated on the 4-pole induction machine when it is assumed to drive a pump load. It is shown that the efficiency can be further improved by decreasing the rotor resistance. Due to space constraints it is however difficult to decrease the rotor resistance in a 4-pole induction machine. An investigation is thus carried out on a standard 12-pole, 17.5kW squirrel-cage induction machine with inherent low power factor. The cage rotor is redesigned to a wound rotor to enable the connection of converter to the rotor windings. An analytical model is developed to design the wound rotor induction machine. The machine performance from calculations is then compared with FEM simulations with good agreement. The analytical model is further used to design several WRIMs with different dimensions and rotor slot numbers. Power factor and efficiency improvement is then explored for these WRIMs. A promising efficiency increase of 6.8% is shown to be achievable.<br><p>QC 20161111</p>
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Jemibewon, Abayomi Oluwaseyi. "A Smart Implementation of Turbo Decoding for Improved Power Efficiency." Thesis, Virginia Tech, 2000. http://hdl.handle.net/10919/34072.
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<p>Error correction codes are a means of including redundancy in a stream of information bits to allow the detection and correction of symbol errors during transmission. The birth of error correction coding showed that Shannon's channel capacity could be achieved when transmitting information through a noisy channel. Turbo codes are a very powerful form of error correction codes that bring the performance of practical coding even closer to Shannon's theoretical specifications. Bit-error-rate (BER) performance and power dissipation are two important measures of performance used to characterize communication systems. Subject to the law of diminishing returns, as the resolution of the analog-to-digital converter (ADC) in the decoder increases, BER improves, but power dissipation increases. The number of decoding iterations has a similar effect on the BER performance and power dissipation of turbo coded systems. This is significant since turbo decoding is typically practiced in a fixed iterative manner, where all transmitted frames go through the same number of iterations. This is not always necessary since certain "good" frames would converge to their final bits within a few iterations, and other "bad" frames never do converge. </p>
<p>In this thesis, we investigate the technical feasibility of adapting the resolution of the ADC in the decoder, and the number of decoding iterations, in order to obtain the best trade-off possible between BER performance and power dissipation in a communication system. With the aid of computer-aided simulations, this thesis investigates the performance and practical implementation issues associated with incorporating a variable resolution ADC into the decoder structure of turbo codes. The possibility of further power conservation resulting from reduced decoding computation is also investigated with the use of a recently developed iterative stopping criterion.</p><br>Master of Science
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Ahmed, Oday Ali. "Investigation into high efficiency DC-DC converter topologies for a DC microgrid system." Thesis, University of Leicester, 2012. http://hdl.handle.net/2381/10165.
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Distributed generation in the form of DC microgrids has recently attracted increasing research interest. For integrating primary sources and energy storage devices to the DC bus of a DC microgrid power electronic converters are necessary, but the associated losses may degrade the microgrid efficiency. Therefore, the aim of this work is to develop high-efficiency converters, particularly for fuel cell generators and ultracapacitors energy buffers suitable for use in a stationary distribution system. Based on the evaluation of the fuel cell dynamic performance, a current–fed DC–DC converter design with a lower voltage rating of the switching devices and a higher DC voltage conversion ratio is proposed. A number of optimisation approaches have been applied to further improve the converter efficiency over its full power range. The periodic steady state operation of the converter is analysed in detail; state-space averaging is then used to determine the small signal equations and derive transfer functions. A closed loop controller has been designed and verified by a novel PSpice/Simulink/actual processor co–simulation approach, where the modelling results are validated by experimental results using a model–based design method. To sustain the charging and discharging states of the ultracapacitor, a bidirectional DC–DC converter is required. Based on a comprehensive overview on different DC–DC converter topologies, the research presented here has shown that, bidirectional voltage–fed topology is better suited for dealing with the fast dynamic response of the ultracapacitor. But for a wide input voltage variation, this topology exhibits a higher circulating power flow and higher conduction losses as a consequence. Therefore, a detailed analysis of the bidirectional converter exploring the impact of the circulating power flow interval is developed in this study. Analytic methods have been applied to establish the optimal operation of the bidirectional voltage–fed converter for an ultracapacitor to improve its performance and efficiency. Based on these methods, a novel modulation scheme is proposed that minimises the circulating power flow in the converter, that has been verified by detailed simulation.
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Lin, Doris M. Eng Massachusetts Institute of Technology. "An exploratory design of a 65 nm CMOS buck converter for maximum efficiency." Thesis, Massachusetts Institute of Technology, 2008. http://hdl.handle.net/1721.1/46024.
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Includes bibliographical references (p. 75-76).<br>Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2008.<br>Portable battery-operated consumer devices, such as mp3 players, cell phones, and digital cameras, are becoming ever more prevalent and so the need for long battery life is increasingly important. These small devices contain power converters that produce lower supply voltages from the fixed battery voltage source. For long battery life, it is necessary to maximize the efficiency of the power converter. A design is proposed for the topology and control of a 65 nm CMOS DC/DC switch-mode converter converting a 3 V battery supply to a 1.2 V output voltage for a maximum output current of 100 mA. The goal of the project was to maximize converter efficiency and improve on the maximum 40% efficiency of a traditional linear regulator. With the proposed topology and control scheme described in this report, the buck converter operates at a switching frequency of 10 to 75 MHz with a maximum efficiency of 93.63%.<br>by Doris Lin.<br>M.Eng.
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Chi, Hsin-Wei, and 紀信維. "Implementation of High Efficiency DCDC Converter." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/17075473241544416654.
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碩士<br>元智大學<br>電機工程學系<br>92<br>ABSTRACT
The aim of this research is to develop a high efficiency DCDC converter. In the process of designing a DCDC converter,the output efficiency will be enhanced if a suitable circuit structure can be chosen first. In this thesis,the basic operation principle of Half Bridge Centro Tap and Current Double structure is discussed. Next, the consideration of component and circuit design is explained. Finally, a practical Half Bridge Current Double Converter based on the theory of DCDC converter is implemented to prove its accessibility. The study is conducted with four different structures.
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Wu, Chia-Hasn, and 吳佳勳. "High-Efficiency D-Type Resonant Converter." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/px77gq.
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碩士<br>崑山科技大學<br>電機工程研究所<br>102<br>This paper proposed a high efficiency power converter in which the class D resonant converter as the main structure, with a simple circuit structure, small size, light weight, low switching losses, low cost price advantages.The use of resonant slots are composed of inductance and capacitance to produce resonant voltage and current required by zero voltage or zero current switching to achieve soft switching technique to reduce switching loss caused in the switch,to obtain the desired output voltage and output current. The paper also analyzed the operating characteristics for the circuit theory and circuit model, and finally, to implement the results of verification circuit, the circuit conversion efficiency of 93.5%.
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Lee, Chia-Wei, and 李佳蔚. "High-Efficiency Non-Isolated Step-Up Converter." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/y8a6n9.
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碩士<br>國立臺灣科技大學<br>電機工程系<br>99<br>By stacking a non-isolated current-fed push-pull converter with a novel voltage doubler rectifier technique, a non-isolated step-up converter is proposed in this thesis. In addition to inheriting the advantages of the current-fed push-pull converter, the proposed converter has several features, for instance, low voltage stress on the semiconductor and the recovery of the leakage energy. Consequently, low voltage rating MOSFET can be used resulting in achieving high conversion efficiency. Moreover, high power density is also achieved because the capacitance as well as the number of the output filter capacitor is significantly reduced.
To demonstrate the feasibility of the proposed converter, the operation principles as well as the experimental results with 150 kHz, 36-75V input and 380V/500W output are described in this thesis.
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Chu, Yu-Hsien, and 朱育賢. "High-Efficiency Design of LLC Resonant Converter." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/23657062494546645211.
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碩士<br>國立臺灣大學<br>電機工程學研究所<br>96<br>The LLC resonant converter has the merit of fixed duty cycle operation. A combination of parasitic components, which includes the MOSFET output capacitance and the leakage inductance of the isolation transformer, produces a resonant action and reduces drain-source voltage prior to turn-on. Moreover, the switching loss is reduced relatively.Therefore, high efficiency operation of system is achieved.An experimental prototype of 115~264Vac input, 19V/4.73A output, the resonant converter full load efficient reaches 95.31%.
The subject of this thesis is to analyze and design a LLC resonant converter. The LLC resonant converter allows zero voltage turn-on of switches while retaining the merits of simple circuit designed and low stresses accompanied with variable frequency control. The LLC resonant converter uses parasitic components to resonate. Therefore, additional resonant components are not required. Moreover, the switching stresses are reduced by using of the zero voltage switching (ZVS) resonant technique.
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Huang, Tang-Yu, and 黃堂祐. "A High Efficiency Dual-Mode Buck Converter." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/02993659578494616844.
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碩士<br>國立臺灣海洋大學<br>電機工程學系<br>95<br>Abstract
A high efficiency DC to DC buck converter is designed in this thesis. The high conversion efficiency converter can effectively prolong the portable products using time. The buck converter can switch between different modulation modes according to different load current conditions. With this arrangement, the converter can reach high efficiency under different load conditions.
The converter can switch between pulse width modulation mode and pulse frequency modulation mode for heavy load and light load conditions, respectively. Dead-time control circuit and zero current detector are also used to avoid excess current consumption. A soft start operation is designed to avoid the damage of the transient large current at the start up.
The switching circuit usually has electromagnetic interference problem. In the thesis, a simple and low power consumption modulation circuit is proposed to spread the switching frequencies. This chip is fabricated with TSMC 0.35μm 2P4M 3.3V/5V Mixed Signal CMOS technology.
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Chang, Yung-Chi, and 張詠冀. "Efficiency Improvement of Active Clamp Forward Converter." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/74700965120745504184.
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碩士<br>國立勤益科技大學<br>電子工程系<br>102<br>As the power transfer becomes more and more widely applied, the customers’ demands for the power efficiency, size and reliability becomes higher accordingly; however, the conventional forward diode rectifying converter can hardly meet the demands.
This paper adopts the active clamp structure to combine with auxiliary switches and clamper capacitance, which can effectively restrain the voltage transient and minimize the damages caused by switch changeover, as well as improve the converting efficiency. The capacity elements can operate a wider range of input voltage. In practice, the Pulse Width Modulation controller is used for the research on efficiency improvement of forward converter. From the experimental results, the methods proposed in the study have realized the improvement results.
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Lee, Bo-Yi, and 李柏毅. "High-Efficiency Power Converter for Portable Devices." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/8h4xsf.
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碩士<br>國立虎尾科技大學<br>電機工程系碩士班<br>106<br>A high-precision bandgap reference voltage circuit, a high-efficiency boost converter, and a high-efficiency buck converter for portable devices are presented in this thesis. The high-precision bandgap reference voltage circuit with an innovative v-curve correction technique markedly reduces reference voltage variations under a wide temperature range. The best temperature coefficient of the proposed bandgap reference is 4.06 ppm/°C that has a 76% improvement compared to that of the conventional bandgap reference voltage circuit over a wide temperature range of −40°C to 140 °C.
In addition, a novel discontinuous conduction mode (DCM) control technique and an adaptive peak current control technique are proposed to improve the power conversion efficiency and the output ripple voltage of power converters in this study. The proposed boost converter with a DCM control technique can accurately sense the variations of the inductor current in the released state. When the inductor current is released to zero, the boost converter operates in the DCM mode to eliminate a reverse inductor current and improves power conversion efficiency. The experimental results revealed that the power conversion efficiency is achieved from 90.3% to 95.03% at a load current range of 1 – 50 mA. The proposed buck converter with an adaptive peak current control will generate different peak inductor currents to optimize the stored energy and improves power conversion efficiency when the load current varies in the different applications. The experimental results show that the power conversion efficiency of the proposed buck converter is achieved from 91.04 to 94.62% at a load current range of 1 – 200 mA. Furthermore, the output ripple voltage is improved from 14.9 mV to 5.19 mV at a load current of 1 mA. All circuits were designed and fabricated using a standard TSMC 0.18-μm 1P6M CMOS technology.
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Liang, Chi-Tsung, and 梁繼宗. "Design of the High Efficiency LLC Power Converter." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/pxv2jj.
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碩士<br>崑山科技大學<br>電子工程研究所<br>96<br>This thesis presents an output-current ripple reduction method for LLC resonant converter. Based on soft-switching, high efficiency and low electromagnetic interference, LLC resonant converter has been widely used for high switching frequency power conversion applications. However, the high output ripple current is the main drawback. Besides, for the large output current ripple of LLC resonant converter, the large output capacitance is necessary to reduce output current ripple for the high quality DC output voltage. In order to solve this problem, a current shaping technique is presented in this thesis. By using the resonant tank with a parallel passive network, the output ripple current can be improved. Also, the values of the output capacitance can be reduced. Finally, a 400V input voltage, 24V/8A output prototype of LLC resonant converter has been simulated and implemented. The simulation and experimental results demonstrated the feasibility of proposed method.
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HSU, CHIH-HAO, and 許智豪. "Study on High Efficiency Synchronous Rectifier Buck Converter." Thesis, 2017. http://ndltd.ncl.edu.tw/handle/69gpb5.
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碩士<br>明新科技大學<br>電機工程系碩士在職專班<br>105<br>In recent years, with rapid growth of electronic portable devices, high performance and small size of power converter becomes more and more important. This thesis is focused on the design and implementation of a synchronous rectifier buck converter with current mode control. This synchronous rectifier buck converter has low output ripple and fast transient response when load current is suddenly changed. It also has high conversion efficiency that is suitable for portable electronic applications. Finally, experimental results of different Inductance are discussed.
For VIN=12V/VOUT=3.3V, the line regulation and load regulation are 1.25mV/V and 10mV/A respectively. For VIN=12V/VOUT=5.0V, the line regulation and load regulation are 2.5mV/V and 23mV/A respectively. The conversion efficiency of synchronous rectifier buck converter is up to 94.5%.
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曾國境. "Design of A Novel High Efficiency Power Converter." Thesis, 1999. http://ndltd.ncl.edu.tw/handle/33200596745746631953.
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碩士<br>大葉大學<br>電機工程研究所<br>87<br>In recent years, there is a fast progress in power electronics technology. The main reason is the improvement in electrical components and the development of new magnetic material.
For example, the manganese - zinc ferrite are used in high frequency power transformer and MPP ( Molybdenum Perm-alloy Powder ) are used in the power inductor ( choke ) to reduce core loss; Ceramic material are used in PCB for better heat dissipation. High speed power transistors, such as MOSFET and IGBT ( Insulated Gate Bipolar Transistor ), IEGT ( Injection Enhanced Gate Transistor ) , FRD ( Fast Recovery Diode ) and pulse width modulation IC, all these make high power — high frequency converter possible.
In this paper, the topology and performance of various kinds of power converter are discussed and compared. Improved designs are proposed to increase the efficiency of power conversion, and to reduce the noise interference. Experimental results show the improvement in performance.
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Kun-YenTsai and 蔡坤諺. "High Efficiency Buck Converter with Adaptive Hysteresis Control." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/91372711063930243883.
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碩士<br>國立成功大學<br>電機工程學系<br>102<br>In recent years, the increase use of multimedia portable electronic devices requires high functionality and high efficiency in the power management units. This thesis presents an adaptive hysteresis window control to achieve optimal operating frequency of the buck converter based on load conditions. This control method not only improves the efficiency at light loads but also achieves fast load response during transients. In circuit implementation, this thesis first illustrates how to use the load consumption model to obtain the optimal operating frequency curve. The analog type hysteresis window control circuit is integrated to a buck converter to validate this method.
Simulation results show that this converter operates at optimal frequency range of 350 kHz to 890 kHz in the load range of 0.2A to 2.6A. This converter makes 5V to 1.6V voltage conversion with 96.5% optimal conversion efficiency and outstanding transient response
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Song, Yuan-Siang, and 宋源翔. "High efficiency synchronous rectifier converter LED driver circuit." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/39109232972702359429.
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碩士<br>國立勤益科技大學<br>電子工程系<br>102<br>This thesis is improved LED driver circuitry. Currently, the global mains
voltage range is AC90 ~ 265V which cannot directly for LED use. So we need LED driver circuitry to control LED. Since varies current values can be transformed by LED driver circuitry, investigations and researches are compared to achieve a high power, high current accuracy, high power factor and low-cost LED driver circuitry architecture.
Power converter with flyback converter as the main framework for flyback converter architecture is preferred below 100W converter. Its’ cheap, simple
structure does not need secondary side of the output inductor. For cost and size consideration, these advantages are superior relatively.
In this paper, the use of synchronous rectification flyback converter architecture improves efficiency and reduces unnecessary power consumption.
Use synchronous rectification technology to replace traditional of diode rectifier mode, and take rate field effect transistor low on-resistance characteristics to replace two-pole pressure drop along the body can improve the secondary side
rectification losses. When the output current is inadequate or too low, the use of inductive compensation is proposed to provide a stable LED current to avoid flicker.
Another standby mode is when the load reaches, close the secondary side synchronous rectifier circuit. It can reduce standby consumption.
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Wang, Chen-Yi, and 王偵亦. "Efficiency Model for Power Converter with PWM Jitter." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/47051367823007617559.
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碩士<br>國立臺灣大學<br>電機工程學研究所<br>104<br>The objective of this thesis is to investigate the impact of the PWM Duty Cycle jitter (PWM Jitter) on the power converter as well as to establish its efficiency model. By adopting a strategy based on the proposed efficiency model, designers can avoid the efficiency drop caused by PWM jitter.
In this thesis, the origin of PWM jitter and the efficiency of power converter are presented first. The synchronous buck DC converters are selected for illustration. Next, a methodology by using the state-space averaging method to find out the impact of the PWM jitter on the power conversion efficiency is proposed. Two efficiency models are developed, one for the constant resistance load and the other for the constant current load. Then, the efficiency drops caused by different PWM jitter’s frequency or amplitude are compared. In order to eliminate the measurement inaccuracy caused by the thermal drift, a LabVIEW-based programmable automatic measuring system is established. Finally, the computer simulations and the hardware experiments confirm the accuracy of the proposed efficiency models.
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Hsueh, Te-Chin, and 薛德欽. "High-Efficiency Interleaved Boost Converter with Zero-Voltage Transition." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/77u9y3.
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碩士<br>國立東華大學<br>電機工程學系<br>96<br>This thesis proposes a high-efficiency interleaved boost converter with zero-voltage transition, which is composed of two shunted elementary boost converters and an auxiliary inductor. This converter is able to turn on both the active power switches at zero voltages to reduce their switching losses and evidently raise the conversion efficiency. Since the two parallel-operated elementary boost converters are identical, operation analysis and design for the converter module becomes quite simple. A laboratorial test circuit is built and the circuit operation shows satisfactory agreement to the theoretical analysis. The experimental results show that this converter module performs very well with the output efficiency as high as 95%.
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Su, Che-Yang, and 蘇哲揚. "Efficiency Improvement of LLC Resonant Converter under Light Load." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/7v6g59.
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碩士<br>國立臺北科技大學<br>電機工程系研究所<br>102<br>The objective of this thesis is to design and implement an LLC resonant converter controlled by digital signal processor to give 12V output voltage. Variable switching frequency control is used to regulate the output voltage. The resonant inductor, resonant capacitor cooperate to achieve zero voltage switching and reduce switching losses. In addition, a synchronous rectification technique for LLC resonant converter is used to reduce conduction losses in secondary side and burst mode control is used to reduce the switching loss under light load.
The Texas Instruments digital signal processor (DSP), TMS320F28035, is used as the control core for the verification of design and implementation. The design specifications include input voltage of 400V, output voltage of 12V and total power rating of 300W. Simulation and experimental results show that the maximum efficiency is 94.66% and the efficiency can be increased up to 18% under 2% load by burst mode control. These results confirm the design and implementation.
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Liao, Chien-Erh, and 廖建貳. "A Switching Buck Converter with Improved Light-load Efficiency." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/dah89q.
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碩士<br>國立中正大學<br>電機工程研究所<br>104<br>In this thesis, existing MPET(Maximum Power Efficiency Tracking Technique) to improve power conversion efficiency in CCU LPIC lab. is investigated to design power efficiency tracking fuction for wide load operative range and high light-load efficiency. There are two major directions to improve power conversion efficiency for existing technology of buck converter in CCU LPIC lab, SOM(Switch-On-Demand Modulator), and MPET. The former focuses on improving medium or light-load efficiency, and the latter focuses on light or ultra light-load status. In the first edition MPET which based on SOM , it was concerned when is the appropriate time to shut down the circuit block which without work. The method depends on counting the numbers of CLK which had been masked. It is unsuitable that it will change as the whole circuit system change, and it’s hard to start the mechanical cut-off at the appropriate time. In this condition, it will cause the power consumption to diminish its efficiency.
Regarding the above discussion, this thesis proposes the second edition MPET which is called Real-Time Maximum Power Efficiency Tracking Technique. It can track power efficiency for wide load operative range on accuracy time. It can not only find the right time to shut down circuit, but also suit with circuits made of different designers. The technique solves the flaw that is the first edition MPET just suitable for unique circuit, and improves light-load efficiency effectively. The principle is design a circuit to compute the input and output power, and maps to one power conversion efficiency line which vary from load status. Furthermore, it can monitor power consumption in control stage circuit blocks. Once the efficiency line is below a threshold voltage, it will mean static loss is dominated in whole power loss. At the moment we shut down the circuit blocks which without work. Further, this thesis design a Energy Self-supply circuit, it can supply energy to load automatically in ultra light-load and open loop status if the power hungry ampilier is shut down. We couled achieve the purpose that output voltage is stable and static loss can be decreased, it makes the Light-load Efficiency better, the buck converter combinated with SOM and RT-MPET operates in the wide load range and maintains high power conversion efficiency.
Finally, this buck converter chip is designed and fabricated with TSMC 0.18μm 1P6M 3.3V Mixed Signal process technology. The chip use the improved version for maximum power efficiency tracking technique. This technology can operate in the wide load range, and track power efficiency for high light-load efficiency. In this thesis, light-load efficiency is over 72%, and operate from 1mA to 500mA load current.
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CHEN, CHUN-LIN, and 陳俊霖. "Series Resonant Converter with Volume Optimization and Efficiency Balance." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/63925247887804145077.
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碩士<br>國立臺灣科技大學<br>電子工程系<br>102<br>This thesis presents a series resonant converter (SRC) with volume optimization and efficiency balance. The front stage is a CCM buck converter. The output voltage of the post-stage SRC is sensed and can be regulated under full-range load conditions by adjusting the duty cycle of the buck converter. The SRC is operated around the first resonant frequency to reduce the volume of the magnetic components. Zero-voltage switching and synchronous rectification are adopted to improve the efficiency and increase the power density. In addition, a novel feedback controller is proposed in this thesis to lower the switching frequency at light loads, while raise the switching frequency at heavy loads.
A DC-DC power converter with an input voltage of 380 V, an output voltage of 12 V, and rated output current of 25 A is implemented. The switching loss at light load can be reduced with the presented control scheme. The load regulation is within 1%. Also the experimental results are provided to confirm the theoretical analysis.
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Yang, Shun-Pin, and 楊舜斌. "A High Efficiency Switched-Capacitor DC-DC up Converter." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/82947824464929343599.
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碩士<br>國立中山大學<br>電機工程學系研究所<br>91<br>A new DC-DC up converter with high efficiency and low output ripple is proposed. We replace previous charge pump converters by switched-capacitor converters to improve the power efficiency and add a voltage regulator at the output to reduce the ripple voltage. The converter reduces the magnitude of output voltage ripples to 36% of the previous converter, and improves the power efficiency from 58% to 73%. The proposed converter is designed to obtain 1.6 mA driving capability with a output voltage around 5.3 ~ 5.4 V. A VCO is also added as the load to test the converter circuit. The VCO is insensititive to power supply noises. The proposed converter circuit is simulated in a TSMC 0.35-um Mixed-mode (2P4M) CMOS process.
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Li, Chih-Hsuan, and 李至軒. "Fabrications of High Coupling Efficiency Spot-size Converter Lasers." Thesis, 1999. http://ndltd.ncl.edu.tw/handle/05926501122521014385.
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碩士<br>國立中山大學<br>光電工程研究所<br>87<br>In this thesis, we have fabricated high chip-to-fiber coupling 1.55mm InGaAsP/InP ridge-waveguide spot-size converter lasers. The active region consists of the separate confinement hetero-structure (SCH) of 1.55Q multiple quantum wells (six pairs of In0.58Ga0.42As0.9P0.1 /In0.75Ga0.25As0.55P0.45.) and 1.25Q-In0.75Ga0.25As0.55P0.45 confinement layers. In order to reduce the perpendicular far- field angle, two 0.2mm - thick 1.25Q passive waveguide layers are added aside to the active region to increase the spot size. Furthermore, to reduce lateral far-field angle, the taper ridge-waveguide width has two fashions: (1) reducing the waveguide width from 2.5mm to 1mm, (2) increasing the waveguide width from 2.5mm to 4mm.
Compared to the 24° * 46° output of the untapered 2.5mm-wide ridge waveguide laser without 1.25Q passive waveguides, our results show an improvement to 12°*32° output.
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Lin, Hui-Chang, and 林輝菖. "High Efficiency Quasi-Fixed-Frequency Quasi-Resonant Flyback Converter." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/62019999127108828186.
Full textAbstract:
碩士<br>國立臺灣科技大學<br>電子工程系<br>103<br>Conventionally, Quasi-Resonant (QR) flyback converter is required to turn on the active switch when the first voltage valley is detected. Therefore, the advantages of soft-switching can be achieved. However, for light-load output and high-voltage input, the duty cycle would be very small, and magnetizing current is also small. After the switch is turned off, the switch voltage could resonate to valley in very short time; therefore, the switch should be turned on again. The increased switching frequency results in higher switching loss and impairs the efficiency. The purpose of this thesis is to propose a high-efficiency QR-flyback converter. By the proposed “Quasi-Fixed-Frequency” algorithm to maintain the frequency within a small range, but still turns on the power switch at voltage-valley. Therefore, the characteristics of low switching-loss can be attained.
The prototype circuit in this thesis is a 65-W Quasi-Fixed-Frequency QR-flyback circuit, the control circuit is implemented by the IC UCC1803, which is the power-efficient version of the commonly used pulse-width-modulation (PWM) IC UC3843. In addition, a specific valley detection circuit is added on to fulfill the control task. The experimental results ascertain that this proposed circuit can improve efficiency during light-load and high-voltage input. Even at high-voltage input and heavy load, the efficiency is approaching 95%.
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Pienkos, John Thaddeus. "Low power efficiency tests for the Vlasov mode converter." 1994. http://catalog.hathitrust.org/api/volumes/oclc/32850962.html.
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Thesis (M.S.)--University of Wisconsin--Madison, 1994.<br>Typescript. eContent provider-neutral record in process. Description based on print version record. Includes bibliographical references (leaf 103).
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Tsai, Ming-Jia, and 蔡銘家. "High Efficiency LLC Resonant Converter with Adaptive Input Voltage." Thesis, 2017. http://ndltd.ncl.edu.tw/handle/rj3vds.
Full textAbstract:
碩士<br>國立臺灣科技大學<br>電機工程系<br>105<br>LLC resonant converters are widely used in medium power applications such as LCD TV power and server power, because it features many advantages such as wide zero-voltage-switching (ZVS) range and low component counts. Unlike other pulse width modulated power converters, LLC resonant converter regulates its output voltage by modulating its operating frequency. For some wide output range applications, the operating frequency may be very high. In addition, the conversion efficiency may downgrade if the operating frequency is far from the resonant frequency.
In this thesis, an adaptive input voltage LLC resonant converter is proposed. The dc-link voltage is adjusted to keep the LLC resonant converter operating at a nearly constant resonant frequency. Using this way, the conversion efficiency can be maximized. In order to validate the correctness of the proposed concept, a 480 W prototyping circuit is built. According to the experimental results, the measured conversion efficiencies of the designed system are all higher than 91.4 %. Comparing with conventional LLC resonant converter, the proposed control technique can improve the averaged conversion efficiency by 1.1 % and 0.31 % at light load and full load, respectively.
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Wen, Yi Hsieh, and 謝文益. "Converter Design for High-efficiency Automotive Permanent Magnet Generator." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/vub685.
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碩士<br>國立虎尾科技大學<br>機械與機電工程研究所<br>97<br>The paper is to design converter for permanent-magnet synchronous generator used in automotive power charge system. AC-DC-DC power converter transfers AC voltage of permanent magnet generator to DC voltage for lead-acid battery to fulfill the adjustment and allocation of energy of automotives. The analysis of converters to obtain the optimum efficiency is proposed in this thesis. The energy storage of battery is depend on the system power demands to control the charge to keep the battery voltage constant without being affected by speed of the generator.
The thesis can be divided into two parts; one is permanent-magnet alternating generator, and the other is power converter. In the permanent-magnet alternating generator, the permanent-magnet alternating motor DTSB08751 by Teco Technology is to generate with output voltage between the 56 V and 220 AC. In power converter, a rectifier and a buck converter are used to convert AC to DC power with stable voltage output. Finally, the digital signal processor (OZ8604) as the control core is used to control the converter. The prototype of 440W generator system has been roughly achieved, and the test results are provided to show the feasibility of system design.
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Wu, Mao-Fu, and 吳懋富. "Wide Load Range High Efficiency Multiphase DC-DC Converter." Thesis, 2019. http://ndltd.ncl.edu.tw/handle/sad22v.
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碩士<br>國立臺灣科技大學<br>電子工程系<br>107<br>For a system-on-chip (SoC) of mobile device, the power supply is required to have driving capability of high current, high efficiency, fast load transient, small area and so on. Wide Load Range High Efficiency Multiphase DC-DC Converter is presented in this paper. By advantage of constant on time control achieve fast transient response and By using adjustable area of mosfet, frequency and numbers of phases improve efficiency. Finally, the figure of efficiency can get better curve in wide load.The chip is implemented in TSMC 0.18μm 1P6M CMOS process. The chip area including PADs is 2.5×1.515 mm2. The specifications of the converter are the input voltage range of 3V~3.6V, output voltage of 1.8V, switch frequency of 2 MHz, current range of 10mA~2000mA. The off-chip inductance and capacitance are 2.7 μH and 10 μF, respectively. ESR of the output capacitance is 15 mΩ. When converter current is set as 300mA, the efficiency improved is up to 25%.
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Lee, Sang Hyeon. "High efficiency wideband low-power delta-sigma modulators." Thesis, 2012. http://hdl.handle.net/1957/30022.
Full textAbstract:
Delta-sigma analog-to-digital converters traditionally have been used for low speed, high
resolution applications such as measurements, sensors, voice and audio systems.
Through continued device scaling in CMOS technology and architectural and circuit
level design innovations, they have even become popular for wideband, high
dynamic range applications such as wired and wireless communication systems.
Therefore, power efficient wideband low power delta-sigma data converters that bridges
analog and digital have become mandatory for popular mobile applications today.
In this dissertation, two architectural innovations and a development and
realization of a state-of-the-art delta-sigma analog to digital converter with effective design
techniques in both architectural and circuit levels are presented. The first one is
timing-relaxed double noise coupling which effectively provides 2nd order noise
shaping in the noise transfer function and overcomes stringent timing requirement
for quantization and DEM. The second one presented is a noise shaping SAR
quantizer, which provides one order of noise shaping in the noise transfer function.
It uses a charge redistribution SAR quantizer and is applied to a timing-relaxed lowdistortion
delta-sigma modulator which is suitable for adopting SAR quantizer.
Finally a cascade switched capacitor delta-sigma analog-to-digital converter suitable for
WLAN applications is presented. It uses a noise folding free double sampling
technique and an improved low-distortion architecture with an embedded-adder
integrator. The prototype chip is fabricated with a double poly, 4 metal, 0.18μm
CMOS process. The measurement result achieves 73.8 dB SNDR over 10 MHz
bandwidth. The figure of merit defined by FoM = P/(2 x BW x 2[superscript ENOB]) is 0.27
pJ/conv-step. The measurement results indicate that the proposed design ideas are
effective and useful for wideband, low power delta-sigma analog-to-digital converters with
low oversampling ratio.<br>Graduation date: 2012<br>Access restricted to the OSU Community at author's request from June 19, 2012 - June 19, 2013
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Zhang, Chao. "A Dual-Supply Buck Converter with Improved Light-Load Efficiency." Thesis, 2011. http://hdl.handle.net/1969.1/ETD-TAMU-2011-05-9521.
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Power consumption and device size have been placed at the primary concerns for battery-operated portable applications. Switching converters gain popularity in powering portable devices due to their high efficiency, compact sizes and high current delivery capability. However portable devices usually operate at light loads most of the time and are only required to deliver high current in very short periods, while conventional buck converter suffers from low efficiency at light load due to the switching losses that do not scale with load current. In this research, a novel technique for buck converter is proposed to reduce the switching loss by reducing the effective voltage supply at light load.
This buck converter, implemented in TSMC 0.18 micrometers CMOS technology, operates with a input voltage of 3.3V and generates an output voltage of 0.9V, delivers a load current from 1mA to 400mA, and achieves 54 percent ~ 91 percent power efficiency. It is designed to work with a constant switching frequency of 3MHz. Without sacrificing output frequency spectrum or output ripple, an efficiency improvement of up to 20 percent is obtained at light load.
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Zhou, Xin. "Resonant gate driver design for high efficiency switching power converter." 2010. http://www.lib.ncsu.edu/resolver/1840.16/5991.
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CHEN, JIA-SHENG, and 陳家陞. "Analysis and Implementation of High Efficiency ZVS-ZCS Resonant Converter." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/80425303252449694013.
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碩士<br>國立雲林科技大學<br>電機工程系<br>104<br>A high efficiency ZVS-ZCS DC-DC resonant converter is proposed in this thesis. For high input voltage application, the primary side of the proposed converter consists of three half-bridge LLC resonant converters that are connected in series. Three split capacitors are adopted so that the voltage on each half-bridge circuit becomes one third of the input voltage, hence the voltage stress of the power switches is mitigated. The input voltage autobalance ability is achieved by introducing two flying capacitors, which eliminate additional components or complex control circuits in conventional converters. For the purpose of low output voltage and high output current applications, the secondary side of the proposed converter is composed of three center-tapped rectifiers connected in parallel to suppress the current ratings of the output rectifier diodes. Based on the characteristics of the LLC resonant converter, the zero voltage switching (ZVS) for whole power switches can be achieved under all load conditions, and the zero current switching (ZCS) of the output rectifier diodes at heavy load is reached. Therefore, the switching losses on power switches and the reverse recovery current losses on the output rectifier diodes are significantly reduced.
Finally, the design and the operation modes of the proposed converter will be analyzed in depth. Furthermore, the feasibility of the proposed converter is verified by the software, SIMetris-SIMPLIS. The input voltage of the experimental circuit ranges from 750 to 800 Vdc, the output voltage is 24 Vdc, the load current is 60 A and the output power is 1440 W.
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Chen, Hui. "A Dual Supply Buck Converter with Improved Light Load Efficiency." Thesis, 2013. http://hdl.handle.net/1969.1/149497.
Full textAbstract:
Power consumption is the primary concern in battery-operated portable applications. Buck converters have gained popularity in powering portable devices due to their compact size, good current delivery capability and high efficiency. However, portable devices are operating under light load condition for the most of the time. Conventional buck converters suffer from low light-load efficiency which severely limits battery lifetime.
In this project, a novel technique for buck converter is proposed to reduce the switching loss by reducing the effective input supply voltage at light load. This is achieved by switching between two different input voltages (3.3V and 1.65V) depending on the output current value. Experimental results show that this technique improves the efficiency at light loads by 18.07%. The buck voltage possesses an output voltage of 0.9V and provides a maximum output current of 400mA. The buck converter operates at a switching frequency of 1MHz. The prototype was fabricated using 0.18µm CMOS technology, and occupies a total active area of 0.6039mm^2.
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ZHANG-JIAN, CHENG-KAI, and 張簡丞凱. "High Efficiency Dual-Mode Buck Converter with Accurate Current Sensing." Thesis, 2017. http://ndltd.ncl.edu.tw/handle/77fx3u.
Full textAbstract:
碩士<br>國立高雄應用科技大學<br>電子工程系<br>105<br>In this thesis, a buck converter with accurate output current sensing mechanism to the change of loading current is proposed. The current sensing circuit can reduce the response time of control circuit of power transistor and the energy in inductor can be stored or released fast. It reduces the influence of loading current change on output voltage. Compared to voltage-mode control method, the current-mode control has better properties of load regulation, line regulation and fast transient response. The soft-start circuit and the zero current sensing circuit are added to avoid the large excess switching current at the start-up and the energy loss due to the reverse conduction of inductor current. The buck converter can be used for portable systems with lithium-battery power supply. The dual-mode modulation technique for 10mA-600mA output loading current is used to increase the overall efficiency. When the output loading current is less than 100mA, the buck converter will operate in pulse-frequency modulation mode. The modulated signal with fixed duty cycle will reduce excessive switching loss. When the output loading current is greater than 100mA, the buck converter will operate in the pulse-width modulation mode. The maximum converting efficiency is about 96.41%. The buck converter is designed in TSMC 0.35μm 2P4M 3.3V/5V mixed-signal CMOS technology.
Keywords: accuracy current sensing, buck converter, dual-mode modulation, lithium battery.