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Journal articles on the topic 'Digital Down Conversion (DDC)'

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Published: 4 June 2021

Last updated: 6 September 2023

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Guo, Lianping, Feng Tan, Peng Zhang, and Hao Zeng. "Decomposing Numerically Controlled Oscillator in Parallel Digital Down Conversion Architecture." Journal of Circuits, Systems and Computers 26, no. 09 (2017): 1750126. http://dx.doi.org/10.1142/s0218126617501262.

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The speed of digital signal processing device restricts the performance of the serial digital down conversion (DDC) architecture when the input of the DDC features a high sampling rate. As a result, the polyphase or parallel structure is adopted to relieve the speed pressure. This paper mainly studies the numerically controlled oscillator (NCO) decomposing in the parallel DDC structure, which can decompose the NCO’s output into several branch signals which then can lower the operating speed of the mixer and the low pass filter (LPF) significantly, making it easier to implement DDC with field programmable gate array (FPGA). The mathematical expressions of the branch NCO outputs applied to the parallel DDC are deduced and the selection principles of the correlated parameters are discussed. The simulation and the experimental results of MATLAB show the corrections of the NCO decomposing technique.

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Mewada, Hiren K., and Jitendra Chaudhari. "Low computation digital down converter using polyphase IIR filter." Circuit World 45, no. 3 (2019): 169–78. http://dx.doi.org/10.1108/cw-02-2019-0015.

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Purpose The digital down converter (DDC) is a principal component in modern communication systems. The DDC process traditionally entails quadrature down conversion, bandwidth reducing filters and commensurate sample rate reduction. To avoid group delay, distortion linear phase FIR filters are used in the DDC. The filter performance specifications related to deep stopband attenuation, small in-band ripple and narrow transition bandwidth lead to filters with a large number of coefficients. To reduce the computational workload of the filtering process, filtering is often performed as a two-stage process, the first stage being a down sampling Hoegenauer (or cascade-integrated comb) filter and a reduced sample rate FIR filter. An alternative option is an M-Path polyphase partition of a band cantered FIR filter. Even though IIR filters offer reduced workload to implement a specific filtering task, the authors avoid using them because of their poor group delay characteristics. This paper aims to propose the design of M-path, approximately linear phase IIR filters as an alternative option to the M-path FIR filter. Design/methodology/approach Two filter designs are presented in the paper. The first approach uses linear phase IIR low pass structure to reduce the filter’s coefficient. Whereas the second approach uses multipath polyphase structure to design approximately linear phase IIR filter in DDC. Findings The authors have compared the performance and workload of the proposed polyphase structured IIR filters with state-of-the-art filter design used in DDC. The proposed design is seen to satisfy tight design specification with a significant reduction in arithmetic operations and required power consumption. Originality/value The proposed design is an alternate solution to the M-path polyphase FIR filter offering very less number of coefficients in the filter design. Proposed DDC using polyphase structured IIR filter satisfies the requirement of linear phase with the least number of computation cost in comparison with other DDC structure.

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Yan, Ji Hong, Zi Shu He, Xiao Hong Tang, and Dao Guo Yang. "A Wideband DDC Design Using Distributed Arithmetic." Applied Mechanics and Materials 321-324 (June 2013): 1303–6. http://dx.doi.org/10.4028/www.scientific.net/amm.321-324.1303.

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In this paper, the technique of distributed arithmetic (DA) and digital down conversion (DDC) are described. Then, an efficient wideband DDC based on polyphase structure with intermediate frequency (IF) bandpass sampling is presented. An optimized distributed arithmetic is used for saving the FPGA multiplier consumption. A design example is given and the FPGA resource consumption saving is discussed also. The corresponding test results demonstrate the effectiveness of the proposed DDC design using distributed arithmetic.

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Traykov, Metodi, Radoslav Mavrevski, and Ivan Trenchev. "Modeling of digital converter for GSM signals with MATLAB." International Journal of Electrical and Computer Engineering (IJECE) 9, no. 5 (2019): 4417. http://dx.doi.org/10.11591/ijece.v9i5.pp4417-4422.

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In this study will simulate steady state of Digital Down Convertor (DDC) for GSM signal with a narrow frequency range. The MATLAB model that is described in this article simulates the work of the TIGC4016 Quad Digital Down Converter. This converter is used for digital mixing (down conversion) of signals, narrow band low-pass filtering and decimation. To implementation of the model, we use high sample-rate (69,333 MSPS) bandpass signal. The result contains low sample-rate (270.83 KSPS) baseband signal, thus facilitating the demodulation process.

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Sahukar, Latha, and Dr M. Madhavi Latha. "Frequency Domain based Digital Down Conversion Architecture for Software Defined Radio and Cognitive Radio." International Journal of Engineering & Technology 7, no. 2.16 (2018): 88. http://dx.doi.org/10.14419/ijet.v7i2.16.11422.

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This paper presents a sampling rate digital down converter that is totally based on frequency domain processing. The proposed DDC is targeted for Software Defined Radio and Cognitive Radio architectures. The proposed architecture is based on replacement of the complex multiplication with direct rotation of the spectrum. Different aspects of frequency domain filtering are also discussed. The Xilinx Virtex-6 family FPGA, XC6VLX240T is used for the implementation and synthesis of the proposed FFT-IFFT based architecture. The overlapping in time domain at the output of the IFFT block is avoided using overlap and add method. In terms area, highly optimized implementation is observed in the proposed architecture when compared to the conventional DDC. The synthesis results have shown that the developed core works at a maximum clock rate of 250 MHz and at the same time occupies only 10% of the slices of FPGA.

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Han, Chun Yang, Wei Sun, and Gui Xin Han. "DDC Design for Multi-Frequency Receiver Based on RF Sampling." Applied Mechanics and Materials 651-653 (September 2014): 413–16. http://dx.doi.org/10.4028/www.scientific.net/amm.651-653.413.

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Multi-frequency receivers rely on GNSS to achieve high-precision positioning, high sensitivity and other functions. GNSS signal frequencies are widely distributed around 1.1GHz to 1.6GHz. Good performance RF front-end receiver will provide high-quality acquisition and tracking environment, reducing the SER to ensure CNR. RF sampling technique is widely used in software radio for its simple structure, flexible configuration, and other advantages, but rarely used in satellite navigation, because the high signal carrier frequency and sampling rate, down-conversion based on RF sampling becomes a big challenge. So, to solve the problems of widely distributed we design three signal bands, using different local oscillator to implement signal down-conversion; to solve the problems of high sampling rate, we propose a down-conversion program of using a cascade of CIC filter’s ployphase and FIR compensation filter. Through the simulation of MATLAB after tracking tests, analysis of CNR and other indicators of programs. Ultimately, we implement the program with Verilog language on the multi-frequency GNSS receiver. The results show that this scheme can achieve digital down-conversion and stable performance of tracking loop with less consumption of resources.

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Li, Yao. "Design and Research of Digital Decimation Filter Based on FPGA." Applied Mechanics and Materials 105-107 (September 2011): 2086–91. http://dx.doi.org/10.4028/www.scientific.net/amm.105-107.2086.

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This paper studies and analyses various digital filter and decimation structure. On this basis, by using QUARTUS development system design the decimation device modules, through the waveform simulation validated its correctness. Finally,a program is written into FPGA chip by the hardware platform. In the digital down conversion (DDC), CIC (cascade integral comb) filter plays an important role. It is mainly used for sampling rate, as well as low-pass filter effect. The main characteristics of CIC filter, using only adders, subtractor and register (no multiplier), so fewer resources occupied, implementation is simple and high speed. Based on the analysis of the principle of CIC filter,simulate and synthesize based on the theory of using VHDL language in FPGA. And successful application in the development of DDC chip. Keyword: CIC (cascade integral comb) filter,FPGA,VHDL

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Karcher, N., D. Richter, F. Ahrens, et al. "SDR-Based Readout Electronics for the ECHo Experiment." Journal of Low Temperature Physics 200, no. 5-6 (2020): 261–68. http://dx.doi.org/10.1007/s10909-020-02463-w.

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Abstract Due to their excellent energy resolution, the intrinsically fast signal rise time, the huge energy dynamic range, and the almost ideally linear detector response, metallic magnetic calorimeters (MMC)s are very well suited for a variety of applications in physics. In particular, the ECHo experiment aims to utilize large-scale MMC-based detector arrays to investigate the mass of the electron neutrino. Reading out such arrays is a challenging task which can be tackled using microwave SQUID multiplexing. Here, the detector signals are transduced into frequency shifts of superconducting microwave resonators, which can be deduced using a high-end software-defined radio (SDR) system. The ECHo SDR system is a custom-made modular electronics, which provides 400 channels equally distributed in a 4 to 8 GHz frequency band. The system consists of a superheterodyne RF frequency converter with two successive mixers, a modular conversion, and an FPGA board. For channelization, a novel heterogeneous approach, utilizing the integrated digital down conversion (DDC) of the ADC, a polyphase channelizer, and another DDC for demodulation, is proposed. This approach has excellent channelization properties while being resource-efficient at the same time. After signal demodulation, on-FPGA flux-ramp demodulation processes the signals before streaming it to the data processing and storage backend.

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Ouyang, Xinxin, Shanfeng Yao, and Qun Wan. "Multiple Signal TDOA/FDOA Joint Estimation with Coherent Integration." Electronics 12, no. 9 (2023): 2151. http://dx.doi.org/10.3390/electronics12092151.

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Passive localization relies significantly on the estimation of the Time Difference of Arrival (TDOA) and Frequency Difference of Arrival (FDOA) to accurately determine the location of a target. The precision of TDOA and FDOA estimation is affected by signal parameters of time and frequency distribution. In case of multiple signals arising at different frequency bands and intercepted simultaneously by spatially separate sensors covering a wide frequency band, the traditional method is first to separate the signals from the mixed wideband signal through digital down conversion (DDC), which brings multiple narrowband signals, and then the estimation of TDOA and FDOA of each narrowband signal can be performed using cross ambiguity function (CAF). The paper introduces a novel approach for estimating TDOA and FDOA of multiple signals simultaneously, which employs a coherent integration method. First, the cross ambiguity function for each signal is realized with the narrowband signal as the same as the traditional method. Next, the phase relation of each CAF is analyzed, then the joint CAF can be obtained with phase compensation, from which multiple signal TDOA and FDOA estimations will be implemented simultaneously. Numerical simulations are performed to compare the two methods, and the results demonstrate the superiority of the proposed algorithm.

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SHIN, YOUNG SAN, JAE-KYUNG WEE, JONG-CHAN HA, JI-HOON LIM, YONG-JU KIM, and YOUNG-SANG SON. "A SEAMLESS-CONTROLLED DIGITAL PLL USING DUAL LOOPS FOR HIGH SPEED SOCS." Journal of Circuits, Systems and Computers 20, no. 04 (2011): 741–56. http://dx.doi.org/10.1142/s021812661100758x.

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A new dual-loop digital phased-locked loop (DPLL) architecture is presented. This novel architecture is designed to provide a wide operating frequency range, high precision, and small jitter, and fits over a relatively small area. To achieve these characteristics, the architecture is implemented using a coarse loop with an UP/DOWN counter and a coarse digital-to-analog converter (DAC) to rapidly reduce the phase error, and a fine loop with a time-to-digital converter (TDC) and a fine DAC to provide more precision. Furthermore, the seamless-frequency tracking architecture based on a code conversion between the coarse cell and the fine cell of the DAC is devised to improve the lock-in stability. The chip is fabricated with Dongbu HiTek 0.18-μm CMOS technology. It has a wide operation range of 0.4–1.4 GHz, and an area of 0.195 mm2. The measured results show 15.64 ps peak-to-peak jitter and 2.22 ps rms jitter, and a power dissipation of 16.2 mW at 1 GHz.

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Bekal, Anush, Shabi Tabassum, and Manish Goswami. "Low Power Design of a 1 V 8-bit 125 fJ Asynchronous SAR ADC with Binary Weighted Capacitive DAC." Journal of Circuits, Systems and Computers 26, no. 05 (2017): 1750077. http://dx.doi.org/10.1142/s0218126617500773.

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The work proposes an improved technique to design a low power 8-bit asynchronous successive approximation register (ASAR), an analog-to-digital converter (ADC). The proposed ASAR ADC consists of a comparator, ASAR (digital control logic block), and a capacitive-digital-to-analog convertor (C-DAC). The comparator is a preamplier-based improved positive feedback latch circuit which has a built-in sample and hold (S/H) functionality and saves an enormous amount of power. The implemented digital control logic block performing the successive approximation (SA) algorithm is totally unrestrained of the external clock pulse. The outputs from the comparator are given to a XOR logic whose outputs serve as an internally generated clock (ready signal) to trigger the digital control block. Hence, an external clock is not required to initiate the digital control block making its operation asynchronous. By implementing this, the ADC can circumvent the usage of an oversampled clock and can operate on a single low-speed sample clock. This, in turn, saves power and it cuts down the required resilience in sampling rates. The proposed ADC has been designed and simulated using UMC-0.18[Formula: see text][Formula: see text]m CMOS technology which dissipates 32.18[Formula: see text][Formula: see text]W power when operated on a single 1[Formula: see text]V power supply and achieves complete 8-bit conversion in 1.09[Formula: see text][Formula: see text]s. The relative accuracy of capacitor ratio, aperture jitter and FOM are 0.39[Formula: see text], 1.2[Formula: see text]ns and 125[Formula: see text]fJ/conversion-step, respectively.

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Zhang, Qiang. "An Improved Swiss Rectifier and Its Nonlinear Control for Lower THD." CPSS Transactions on Power Electronics and Applications 7, no. 3 (2022): 319–27. http://dx.doi.org/10.24295/cpsstpea.2022.00029.

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Three-phase power factor correction (PFC) converters capable of step-down voltage are attractive in lower components voltage stress, and optimal design of following dcdc stage, which is an alternative for next-generation datacenter power conversion. An improved three-phase step-down PFC converter (swiss rectifier) based on harmonic-current-injection (HCI) concept is proposed. It improves input current quality by eliminating switching dead zone of HCI network and avoids short circuit fault from hardware level. According to one-cycle control (OCC), a novel nonlinear control strategy (termed as closed-loop OCC) is presented, which reduces the impact of dc inductor current ripple on input current. The principles of the improved swiss rectifier and closed-loop OCC are analyzed in detail, verified by simulation and on an 80 kHz, 300 V/2 kW prototype with digital controller. At rated condition, input current THD < 2%.

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Chen, Yanbo, Qiong Nie, Chaowei Zhong, et al. "A 24 nW 10-bit 10 kS/s ultra-low-power SAR ADC for biomedical devices." AIP Advances 13, no. 2 (2023): 025351. http://dx.doi.org/10.1063/5.0138835.

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This paper proposed an ultra-low-power successive approximation register analog to digital converter (ADC) for medical implant devices. To reduce power consumption, the novel techniques presented in this paper are a tri-state capacitor unit, a novel switch scheme, and a new low static power comparator. Tri-state capacitor unit reduces down power without the use of middle voltage reference. The proposed switch scheme can complete the most-significant bit 3-bit conversion without any power consumption. The offset of the low static power comparator is only optimized by physical design. This ADC is fabricated in a 110 nm 1P5M CMOS process. The reference voltage of DAC is 1 V, and the supply voltage of comparator and digital logic is 1 .5 V. At 10 kS/s sampling rate, the signal to noise and distortion ratio (SNDR) is 57 .57 dB and power consumption is 24 nW.

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Dhanabalan, Gnanasekaran, Sankar Tamil Selvi, and Miroslav Mahdal. "Scan Time Reduction of PLCs by Dedicated Parallel-Execution Multiple PID Controllers Using an FPGA." Sensors 22, no. 12 (2022): 4584. http://dx.doi.org/10.3390/s22124584.

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A programmable logic controller (PLC) executes a ladder diagram (LD) using input and output modules. An LD also has PID controller function blocks. It contains as many PID function blocks as the number of process parameters to be controlled. Adding more process parameters slows down PLC scan time. Process parameters are measured as analog signals. The analog input module in the PLC converts these analog signals into digital signals and forwards them to the PID controller as inputs. In this research work, a field-programmable gate array (FPGA)-based multiple PID controller is proposed to retain PLC scan time at a lower value. Concurrent execution of multiple PID controllers was assured by assigning separate FPGA hardware resources for every PID controller. Digital input to the PID controller is routed by the novel idea of analog to digital conversion (ADC), performed using a digital to analog converter (DAC), comparator, and FPGA. ADC combined with dedicated PID controller logic in an FPGA for every closed-loop control system confirms concurrent execution of multiple PID controllers. The time required to execute two closed-loop controls was identified as 18.96000004 ms. This design can be used either with or without a PLC.

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Zhao, Jing, Hao Nie, and Jing Yu. "A IF Signal Precessing System Design Based on Software Radio Platform." ITM Web of Conferences 17 (2018): 01014. http://dx.doi.org/10.1051/itmconf/20181701014.

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Software radio is a definition of a design thought about how to implement flexible functions by using fixed hardware platform. Any platform based on this is characterized to be universal, standardized, modular, open and highly flexible. Due to some realistic reasons, a software radio platform is hard to be realized. So, most signal processing is operated after mixing. According to software radio requirements, a “FPGA+ADC+DAC” structure is designed. Compared with former processors, this module has broad application prospects with the small size, low power, configurable and programmable feathers. It has multifunction, such as generating IF signals, performing digital down conversion and realizing the synchronous demodulation and the other functions. This module also provides the extended host interface to communicate with upper computers. According to the practical test, take MSK signal for example, if the bit rate is 1Mb/s, bit error rate is lower than 10-6.

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Cui, Shu Lin, and Xu Li. "FPGA-Based Design of Resource-Efficient Digital down Converter." Applied Mechanics and Materials 128-129 (October 2011): 878–81. http://dx.doi.org/10.4028/www.scientific.net/amm.128-129.878.

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Digital down converter (DDC) is based on the theory of Software Defined Radio (SDR) and multirate signal processing, extensively applied in digital receivers of communications systems. An improved resource-efficient DDC with polyphase architecture and distributed arithmetic (DA) is presented in this paper. The design based on Xilinx FPGA Virtex-5 has more flexible characters and higher precision computation with less resource consumption.

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Zhou, Yizhao, Shuang Song, Shiwei Wang, et al. "A Review on Direct Digital Conversion Techniques for Biomedical Signal Acquisition." Electronics 12, no. 12 (2023): 2676. http://dx.doi.org/10.3390/electronics12122676.

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Biomedical signals such as Electrocardiogram (ECG), Electroencephalogram (EEG) and photoplethysmography (PPG) are recorded routinely to provide helpful information for early diagnosis of disease. Low power consumption is very important to allow long-term ambulatory monitoring with battery-powered systems. A direct digital conversion (DDC) technique has been proposed in recent years, which employs preamplifier and data converters, reducing the complexity of the readout chain and thus its power consumption. This paper provides a review on DDC for biopotential signals and bio-optical signal acquisition. The state-of-the-art DDC-based readout architectures together with circuit implementations are provided.

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Telagathoti, Pitchaiah, Moparthi Aparna, and P. V. Sridevi. "Design and FPGA Implementation of Digital Down Converter for LTE-SDR Receiver." International Journal of Engineering & Technology 7, no. 2-1 (2018): 421. http://dx.doi.org/10.14419/ijet.v7i2.9242.

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Due to huge demand for high data rate transmission, there is requirement for efficient design of Digital Down Converter (DDC) in wireless communications. DDC is an indispensable part in modern communication, as for higher frequencies it is difficult to down convert the frequency directly to the baseband frequency. Hence a super heterodyne receiver is used to convert the received signal into an intermediate frequency and the intermediate frequency is then converted into the baseband frequency. The architecture of DDC mainly consists of two parts; first one is demodulation and second one is decimation system. The first stage performs the demodulation and the second stage decimation system performs the operation of filtering and decimation. This paper discusses the design and FPGA implementation of DDC for the LTE-SDR receiver for band5 in LTE(UMTS) standards. The design and FPGA implementation of DDC for LTE-SDR is developed and tested using SystemVue software and Xilinx ML507 FPGA board. The results show that simulation results and FPGA implementation results are very close to each other, so the designed DDC can be used in real time LTE SDR application with hardware as FPGA for efficient processing of data with minimum number of resources and at higher operating frequency.

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Datta, Debarshi, and Himadri Dutta. "Area and power-efficient reconfigurable digital down converter on FPGA." Facta universitatis - series: Electronics and Energetics 35, no. 2 (2022): 243–52. http://dx.doi.org/10.2298/fuee2202243d.

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This paper presents a field-programmable gate array (FPGA)-based digital down converter (DDC) that can reduce the bandwidth from about 70 MHz to 182.292 kHz. The proposed DDC consists of a polyphase COordinate Rotation DIgital Computer (CORDIC) processor and a multirate filter. The advantage of polyphase CORDIC processor is to process with high sample rate input data and produces computational efficient noiseless baseband spectrum. The pipeline multirate filter works at a high clock speed. Moreover, the multirate filter generates a fractional sample rate factor using a cubic B-spline Farrow filter. The proposed DDC is coded with optimal hardware description language (HDL) and tested on Kintex-7 Xilinx FPGA as the target device. Experimental results indicate that the proposed design saves chip area, power consumption and operates at high speed without loss of any functionality. Additionally, the proposed design offers sufficient spurious-free dynamic range (SFDR) and produces less than 1 Hz frequency resolution at the output.

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Xu, Ping, Wei Xia, and Zi Shu He. "A Design of VB-DDC Using DA-Based Systolic FIR Filter." Applied Mechanics and Materials 130-134 (October 2011): 3950–53. http://dx.doi.org/10.4028/www.scientific.net/amm.130-134.3950.

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In this paper, we present yet another design of the variable-bandwidth digital down-converter (VB-DDC). The shaping filter in the DDC architecture is substitute with a method which is implemented with fully pipelined computing structure of systolic decomposition for distributed arithmetic (DA) based FIR filer. The systolic structure of the FIR filter involves significantly less memory and complexity compared with the existing ones. The effectiveness of the design is validated by the proposed FPGA implementation results.

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Wang, Wen Bin, Dao Yuan Liu, and Yu Qin Yao. "Research and Design of Digital down Converter Based on Software Defined Radio." Applied Mechanics and Materials 513-517 (February 2014): 1803–6. http://dx.doi.org/10.4028/www.scientific.net/amm.513-517.1803.

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This paper makes a brief introduction on the current development trend of software radio and digital down converter status. The basic theoretical knowledge: Band-pass sampling theorem, digital signal orthogonal transformation theory, multi-rate signal processing theory. Based on these theories, use MATLAB complete the design and verification of mixing module, the extraction module (CIC filter, half-band filter and FIR filters), finally verify the correctness of the design, and implement DDC.

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Wang, Yi, Shuai Ji, and Yang Guan. "The Design of Four Channel TR Module for Ku Band." Journal of Physics: Conference Series 2189, no. 1 (2022): 012006. http://dx.doi.org/10.1088/1742-6596/2189/1/012006.

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Abstract This paper presents the design and development of four channel digital TR module for Ku band.The four channel TR module for Ku band consists of consists of digital part and RF part. DDS, TR control, AD, DDC and echo transmission constitute the digital transceiver part of the digital TR module. Two-stage frequency conversion and filtering, circulator, limiter, multi-stage LNA and multi-stage PA constitute the the RF transceiver part of the digital TR module. At present, the digital TR module has completed the program design, production and processing, testing.

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BOIKO, JULIY, ILYA PYATIN, and IGOR PARKHOMEY. "SIGNAL PROCESSING AND SYNCHRONIZATION TECHNIQUE IN SOFTWARE-DEFINED RADIO SYSTEMS WITH OFDM." Herald of Khmelnytskyi National University. Technical sciences 307, no. 2 (2022): 123–32. http://dx.doi.org/10.31891/2307-5732-2022-307-2-123-132.

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The article describes modern concepts for the development of Software-defined Radio (SDR) technology. A functional diagram of a software-defined radio station using the method of transmitting information with modulation based on Orthogonal Frequency Division Multiplexing (OFDM) is proposed. The conditions for ensuring symbol synchronization of OFDM signals are investigated. It is determined that the disruption of the orthogonality of OFDM symbols is accompanied by such phenomena as the occurrence of inter-symbol interference and inter-channel interference. The method of constellation diagrams was used to study the effect of errors caused by interference on the quality of processing of multiposition signals. The effect of interference in a channel from OFDM on the phase of signals during their processing is estimated. Mathematical models of signals with OFDM in the presence of interference effects are obtained. Two types of errors are considered, which are caused by carrier distortion. In particular, the occurrence of phase noise is possible, the cause of which is associated with the instability of the generating equipment of the carrier signals both on the transmitting and on the receiving side. Another factor is carrier offset due to Doppler frequency. The proposed SDR receiver structure is based on the digital IF architecture. This architecture has more flexibility than traditional RF architectures and is not sensitive to DC offset, LO leakage, etc. Moreover, since the I/Q up/down conversion is done digitally in the IF stage, the negative effects caused by I/Q imbalance will be minimized. The SDR consists of a small piece of hardware at the RF input, i.e., an antenna and a high-rate ADC capable of capturing and digitizing broadband radio signals. To increase the communication range in SDR, we use amplifiers in front of two DAC/ADC stages. The receiver has a low-noise amplifier to reduce the quantization noise of the transducer and increase the Signal-to-noise Ratio (SNR). The data is then processed on specialized computational units within the embedded system, enabling important demodulation, synchronization, and decoding techniques to be implemented.

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Sun, Xu Dong, and Yong Bin Leng. "MATLAB Simulation of DBPM Digital Down Conversion." Applied Mechanics and Materials 333-335 (July 2013): 680–83. http://dx.doi.org/10.4028/www.scientific.net/amm.333-335.680.

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A software defined radio architecture algorithm is applied to Digital BPM processor for its signal processing. The algorithm is evaluated in MATLAB with data acquired from the instrument with a commercial signal source as input.The data flow diagram of the algorithm is shown and explained, critical parameters of the filters are displayed and the results are shown which testify the feasibility of the method.

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Deng, Jun, Lin Tao Liu, Yu Jing Li, Xiao Zong Huang, Xu Huang, and Lun Cai Liu. "Design of a SoC With High-Speed DDC for Software Radio Receiver." Advanced Materials Research 605-607 (December 2012): 1875–79. http://dx.doi.org/10.4028/www.scientific.net/amr.605-607.1875.

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This paper presents a novel scheme for software radio receiver application, which integrates a high-speed digital down converter (DDC) block into a SoC (system on chip) based on OR1200 CPU. The proposed design can transform intermediate frequency (IF) signal to baseband signal and realize the real-time baseband signal processing. The simulation results indicate that the design is capable of accepting data at a 200MHz sample rate and the verification results based on Xilinx FPGA show that the SFDR of DDC can reach to 70.59dBFS.The synthesized results on 0.18um CMOS technology reveal that the maximum clock frequency can reach to 116MHz and the total area is 5.662mm2, and the corresponding power consumption is below 150mW. It should have a good potential for wireless communication applications.

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A, Athulya, and Dinesha P. "STUDY ON DIGITAL DOWN CONVERSION TECHNIQUE IMPLEMENTED ON FPGA." International Journal of Engineering Applied Sciences and Technology 5, no. 3 (2020): 363–67. http://dx.doi.org/10.33564/ijeast.2020.v05i03.058.

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Xie, Xiao Ming, and Hui Meng Huang. "Design and Analysis of Digital Filter in Digital Down Converter." Advanced Materials Research 433-440 (January 2012): 2844–49. http://dx.doi.org/10.4028/www.scientific.net/amr.433-440.2844.

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In this paper, based on the analysis and discussion of multistage decimation structure, we have studied and analyzed some key technologies of the digital filter in digital down conversion. Meanwhile, we have analyzed and summarized the decimation filter modules as CIC, HB, FIR of the digital filter, and a multistage decimation filter design program is given in this paper. An optimum design method is proposed in this article, which greatly reduce the complexity of system design and memory usage and has upgrade the data rate operation with great extent.

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Tsvetkov, A. N., and Doan Ngok Shi. "Hardware-software complex for experimental research of electric drives of asynchronous motors with squirrel-cage rotor with traditional winding and motors with combined winding." Power engineering: research, equipment, technology 23, no. 6 (2022): 157–65. http://dx.doi.org/10.30724/1998-9903-2021-23-6-157-165.

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THE PURPOSE. Modern requirements for electric drives impose increasingly stringent conditions for energy efficiency, dimensions and weight. The weight and size parameters are especially noticeable in relation to the rapidly developing electric transport. The achieved technological limits practically do not give tangible results in improving the characteristics of known structures, so there is a struggle for units of percent and fractions of a percent in terms of increasing the efficiency of equipment.MATERIALS. Debugging and fine-tuning of electric drive elements requires numerous tests on research benches using measuring channels and analog-to-digital conversion (ADC), digital-to-analog conversion (DAC), digital-to-digital conversion (DDC).RESULTS. The creation of research stands implies the development of a hardware-software complex (HSC) based on high-speed computing devices. The structure of the HSC included the developed frequency converter with the possibility of adjusting the algorithms for controlling the electric motor and the mathematical model of the electric motor itself. The object of experimental research was prototypes of electric drives based on asynchronous electric motors with a squirrel-cage rotor and a combined stator winding.CONCLUSION. The article discusses ways to organize the measuring and control channels of the measuring and information system of the research stand, which makes it possible to study samples of asynchronous electric motors in idling and under load modes.

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Jeong, Kil-Hyun. "The Implementation of DDC for the WLAN Receiver." Journal of the Korea Society of Computer and Information 17, no. 2 (2012): 113–18. http://dx.doi.org/10.9708/jksci.2012.17.2.113.

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Deng, Jun, Hua Yong Tan, Lun Cai Liu, and Lin Tao Liu. "Research of a Mixed-Signal Programmable SoC Based on FPAA." Applied Mechanics and Materials 556-562 (May 2014): 1741–44. http://dx.doi.org/10.4028/www.scientific.net/amm.556-562.1741.

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This paper presents a novel architecture for mixed-signal SoC, which integrates a Field Programmable Analog Array (FPAA) into a SoC based on 32-bit RISC CPU. The FPAA unit can be configured as Filter, Comparator, Gain Amplifier, and so on. The proposed mixed-signal SoC can transform the intermediate frequency (IF) analog signal to baseband digital signal and realize the real-time baseband signal processing, besides this, which can transmit the modulated IF signals which are converted from baseband signals by digital up-conversion (DUC). The proposed mixed-signal SoC is a transceiver on chip actually, due to the internal integrated IPs, such as ADC, DAC, DDC and DUC, which can provide smaller board area, lower power consumption and the system cost for the product development of transceiver. This design will have a good potential for wireless communication applications.

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Tsvetkov, A. N., V. Yu Kornilov, A. R. Safin, A. G. Logacheva, T. I. Petrov, and N. E. Kuvshinov. "Control measuring and information system of the experimental stand." Power engineering: research, equipment, technology 22, no. 4 (2020): 88–98. http://dx.doi.org/10.30724/1998-9903-2020-22-4-88-98.

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Modern trends in the development of technology are based on the need for experimental studies of the equipment being developed in laboratory conditions with the maximum approximation of the operating modes to real ones. Such studies are impossible without the development of specialized stands with test automation systems. Automation of processes involves the organization of measuring channels as part of a stand using analog-to-digital conversion (ADC), digital-to-analog conversion (DAC), digital-todigital conversion (DDC) and the development of a hardware-software complex (HSC) based on high-speed computing devices. As part of the project to create new high-tech equipment, the specialists of FSBEI HE “KSPEU” and JSC “ChEAZ” developed and created an experimental stand designed to verify and confirm the correctness of the selected structural and circuit solutions used in the design of a synchronous valve electric motor (SVEM) and rod control station borehole pumping unit (RC SBPU). The object of experimental research was the prototype and prototype electric drives of oil pumping units, as well as their components: SVEM and RC SBPU. The article discusses the ways of organizing the measuring and control channels of the measuring and information system of the experimental bench, which allows to study samples of synchronous valve motors and control stations of the sucker rod pump unit in the regimes that are as close as possible to real field conditions simulating the operation of the oil pumping unit of the sucker rod pump unit. Thus, in the experimental stand, analog, discrete and digital control and control channels are implemented.

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He, Hong, De Peng Sha, and Hong Sun. "The SIMULINK Modeling and FPGA Realization of Digital down Converter." Advanced Materials Research 186 (January 2011): 131–35. http://dx.doi.org/10.4028/www.scientific.net/amr.186.131.

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Digital down converter is the core technology of soft radio receiver. It lets the high-speed-sampled digital signals down-conversion to base band down and then are decimated and high-passed filtered. This paper puts the main emphasis on analyzing the modeling and simulation by SIMULINK of digital mixing converter part and CIC decimation filter part of digital down converter and the realization on FPGA. It has been showed by the results that the problem that the operational pressure is too big to DSP and much too wide bandwidth gose against the channel separation when processing digital signal directly after A/D sampler has been solved well by digital down converter and decimating to reduce unnecessary data.

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Sokolov, Kirill Yu, Vladimir S. Priputin, and Elizaveta O. Lobova. "Implementation of Cosine Modulated Digital Filter Bank on Processor with ARM Architecture." T-Comm 14, no. 11 (2020): 57–63. http://dx.doi.org/10.36724/2072-8735-2020-14-11-57-63.

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This paper presents a class of multichannel cosine-modulated filter banks (CMFB) of analysis based on the modulation effect with a fast discrete-cosine transformation of the fourth type (DCT-IV), which is calculated using the fast Fourier transform. As a prototype filter, a low-frequency filter with a finite pulse characteristic was used, frequency-shifted copies of which were made using an effective technology for polyphase representation of the filter Bank. The comparison of the number of arithmetic operations performed by digital down converter (DDC) based on cascade integral-comb (CIC) and CMFB based on different number of channels is given. A software description of the CMFB algorithm is presented in the form of block diagrams describing the capabilities of the Opencl and clfft software libraries for implementing the DCT-IV filter Bank and modulation algorithm on a GPU. The obtained algorithm was tested on an ARM family processor and a mali GPU with a table with sample rate for different number of channels with the maximum load of the graphics processor (GPU) and the minimum load of the Central processor (CPU).

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Obradovic, Vuk, Predrag Okiljevic, Nadica Kozic, and Dejan Ivkovic. "Practical implementation of digital down conversion for wideband direction finder on FPGA." Scientific Technical Review 66, no. 4 (2016): 40–46. http://dx.doi.org/10.5937/str1604040o.

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Xu, Liuzhu, Di Peng, Yuwen Qin, et al. "Image-Rejected Multi-Band Frequency Down-Conversion Based on Photonic Sampling." Photonics 10, no. 1 (2022): 35. http://dx.doi.org/10.3390/photonics10010035.

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An image-rejected multi-band frequency down-conversion scheme is proposed and experimentally demonstrated based on photonic sampling. The multi-band radio-frequency (RF) signals to be processed are copied into two replicas in quadrature, which are then sampled by an ultra-short optical pulse train via a polarization-multiplexed modulator. After polarization demultiplexing and detection using a pair of low-speed photodetectors, the multi-band RF signals are simultaneously down-converted to the intermediate frequency (IF) band. The image components can be suppressed by quadrature coupling the two generated IF signals via an electrical 90° hybrid coupler (HC). In the experiment, multi-band RF signals in the frequency range of 6 GHz to 39 GHz are down-converted to the IF band below 4 GHz using a local oscillator (LO) signal at 8 GHz to generate the ultra-short optical pulse train. Image rejection is achieved in the digital domain using digital signal processing to compensate for the amplitude and phase mismatch between the two IF signals and to implement quadrature coupling. In addition, through using an electrical phase shifter, an electrical attenuator, and an electrical 90° HC to achieve quadrature coupling of the two IF signals, image-rejected multi-band frequency down-conversion is also verified in the analog domain.

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Panda, Amiya Ranjan, Debahuti Mishra, and Hare Krishna Ratha. "A Software Defined Radio based UHF Digital Ground Receiver System for Flying Object using LabVIEW." Defence Science Journal 67, no. 3 (2017): 291. http://dx.doi.org/10.14429/dsj.67.10365.

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This study demonstrates the design and implementation of a software defined radio based digital ground receiver system using LabVIEW. In flight testing centre, command transmission system is used to transmit specific commands to execute some operation inside the flight vehicle. One ground receiver system is needed to monitor the transmitted command and monitor the presence of the command in air. The newly implemented ground receiver system consists of FPGA, RTOS and general processing unit. The analog to digital conversion and RF down conversions are carried out in high speed PCI extension for instrumentation express cards. The communication algorithms, digital down conversion are implemented in FPGAs. The communication system uses digital demodulation and decoding scheme and realised by NI PXI-7966R with Xilinx Virtex 5, SXT, FPGA. The performance of the receiver system has been analysed by linearity measurement of pre-amplifier Gain, Noise figure, frequency, power and also measurement of sensitivity. The results show successful implementation of the ground receiver system.

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Karklinsh, V. "The “up-and-down” method with a variable step in digital sampling conversion." Automatic Control and Computer Sciences 46, no. 1 (2012): 34–40. http://dx.doi.org/10.3103/s0146411612010051.

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Pal, Soma, and Azazul Haque. "A review: algorithm used for beam forming systems." International Journal of Engineering & Technology 7, no. 1.2 (2017): 58. http://dx.doi.org/10.14419/ijet.v7i1.2.8991.

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Wireless communication uses a smart antenna to provide better coverage and capacity for the communication system. Main functions performed by the smart antenna are Direction of Arrival estimation (DOA) and beamforming (DBF). The beam forming is signal processing techniques which combine antenna array technology with high-performance up/down-conversion, analog to digital conversion and digital signal processing to provide receivers with very high spatial selectivity. This paper evaluates non-blind algorithm such as LMS, to compute the weight calculation for phased array antenna using Matlab Simulink.

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Deguchi, Mitsuyasu, Yukihiro Kida, Yoshitaka Watanabe, and Takuya Shimura. "Application of adaptive digital down-conversion to underwater acoustic communication with nonuniform Doppler shift." Japanese Journal of Applied Physics 59, SK (2020): SKKF02. http://dx.doi.org/10.35848/1347-4065/ab80db.

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Yang, Nie, Ge Hua, Jing Li-li, and Zhao Peng-yu. "Model-Based Design Methodology for Digital Up and Down Conversion of Software Defined Radio." International Journal of Multimedia and Ubiquitous Engineering 11, no. 4 (2016): 27–36. http://dx.doi.org/10.14257/ijmue.2016.11.4.04.

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Kou, Zhengchang, and Michael L. Oelze. "Implementation of real-time high-speed ultrasound communications through tissue." Journal of the Acoustical Society of America 151, no. 4 (2022): A245. http://dx.doi.org/10.1121/10.0011208.

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In this work, we propose a novel implementation of both a transmitter and receiver with field programmable gate arrays (FPGAs) to achieve real-time continuous high-definition (HD) video transmission through tissue, which can enable HD and higher frame rate wireless capsule endoscopy. We used a Texas Instruments AFE58JD48EVM 16 channel analog front end (AFE) evaluation board as the receiver connected to a Xilinx ZCU106 Zynq Ultrascale MPSoC development board in which we implemented a digital down converter (DDC), OFDM demodulator, maximum ratio combiner and low-density parity-check (LDPC) decoder. For the transmitter, we used an Analog Devices EVAL-AD9166 vector signal generator evaluation board, which has a built-in 4.3 dBm output power amplifier as a transmitter connected to another ZCU106 development board in which we implemented a LDPC encoder, OFDM modulator and digital up converter (DUC). The modulated signal was transmitted through a tissue-mimicking abdominal phantom using a 2-mm microcrystal transducer and received with a Sonic Concepts IP103 64 channel phased array at a center frequency of 3.2 MHz. We achieved the continuous transmission of up to over[OML1] 6 Mbps error free payload data rate after LDPC decoder which is used to carry HD video streams through ultrasound.

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Liu, Yue, Taishan Mo, and Bin Wu. "A Dual-Mode Step-Down Converter with Automatic Mode Switch Circuit for System-on-Chip Applications." Electronics 12, no. 13 (2023): 2999. http://dx.doi.org/10.3390/electronics12132999.

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In this paper, a dual-mode step-down DC-DC converter with an automatic mode-switching circuit is implemented in a 28 nm digital CMOS process and embedded in an RF transceiver chip to power the digital part. The proposed automatic mode-switching circuit includes a frequency-voltage conversion circuit that is designed according to the principle of charge redistribution on capacitance. The converter can switch modes according to the load without external intervention. This converter, along with a PMU sequencer, can also provide a solution for low-power design for system-on-chip applications. The IC occupies a total die area of 0.378 mm2. The input voltage of the converter is 3.3 V, the output voltage is 1.05 V, and the maximum load current can reach 1 A. The converter shows a conversion efficiency of not less than 81% at a full load range and can achieve a peak conversion efficiency of 91% when the load current is 100 mA. The load range of the PWM mode is 1 A to 50 mA, and that of the PFM mode is 100 mA to 1 mA. The combination of zero-crossing detection circuitry and freewheel switches can reduce energy loss and eliminate additional electromagnetic interference.

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Hoffmann, C., and P. Russer. "A low-noise high dynamic-range time-domain EMI measurement system for CISPR Band E." Advances in Radio Science 9 (August 1, 2011): 309–15. http://dx.doi.org/10.5194/ars-9-309-2011.

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Abstract. In this paper, a broadband time-domain EMI measurement system for measurements from 9 kHz to 18 GHz is presented that allows for compliant EMI measurements in CISPR Band E. Combining ultra-fast analog-to-digital-conversion and real-time digital signal processing on a field-programmable-gate-array (FPGA) with ultra-broadband multi-stage down-conversion, scan times can be reduced by several orders of magnitude in comparison to a traditional heterodyne EMI-receiver. The ultra-low system noise floor of 6–8 dB and the real-time spectrogram allow for the characterisation of the time-behaviour of EMI near the noise floor. EMI measurements of electronic consumer devices and electric household appliances are presented.

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George, James T., and Elizabeth Elias. "Reconfigurable channel filtering and digital down conversion in optimal CSD space for software defined radio." AEU - International Journal of Electronics and Communications 68, no. 4 (2014): 312–21. http://dx.doi.org/10.1016/j.aeue.2013.09.013.

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Hidalgo-López, José A., José A. Sánchez-Durán, and Óscar Oballe-Peinado. "Reducing Measurement Time in Direct Interface Circuits for Resistive Sensor Readout." Sensors 20, no. 9 (2020): 2596. http://dx.doi.org/10.3390/s20092596.

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Direct Interface Circuits (DICs) carry out resistive sensor readings using a resistance-to-time-to-digital conversion without the need for analog-to-digital converters. The main advantage of this approach is the simplicity involved in designing a DIC, which only requires some additional resistors and a capacitor in order to perform the conversion. The main drawback is the time needed for this conversion, which is given by the sum of up to three capacitor charge times and their associated discharge times. This article presents a modification of the most widely used estimation method in a resistive DIC, which is known as the Two-Point Calibration Method (TPCM), in which a single additional programmable digital device pin in the DIC and one extra measurement in each discharge cycle, made without slowing down the cycle, allow charge times to be reduced more than 20-fold to values around 2 µs. The new method designed to achieve this reduction only penalizes relative errors with a small increase of between 0.2% and 0.3% for most values in the tested resistance range.

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Zheng, Zhou, Meng Yuan Li, and Wei Jiang Wang. "A High Efficient Baseband GNSS Signal Narrow Band Anti-Jamming Approach in Frequency Domain." Advanced Materials Research 926-930 (May 2014): 1857–60. http://dx.doi.org/10.4028/www.scientific.net/amr.926-930.1857.

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In order to reduce the burden of the calculation and the low frequency resolution of the tradition GNSS signal intermediate narrow band anti-jamming method, it introduces a high efficient approach of narrow band interference rejection based on baseband GNSS signal processing. After digital down conversion to baseband and down sampling to a low rate, the interference is removed in frequency domain. According to the theoretical analysis and simulation, it claims that the method can reduce the calculation and increase the detection resolution in frequency domain which will realize a high efficient interference rejection.

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Plocins, V. "The Effect of Inaccuracy of Digital-to-Analog Conversion on Properties of the Up-and-Down Method for Digital Signal Processing." Automatic Control and Computer Sciences 52, no. 4 (2018): 317–21. http://dx.doi.org/10.3103/s0146411618040090.

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Motta, Lucas Lui, Byron Alejandro Acuña Acurio, Nathália Figueiredo Tinoco Aniceto, and Luís Geraldo P. Meloni. "Design and implementation of a digital down/up conversion directly from/to RF channels in HDL." Integration 68 (September 2019): 30–37. http://dx.doi.org/10.1016/j.vlsi.2019.05.006.

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Rao, D. Govind, N. S. Murthy, and A. Vengadarajan. "Design and Implementation of Digital Beam Former Architecture for Phased Array Radar." International Journal of Systems Applications, Engineering & Development 16 (January 5, 2022): 9–13. http://dx.doi.org/10.46300/91015.2022.16.2.

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This paper deals with the design and implementation of a digital beam former architecture which is developed for 4/8/12/16 element phased array radar. This technique employs a very high performance FPGA to handle large no of parallel complex arithmetic operations including digital down conversion and filtering. A 3MHz echo signal riding on an IF carrier of 60 MHz is under sampled at 50 MHz and down converted digitally to bring the spectrum to echo signal baseband. After suitable decimation filtering, the I and Q channels are multiplied with Recursive Least Squares based optimized complex weights to form partial beams. The prototype architecture employs techniques of pipelining and parallelism to generate multiple beams simultaneously from a 16 element array within 1 μsec. This can be extended to several number of arrays. The critical components employed in this design are eight 16 bit 125 MS/s ADCs and a very high performance state of the art Xilinx FPGA device Virtex-5 FX 130T having several on-chip resources and 150 MHz clock generators.

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Mayank, Kaushik, J. S. Sidana, Kumar Shivendra, and P. M. Menghal. "Performance analysis of photonics-based RF transceiver for high-speed data transmission." i-manager’s Journal on Pattern Recognition 10, no. 1 (2023): 34. http://dx.doi.org/10.26634/jpr.10.1.19783.

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Current digital radar systems have limitations at higher frequencies, and a new approach is needed to be able to operate in different environments and at higher frequencies. Photonics offers a solution to these limitations. It has UltraWide Bandwidth (UWB) and high precision, which allows for the flexible generation of highly consistent Radio Frequencies (RF) signals and the accurate direct digitization of signals without down-conversion. This research proposes a novel Wavelength-Division Multiplexing (WDM)-based photonics link for a radar demonstrator. The proposed system uses a single pulsed laser as a source to design a transceiver for high-speed data transmission and reception. The system can generate tunable radar signals and their echoes, avoiding the up/down conversion of radio frequency and ensuring both high resolution and simulation-based operation. The proposed system has the potential to revolutionize radar technology by enabling high resolution that can operate at higher frequencies. The system is also scalable and can be easily adapted to different radar applications.

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