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1
Yang, Xuecan. "Approximate computing for embedded machine learning." Electronic Thesis or Diss., Institut polytechnique de Paris, 2021. http://www.theses.fr/2021IPPAT005.
Full textAbstract:
Les réseaux de neurones convolutifs (CNN) ont été largement utilisés dans de nombreux domaines tels que la reconnaissance d’image, le traitement vidéo et le traitement du langage naturel. Cependant, les CNN sont toujours gourmands en calculs et en ressources. Ils sont souvent limités par les performances et la mémoire limitées lorsqu’ils sont déployés sur des systèmes embarqués. Ce projet de recherche doctorale vise à proposer des CNNs à faibles besoins en ressources informatiques et en mémoire, qui sont plus adaptés aux systèmes embarqués. En plus de la revue de la littérature, trois méthodes pour accélérer les CNNs sont proposées : Selective Binarisation, Quad-Approx Networks et MinConv-Nets : La Selective Binarisation combine des couches avec différentes précisions dans les CNNs pour obtenir une vitesse et une précision acceptables. De plus, un accélérateur basé sur FPGA est proposé pour ces structures optimisées. Avec le PArameterized Clipping acTivation Function signé proposé (signed PACT), les CNN sont quantizées en 3 bits, puis le multiplicateur approximatif est utilisé pour construire un réseau sans perte les précisions de détection, appelé Quad-Approx Network. En plus de l’accélération, il est plus précieux que Quad-Approx montre que les CNN sont des systèmes de tolérance aux pannes, ce qui nous conduit à proposer les MinConvNets. MinConvNet est un ensemble de CNN sans multiplication dont la multiplication est remplacée par une opération approximative. MinConvNet peut obtenir une perte de prédiction négligeable par rapport aux réseaux de classification d’image exacte grâce à l’apprentissage par transfert, tandis que la multiplication difficile à mettre en oeuvre est remplacée par des opérations plus faciles à implémenter. D’une part, l’humain inaugure l’ère de l’intelligence artificielle. D’un autre côté, l’Internet des objets (IoT) nous facilite la vie. Ces travaux apportent des algorithmes intelligents plus complexes dans les appareils de périphérie et nous aident à créer l’ère de l’Internet des objets artificiel et intelligent (AIoT)<br>Convolutional Neural Networks (CNNs) have been extensively used in many fields such as image recognition, video processing, and naturallanguage processing. However, CNNs are still computational-intensive and resource-consuming. They are often constrained by the limit performanceand memory when deployed on embedded systems. This PhD research project aims at proposing CNNs which are more suitable for embedded systems withlow computing resources and memory requirements. Based on literature review, we propose three methods to accelerate the operation of neural networks : Selective Binarization, Quad-Approx Network and Min- ConvNets. Selective Binarization combines layers with different precisions in CNNs to achieve an acceptable speed and accuracy. As well an FPGA based hardware accelerator is proposed for these optimized structures. With the proposed signed PArameterized Clipping acTivation Function (signed PACT), the CNNs are quantized into 3 bits, and then a loss-less network is established by using approximate multiplier, which is named Quad-Approx Network. In addition to acceleration, what is more valuable is that Quad-Approx shows that CNNs are certain fault tolerance systems, which leads us to propose the MinConvNets. MinConvNet is a set of multiplication-less CNNs whose multiplications are replaced by approximate operations. MinConvNet can achieve negligible loss of prediction compared to exact image classification networks through transfer learning, meanwhile the multiplication which is more resource consuming to implement is replaced by easier implemented operations. Human is ushering the era of the artificial intelligence. In the meantime, the Internet of Things (IoT) makes our lives more convenient. These works bring more complex intelligent algorithms into the edge devices and helps us to create the era of Artificial intelligent Internet of Things (AIoT)
2
Legband, Neil (Neil Robert). "Domestically dextrous : embedded computing for senior housing." Thesis, Massachusetts Institute of Technology, 2013. http://hdl.handle.net/1721.1/79178.
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Thesis (M. Arch.)--Massachusetts Institute of Technology, Dept. of Architecture, 2013.<br>Cataloged from PDF version of thesis.<br>Includes bibliographical references (p. 122-123).<br>This thesis proposes a new home for the aging baby boomers. The US is about to see a massive influx in the elderly population, and the current model of housing the elderly is woefully unprepared. The boomer generation has lived in single family homes for decades, and will want to continue living in one. Current strategies for retrofitting homes for seniors, things like wheelchair ramps, stair lifts, grab bars, are remarkably ill-suited to properly accommodate the needs of the elderly. Incorporating embedded computation into the home will allow the elderly to maintain their independence, and live in an environment which accommodates their expanding and changing needs as they deteriorate both mentally and physically. The home will take an active role in monitoring the occupant, monitoring itself, adapting to the changing physical/mental dexterity of the occupants, as well as assisting with domestic activities. Given the varying degrees of complexity that exist at the interface between the systems required to perform these activities and traditional residential stick frame construction, a new type of home which integrates electronics while also altering typical programmatic definitions within the domestic space.<br>by Neil Legband.<br>M.Arch.
3
Lerner, Lee Wilmoth. "Trustworthy Embedded Computing for Cyber-Physical Control." Diss., Virginia Tech, 2015. http://hdl.handle.net/10919/51545.
Full textAbstract:
A cyber-physical controller (CPC) uses computing to control a physical process. Example CPCs can be found in self-driving automobiles, unmanned aerial vehicles, and other autonomous systems. They are also used in large-scale industrial control systems (ICSs) manufacturing and utility infrastructure. CPC operations rely on embedded systems having real-time, high-assurance interactions with physical processes. However, recent attacks like Stuxnet have demonstrated that CPC malware is not restricted to networks and general-purpose computers, rather embedded components are targeted as well. General-purpose computing and network approaches to security are failing to protect embedded controllers, which can have the direct effect of process disturbance or destruction. Moreover, as embedded systems increasingly grow in capability and find application in CPCs, embedded leaf node security is gaining priority.
This work develops a root-of-trust design architecture, which provides process resilience to cyber attacks on, or from, embedded controllers: the Trustworthy Autonomic Interface Guardian Architecture (TAIGA). We define five trust requirements for building a fine-grained trusted computing component. TAIGA satisfies all requirements and addresses all classes of CPC attacks using an approach distinguished by adding resilience to the embedded controller, rather than seeking to prevent attacks from ever reaching the controller. TAIGA provides an on-chip, digital, security version of classic mechanical interlocks. This last line of defense monitors all of the communications of a controller using configurable or external hardware that is inaccessible to the controller processor. The interface controller is synthesized from C code, formally analyzed, and permits run-time checked, authenticated updates to certain system parameters but not code. TAIGA overrides any controller actions that are inconsistent with system specifications, including prediction and preemption of latent malwares attempts to disrupt system stability and safety.
This material is based upon work supported by the National Science Foundation under Grant Number CNS-1222656. Any opinions, findings, and conclusions or recommendations expressed in this material are those of the authors and do not necessarily reflect the views of the National Science Foundation. We are grateful for donations from Xilinx, Inc. and support from the Georgia Tech Research Institute.<br>Ph. D.
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Alessi, Marco. "Spatial computing per dispositivi mobile ed embedded." Master's thesis, Alma Mater Studiorum - Università di Bologna, 2015. http://amslaurea.unibo.it/8618/.
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Questa tesi si focalizza sulle possibili tecnologie per realizzare comunicazioni opportunistiche fra dispositivi mobile ed embedded, con l'obiettivo di integrarle nel contesto di sistemi a larga scala situati, e con particolare riferimento al prototipo denominato "Magic Carpet". Vengono considerate in particolare le tecnologie WiFi ad-hoc e Bluetooth Low Energy su Android e Raspberry Pi.
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Colin, Alexei. "System Support for Intermittent Computing." Research Showcase @ CMU, 2018. http://repository.cmu.edu/dissertations/1156.
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Smart things, spaces, and structures are created by embedding computation into them. Embedded computers sense, compute, and communicate at the edge, closer to the physical rather than the cyber world. Not any computer can be embedded, because many deployment settings demand small size, long lifetime, and robustness to a harsh environment. .
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Lee, Dongwon. "High-performance computer system architectures for embedded computing." Diss., Georgia Institute of Technology, 2011. http://hdl.handle.net/1853/42766.
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The main objective of this thesis is to propose new methods for designing high-performance embedded computer system architectures. To achieve the goal, three major components - multi-core processing elements (PEs), DRAM main memory systems, and on/off-chip interconnection networks - in multi-processor embedded systems are examined in each section respectively.
The first section of this thesis presents architectural enhancements to graphics processing units (GPUs), one of the multi- or many-core PEs, for improving performance of embedded applications. An embedded application is first mapped onto GPUs to explore the design space, and then architectural enhancements to existing GPUs are proposed for improving throughput of the embedded application.
The second section proposes high-performance buffer mapping methods, which exploit useful features of DRAM main memory systems, in DSP multi-processor systems. The memory wall problem becomes increasingly severe in multiprocessor environments because of communication and synchronization overheads. To alleviate the memory wall problem, this section exploits bank concurrency and page mode access of DRAM main memory systems for increasing the performance of multiprocessor DSP systems.
The final section presents a network-centric Turbo decoder and network-centric FFT processors. In the era of multi-processor systems, an interconnection network is another performance bottleneck. To handle heavy communication traffic, this section applies a crossbar switch - one of the indirect networks - to the parallel Turbo decoder, and applies a mesh topology to the parallel FFT processors. When designing the mesh FFT processors, a very different approach is taken to improve performance; an optical fiber is used as a new interconnection medium.
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Suslowicz, Charles Eugene. "Secure Intermittent Computing: Precomputation and Implementation." Thesis, Virginia Tech, 2018. http://hdl.handle.net/10919/83376.
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This thesis explores the security of intermittent devices, embedded systems designed to retain their state across periods of power loss, for cases both when the device has an excess of available energy and when power loss is unavoidable. Existing work with intermittent systems has focused on the problems inherent to the intermittent paradigm and ignored the security implications of persistent state across periods of power loss. The security of these devices is closely linked to their unique operational characteristics and are addressed here in two studies. First, the presence of an energy harvester creates an opportunity to use excess energy, available when additional energy is harvested after the local energy reservoir is filled, to precompute security related operations. Precomputation powered by this excess energy can reduce the cost of expensive tasks during periods of energy scarcity, potentially enabling the use of expensive security operations on traditionally unsecured devices. Second, when energy is limited and intermittent operation is required, the secure storage of checkpoints is a necessity to protect against adversary manipulation of the system state. To examine the secure storage of checkpoints a protocol is implemented to ensure the integrity and authenticity of a device's checkpoints, and evaluated for its energy overhead and performance. The cost of properly ensuring the integrity and authenticity of these checkpoints is examined to identify the overhead necessary to execute intermittent operations in a secure manner. Taken together, these studies lay the groundwork for a comprehensive view of the current state of intermittent device security.<br>Master of Science
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Say, Fatih. "A Reconfigurable Computing Platform For Real Time Embedded Applications." Phd thesis, METU, 2011. http://etd.lib.metu.edu.tr/upload/12613628/index.pdf.
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Today&rsquo<br>s reconfigurable devices successfully combine &lsquo<br>reconfigurable computing machine&rsquo<br>paradigm and &lsquo<br>high degree of parallelism&rsquo<br>and hence reconfigurable computing emerged as a
promising alternative for computing-intensive applications. Despite its superior performance
and lower power consumption compared to general purpose computing using microprocessors,
reconfigurable computing comes with a cost of design complexity. This thesis aims to
reduce this complexity by providing a flexible and user friendly development environment to
application programmers in the form of a complete reconfigurable computing platform.
The proposed computing platform is specially designed for real time embedded applications
and supports true multitasking by using available run time partially reconfigurable architectures.
For this computing platform, we propose a novel hardware task model aiming to minimize
logic resource requirement and the overhead due to the reconfiguration of the device.
Based on this task model an optimal 2D surface partitioning strategy for managing the hardware
resource is presented. A mesh network-on-chip is designed to be used as the communication
environment for the hardware tasks and a runtime mapping technique is employed to
lower the communication overhead.
As the requirements of embedded systems are known prior to field operation, an oine design
flow is proposed for generating the associated bit-stream for the hardware tasks. Finally, an
online real time operating system scheduler is given to complete the necessary building blocks
of a reconfigurable computing platform suitable for real time computing-intensive embedded
applications.
In addition to providing a flexible development environment, the proposed computing platform
is shown to have better device utilization and reconfiguration time overhead compared
to existing studies.
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Sun, Eugene Yu-Ting. "A many-core software framework for embedded space computing." Thesis, Massachusetts Institute of Technology, 2013. http://hdl.handle.net/1721.1/85507.
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Thesis: M. Eng., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2013.<br>Cataloged from PDF version of thesis.<br>Includes bibliographical references (pages 66-67).<br>Space computing has long called for powerful yet power-efficient hardware for on-board computation. The emergence of many-core CPUs on a single die provides one potential solution. The development of processors like Maestro strives for the balance between computational power and energy efficiency. However, development in software has not kept up. Not a single dominant programming framework has emerged to allow developers to easily write applications to take advantage of the new multi-core paradigm. As a result, in NASA's technology roadmap, fault management, programmability, and energy management under the new multi-core paradigm have been listed as top challenges. The goal of this thesis is to develop a framework that streamlines programming for multi-core processors, in the form of a programming model and a C++ programming library. A 49-core Maestro Development Board (MDB) serves as the development and testing hardware platform. The framework's usability is tested through a software simulation of a vision-based crater recognition algorithm for a lunar lander. A parallel version of the algorithm is written under the framework and tested, and a performance gain of about 300%, using 21 Maestro cores, is observed over the RAD750. The uniqueness of this framework lies in the principle that task blocks, not CPU cores, are the fundamental abstraction for individual processes. Each task block is allocated an arbitrary number of CPUs, completes one task, and communicates with other task blocks through message passing. Fault tolerance, power management, and communication among task blocks are abstracted out so that programmers can concentrate on the implementation of the application. The resulting programming library provides developers with the right tools to design and test parallel programs, port serial versions of applications to their parallelized counterparts, and develop new parallel programs with ease.<br>by Eugene Yu-Ting Sun.<br>M. Eng.
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Ghosh, Anandaroop. "Energy Efficient Computing in FPGA Through Embedded RAM Blocks." Case Western Reserve University School of Graduate Studies / OhioLINK, 2013. http://rave.ohiolink.edu/etdc/view?acc_num=case1365198486.
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Ireland, David John, and n/a. "Realization of Dielectric Embedded Monopole Radiating Structures For Wireless Computing." Griffith University. School of Microelectronic Engineering, 2006. http://www4.gu.edu.au:8080/adt-root/public/adt-QGU20070117.175717.
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With the rapid of growth of wireless connectivity more demand is placed on the need for innovative technologies capable of satisfying increasing user demand and network capacity. Adaptive antennas systems or most commonly known as Smart Antennas are expected to be implemented in the next generation of wireless systems. Their implementation avails in dynamic adaptation to spatial and temporal conditions affecting the quality of communication, while offering tremendous flexibility to wireless providers. However one of the major challenges facing Smart Antenna technology is the inherent complexity of the antenna structure, associated control algorithm and implemented RF components possibly contributing to the delay of commercial interest. This thesis will present various adaptive antenna configurations that utilize an embedded dielectric in order to achieve significant size reduction and mechanical rigidity while maintaining favorable electromagnetic performance. In order to constrict the lateral ground plane dimension, a cylindrical shaped hollow ground skirt was attached to the antenna structures effectively compromising between effective beam forming in the azimuth plane and physical size. The complexity of these antenna structures requires a more contemporary design approach which involved computer modeling using a commercial available Finite Element software package and optimization using a developed generic Genetic Algorithm based optimization program. A dielectric embedded 7-element monopole array antenna featuring switched parasitic elements is presented and optimized for maximum vertically polarized gain in the horizontal plane, producing an antenna structure with a radial length of less then 0.25λ and total height of 0.4&alamba which was shown to radiate a main lobe beamwidth of 80 degrees with an absolute gain of 4.8dBi at 2.45GHz. Further on a dielectric embedded 7-element monopole array antenna featuring parasitic elements terminated with finite set of terminating reactive loads is presented with a radial length of less then 0.25&alambda and total height of 0.4&alambda. The antenna structure and reactive load combination were optimized for maximum horizontal gain producing a principal main lobe with a measured gain of 5.1dBi and beamwidth of 110 degrees at 2.48GHz. Finally it was shown single and dual radiation lobes maybe produced when active monopoles elements are placed eccentric in a circular shaped dielectric material. A circular array of elements embedded in a dielectric material was realized with measured gains of single and dual beam radiation at 2.45GHz was shown to be 5.18dBi and 3.65Bi respectively with corresponding beamwidths of 78.5 degrees and 53 degrees.
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Ferreira, Ronaldo Rodrigues. "The transactional HW/SW stack for fault tolerant embedded computing." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2015. http://hdl.handle.net/10183/114607.
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O desafio de implementar tolerância a falhas em sistemas embarcados advém das restrições físicas de ocupação de área, dissipação de potência e consumo de energia desses sistemas. A necessidade de otimizar essas três restrições de projeto concomitante à computação dentro dos requisitos de desempenho e de tempo-real cria um problema difícil de ser resolvido. Soluções clássicas de tolerância a falhas tais como redundância modular dupla e tripla não são factíveis devido ao alto custo em potência e a falta de um mecanismo para se recuperar erros. Apesar de algumas técnicas existentes reduzirem o overhead de potência e área, essas incorrem em alta degradação de desempenho e muitas vezes assumem um modelo de falhas que não é factível. Essa tese introduz a Pilha de HW/SW Transacional, ou simplesmente Pilha, para gerenciar de maneira eficiente as restrições de área, potência, cobertura de falhas e desempenho. A Pilha introduz uma nova estratégia de compilação que organiza os programas em Blocos Básicos Transacionais (BBT), juntamente com um novo processador, a Arquitetura de Blocos Básicos Transacionais (ABBT), a qual provê detecção e recuperação de erros de grão fino e determinística ao usar o BBT como um contâiner de erros e como unidade de checkpointing. Duas soluções para prover a semântica de execução do BBT em hardware são propostas, uma baseada em software e a outra em hardware. A área, potência, desempenho e cobertura de falhas foram avaliadas através do modelo de hardware do ABBT. A Pilha provê uma cobertura de falhas de 99,35%, com overhead de 2,05 em potência e 2,65 de área. A Pilha apresenta overhead de desempenho de 1,33 e 1,54, dependento do modelo de hardware usado para suportar a semântica de execução do BBT.<br>Fault tolerance implementation in embedded systems is challenging because the physical constraints of area occupation, power dissipation, and energy consumption of these systems. The need for optimizing these three physical constraints while doing computation within the available performance goals and real-time deadlines creates a conundrum that is hard to solve. Classical fault tolerance solutions such as triple and dual modular redundancy are not feasible due to their high power overhead or lack of efficient and deterministic error recovery. Existing techniques, although some of them reduce the power and area overhead, incur heavy perfor- mance penalties and most of the time do not assume a feasible fault model. This dissertation introduces the Transactional HW/SW Stack, or simply Stack, to effi- ciently manage the area, power, fault coverage, and performance conundrum. The Stack introduces a new compilation strategy that assembles programs into Transac- tional Basic Blocks, together with a novel microprocessor, the TransactiOnal Basic Block Architecture (ToBBA), which provides fine-grained error detection and deter- ministic error rollback and elimination using the Transactional Basic Blocks (TBBs) both as a container for errors and as a small unit of data checkpointing. Two so- lutions to sustain the TBB semantics in hardware are introduced: software- and hardware-based. Stack’s area, power, performance, and coverage were evaluated using ToBBA’s hardware implementation model. The Stack attains an error correc- tion coverage of 99.35% with 2.05 power overhead within an area overhead of 2.65. The Stack also presents a performance overhead of 1.33 or 1.54, depending on the hardware model adopted to support the TBB.
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Ireland, David John. "Realization of Dielectric Embedded Monopole Radiating Structures For Wireless Computing." Thesis, Griffith University, 2006. http://hdl.handle.net/10072/367819.
Full textAbstract:
With the rapid of growth of wireless connectivity more demand is placed on the need for innovative technologies capable of satisfying increasing user demand and network capacity. Adaptive antennas systems or most commonly known as Smart Antennas are expected to be implemented in the next generation of wireless systems. Their implementation avails in dynamic adaptation to spatial and temporal conditions affecting the quality of communication, while offering tremendous flexibility to wireless providers. However one of the major challenges facing Smart Antenna technology is the inherent complexity of the antenna structure, associated control algorithm and implemented RF components possibly contributing to the delay of commercial interest. This thesis will present various adaptive antenna configurations that utilize an embedded dielectric in order to achieve significant size reduction and mechanical rigidity while maintaining favorable electromagnetic performance. In order to constrict the lateral ground plane dimension, a cylindrical shaped hollow ground skirt was attached to the antenna structures effectively compromising between effective beam forming in the azimuth plane and physical size. The complexity of these antenna structures requires a more contemporary design approach which involved computer modeling using a commercial available Finite Element software package and optimization using a developed generic Genetic Algorithm based optimization program. A dielectric embedded 7-element monopole array antenna featuring switched parasitic elements is presented and optimized for maximum vertically polarized gain in the horizontal plane, producing an antenna structure with a radial length of less then 0.25λ and total height of 0.4&alamba which was shown to radiate a main lobe beamwidth of 80 degrees with an absolute gain of 4.8dBi at 2.45GHz. Further on a dielectric embedded 7-element monopole array antenna featuring parasitic elements terminated with finite set of terminating reactive loads is presented with a radial length of less then 0.25&alambda and total height of 0.4&alambda. The antenna structure and reactive load combination were optimized for maximum horizontal gain producing a principal main lobe with a measured gain of 5.1dBi and beamwidth of 110 degrees at 2.48GHz. Finally it was shown single and dual radiation lobes maybe produced when active monopoles elements are placed eccentric in a circular shaped dielectric material. A circular array of elements embedded in a dielectric material was realized with measured gains of single and dual beam radiation at 2.45GHz was shown to be 5.18dBi and 3.65Bi respectively with corresponding beamwidths of 78.5 degrees and 53 degrees.<br>Thesis (Masters)<br>Master of Philosophy (MPhil)<br>School of Microelectronic Engineering<br>Full Text
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Harkin, James. "Hardware software partitioning : a reconfigurable and evolutionary computing approach." Thesis, University of Ulster, 2001. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.274414.
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Rivoli, Domenico. "Ubiquitous Computing: Una Panoramica." Bachelor's thesis, Alma Mater Studiorum - Università di Bologna, 2017.
Find full textAbstract:
Con questo documento voglio introdurre il lettore al concetto ingegneristico di Ubiquitous Computing. Partendo da un'analisi dei suoi connotati generali, verrà tracciato un percorso che tratterà nel dettaglio i vari aspetti collegati alle componentistiche hardware e di connettività, fino ad approfondire le metodologie e i dettagli collegati all'apparato di progettazione dei sistemi. Infine verrà discussa la parte applicativa ponendo l'enfasi su alcuni casi di studio correlati a Internet of Things, il quale è per molti aspetti profondamente connesso a Ubiquitous Computing.
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Joven, Murillo Jaume. "HW-SW components for parallel embedded computing on Noc-based MPSoCs." Doctoral thesis, Universitat Autònoma de Barcelona, 2010. http://hdl.handle.net/10803/5779.
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Recentment, en el camp del sistemes encastats, estem assistint al creixement de sistemes Multi-Processor System-on-Chip (MPSoC). El paradigma de Network-on-chip (NoC) s'ha proposat una solució viable, eficient, escalable, predictible i flexible per connectar components dins un xip, o inclús sistemes complets basats en busos dins al xip amb la finalitat de crear sistemes altament complexos. Així, el paradigma de computació encastada d'altres prestacions està arribant a través d'integrar hardware altament paral·lel amb llibreries software per obtenir una màxima integració a nivell de plataforma utilitzant de components prèviament dissenyats (IP cores), en la forma de arquitectures NoC-based MPSoCs. No obstant, quan el nombre de components augmenta hi ha diversos desafiaments i problemes a resoldre. <br/>El primer repte és el disseny d'una xarxa d'interconnexió que proporcioni qualitat de servei assegurant un cert ample de banda i latència entre cada bloc del sistema, amb el mínim area i consum possible. Ja que l'espai de disseny en arquitectures NoCs és enorme, s'han de desenvolupar entorns de simulació, i verificació per explorar validar i optimitzar múltiples NoC arquitectures. <br/>El segon objectiu, que és actualment un forat de recerca, és proveir models de programació paral·lela flexibles i eficients sobre les arquitectures NoC-based MPSoCs. Així, és obligatori l'ús de llibreries software lleugeres capaces d'explotar la capacitats del hardware present a la plataforma d'execució. Fent servir aquestes llibreries software permetrà els programadors reutilitzar i programar de manera fàcil aplicacions paral·leles dins un xip. <br/>Finalment, per obtenir un sistema eficient, un punt clau és el disseny de les interfícies HW-SW apropiades. Aquest fet és crucial in multi processadors heterogenis on els paradigmes de programació paral·lela and middleware han d'abstreure els recursos de comunicació durant l'especificació d'aplicacions software. <br/>El principal objectiu d'aquesta tesis és enriquir les emergents arquitectures NoC-based MPSoC explorant i fent contribucions de caire científic afrontant els nous reptes apareguts aquest últims anys. Aquesta tesis es focalitza en els següents temes: <br/>Descripció of un entorn experimental anomenat NoCMaker per realitzar exploració arquitectural de sistemes NoC-based MPSoC, permetent alhora una validació i prototipatge ràpid. <br/>Extensió de les interfícies de xarxa per controlar tràfic heterogeni de diferents estàndards (AMBA AHB, OCP-IP) amb la finalitat de reutilitzar i comunicar de manera transparent múltiple IP cores des del punt de vista de l'usuari. <br/>Proporcionar qualitat de servei en temps d'execució a traves de components hardware a la NoC, i de rutines middleware en software. <br/>Exploració de les interfícies HW-SW i la compartició de recursos quan una unitat de punt flotant es connecta com a coprocessador a un sistema NoC-based MPSoC. <br/>Migració de paradigmes de programació paral·lela, com memòria compartida i pas de missatges en arquitectures NoC-based MPSoCs. En aquesta tesis presentem el desenvolupament d'un model de programació paral·lela basat en pas de missatges (MPI), anomenat on-chip MPI. Això permet el disseny de programes paral·leles distribuïts a nivell de tasca o funció fent servir la programació paral·lela explicita amb els mètodes de sincronia entre els elements integrats en el xip. <br/>Proporcionant qualitat de servei en temps d'execució a sobre d'una llibreria OpenMP dissenyada per sistemes de memòria compartida amb la finalitat d'accelerar o balancejar aplicacions critiques i fils d'execució durant la seva execució. <br/>Tots els reptes explorats durant aquesta tesi doctoral estan formalitzats en una metodologia hardware-software centrada en la infraestructura de comunicació de la plataforma. Així, el resultat d'aquest treball d'investigació serà una plataforma cluster-on-chip per una computació paral·lela encastada d'altes prestacions, on els components hardware and software poden ser reutilitzats a diverses nivells d'abstracció.<br>Recently, on the on-chip and embedded domain, we are witnessing the growing of the Multi-Processor System-on-Chip (MPSoC) era. Network-on-chip (NoCs) have been proposed to be a viable, efficient, scalable, predictable and flexible solution to interconnect IP blocks on a chip, or full-featured bus-based systems in order to create highly complex systems. Thus, the paradigm to high-performance embedded computing is arriving through high hardware parallelism and concurrent software stacks to achieve maximum system platform composability and flexibility using pre-designed IP cores. These are the emerging NoC-based MPSoCs architectures. However, as the number of IP cores on a single chip increases exponentially, many new challenges arise. <br/>The first challenge is the design of a suitable hardware interconnection to provide adequate Quality of Service (QoS) ensuring certain bandwidth and latency bounds for inter-block communication, but at a minimal power and area costs. Due to the huge NoC design space, simulation and verification environments must be put in place to explore, validate and optimize many different NoC architectures. <br/>The second target, nowadays a hot topic, is to provide efficient and flexible parallel programming models upon new generation of highly parallel NoC-based MPSoCs. Thus, it is mandatory the use of lightweight SW libraries which are able to exploit hardware features present on the execution platform. Using these software stacks and their associated APIs according to a specific parallel programming model will let software application designers to reuse and program parallel applications effortlessly at higher levels of abstraction. <br/>Finally, to get an efficient overall system behaviour, a key research challenge is the design of suitable HW/SW interfaces. Specially, it is crucial in heterogeneous multiprocessor systems where parallel programming models and middleware functions must abstract the communication resources during high level specification of software applications. <br/>Thus, the main goal of this dissertation is to enrich the emerging NoC-based MPSoCs by exploring and adding engineering and scientific contribution to new challenges appeared in the last years. This dissertation focuses on all of the above points: <br/>by describing an experimental environment to design NoC-based systems, xENoC, and a NoC design space exploration tool named NoCMaker. This framework leads to a rapid prototyping and validation of NoC-based MPSoCs. <br/>by extending Network Interfaces (NIs) to handle heterogeneous traffic from different bus¬based standards (e.g. AMBA, OCP-IP) in order to reuse and communicate a great variety off-the-shelf IP cores and software stacks in a transparent way from the user point of view. <br/>by providing runtime QoS features (best effort and guaranteed services) through NoC-level hardware components and software middleware routines. <br/>by exploring HW/SW interfaces and resource sharing when a Floating Point Unit (FPU) co¬processor is interfaced on a NoC-based MPSoC. <br/>by porting parallel programming models, such as shared memory or message passing models on NoC-based MPSoCs. We present the implementation of an efficient lightweight parallel programming model based on Message Passing Interface (MPI), called on-chip Message Passing Interface (ocMPI). It enables the design of parallel distributed computing at task-level or function-level using explicit parallelism and synchronization methods between the cores integrated on the chip. <br/>by provide runtime application to packets QoS support on top of the OpenMP runtime library targeted for shared memory MPSoCs in order to boost or balance critical applications or threads during its execution. <br/>The key challenges explored in this dissertation are formalized on HW-SW communication centric platform-based design methodology. Thus, the outcome of this work will be a robust cluster-on-chip platform for high-performance embedded computing, whereby hardware and software components can be reused at multiple levels of design abstraction.
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Kwok, Tai-on Tyrone. "High performance embedded reconfigurable computing data security and media processing applications /." Click to view the E-thesis via HKUTO, 2005. http://sunzi.lib.hku.hk/hkuto/record/B3204043X.
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Kim, Se Hun. "Accuracy-energy tradeoffs in digital image processing using embedded computing platforms." Diss., Georgia Institute of Technology, 2011. http://hdl.handle.net/1853/42881.
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As more and more multimedia applications are integrated in mobile devices, a significant amount of energy is devoted to digital signal processing (DSP). Thus, reducing energy consumption for DSP systems has become an important design goal for battery operated mobile devices. Since supply voltage scaling is one of the most effective methods to reduce power/energy consumption, this study examines aggressive voltage scaling to achieve significant energy savings by allowing some output quality degradation for error tolerant image processing system. The objective of proposed research is to explore ultra-low energy image processing system design methodologies based on efficient accuracy (quality)-energy tradeoffs.
This dissertation presents several new analyses and techniques to achieve significant energy savings without noticeable quality degradation under aggressive voltage scaling. In the first, this work starts from accurate error analysis and a model based on input sequence dependent delay estimation. Based on the analysis, we explain the dependence of voltage scalability on input image types, which may be used for input dependent adaptive control for optimal accuracy-energy tradeoffs. In addition, this work includes the system-level analysis of the impact of aggressive voltage scaling on overall energy consumption and a low-cost technique to reduce overall energy consumption. Lastly, this research exploits an error concealment technique to improve the efficiency of accuracy-energy tradeoffs. For an image compression system, the technique minimizes the impact of delay errors on output quality while allowing very low voltage operations for significant energy reduction.
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Kwok, Tai-on Tyrone, and 郭泰安. "High performance embedded reconfigurable computing: data security and media processing applications." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 2005. http://hub.hku.hk/bib/B3204043X.
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Pham, Hung-Manh. "Embedded computing architecture with dynamic hardware reconfiguration for intelligent automotive systems." Rennes 1, 2007. http://www.theses.fr/2010REN1S139.
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L’omniprésence des calculateurs électroniques a conduit l’industrie automobile à faire face à de nouvelles exigences de sécurité et de performances pour intégrer les nouvelles applications du domaine. Il est maintenant reconnu que les circuits logiques reconfigurables répondent aux exigences de performances de traitement, de flexibilité et aux tendances industrielles sur la réduction du coût du produit. Nous démontrons dans cette thèse l’intérêt des nouvelles architectures reconfigurable dynamiquement dans le domaine de l’automobile et plus généralement dans le domaine de la sûreté de fonctionnement. L’utilisation de calculateurs reconfigurables dynamiquement permet de réduire le nombre de calculateurs et de diminuer les coûts de mise en œuvre. Malheureusement ces architectures sont très sensibles aux radiations et donc aux erreurs. Nous proposons, dans ce travail, des mécanismes de tolérances aux fautes faibles coûts pour palier à ce problème. En réalisant une détection de fautes sur les calculateurs reconfigurables et en la couplant avec un mécanisme de migration des tâches (matérielles et logicielles), il est alors possible d’augmenter de façon significative la robustesse du système, tout en conservant des performances optimales<br>The omnipresence of electronic computers has led the automotive industry to face new security and performance requirements to integrate new applications in the field. The modern reconfigurable logic circuits meet now the requirements of processing performance, flexibility and industry trends on reducing product cost. We show in this thesis the importance of new dynamically reconfigurable architectures in the automotive field and more generally in the area of dependability. The use of dynamically reconfigurable computers can reduce the number of computers and reduce the costs of implementation. Unfortunately, these architectures are very sensitive to radiation and therefore to errors. We propose in this work, low cost fault-tolerant mechanisms to solve this problem. By performing a fault detection on reconfigurable computers and coupling it with a mechanism of tasks migration (hardware and software), then it is possible to significantly increase the robustness of the system, while maintaining high degree of performance
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Tagliavini, Giuseppe <1980>. "Optimization Techniques for Parallel Programming of Embedded Many-Core Computing Platforms." Doctoral thesis, Alma Mater Studiorum - Università di Bologna, 2017. http://amsdottorato.unibo.it/8068/1/TESI.pdf.
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Nowadays many-core computing platforms are widely adopted as a viable solution to accelerate compute-intensive workloads at different scales, from low-cost devices to HPC nodes. It is well established that heterogeneous platforms including a general-purpose host processor and a parallel programmable accelerator have the potential to dramatically increase the peak performance/Watt of computing architectures. However the adoption of these platforms further complicates application development, whereas it is widely acknowledged that software development is a critical activity for the platform design. The introduction of parallel architectures raises the need for programming paradigms capable of effectively leveraging an increasing number of processors, from two to thousands. In this scenario the study of optimization techniques to program parallel accelerators is paramount for two main objectives: first, improving performance and energy efficiency of the platform, which are key metrics for both embedded and HPC systems; second, enforcing software engineering practices with the aim to guarantee code quality and reduce software costs. This thesis presents a set of techniques that have been studied and designed to achieve these objectives overcoming the current state-of-the-art.
As a first contribution, we discuss the use of OpenMP tasking as a general-purpose programming model to support the execution of diverse workloads, and we introduce a set of runtime-level techniques
to support fine-grain tasks on high-end many-core accelerators (devices with a power consumption greater than 10W). Then we focus our attention on embedded computer vision (CV), with the aim to show how to achieve best performance by exploiting the characteristics of a specific application domain. To further reduce the power consumption of parallel accelerators beyond the current technological limits, we describe an approach based on the principles of approximate computing, which implies modification to the program semantics and proper hardware support at the architectural level.
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Santhana, Krishnan Archanaa. "Top-down Approach To Securing Intermittent Embedded Systems." Diss., Virginia Tech, 2021. http://hdl.handle.net/10919/105128.
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The conventional computing techniques are based on the assumption of a near constant source of input power. While this assumption is reasonable for high-end devices such as servers and mobile phones, it does not always hold in embedded devices. An increasing number of Internet of Things (IoTs) is powered by intermittent power supplies which harvest energy from ambient resources, such as vibrations. While the energy harvesters provide energy autonomy, they introduce uncertainty in input power. Intermittent computing techniques were proposed as a coping mechanism to ensure forward progress even with frequent power loss. They utilize non-volatile memory to store a snapshot of the system state as a checkpoint. The conventional security mechanisms do not always hold in intermittent computing. This research takes a top-down approach to design secure intermittent systems. To that end, we identify security threats, design a secure intermittent system, optimize its performance, and evaluate our design using embedded benchmarks. First, we identify vulnerabilities that arise from checkpoints and demonstrates potential attacks that exploit the same. Then, we identify the minimum security requirements for protecting intermittent computing and propose a generic protocol to satisfy the same. We then propose different security levels to configure checkpoint security based on application needs.
We realize configurable intermittent security to optimize our generic secure intermittent computing protocol to reduce the overhead of introducing security to intermittent computing. Finally, we study the role of application in intermittent computing and study the various factors that affect the forward progress of applications in secure intermittent systems. This research highlights that power loss is a threat vector even in embedded devices, establishes the foundation for security in intermittent computing.<br>Doctor of Philosophy<br>The embedded systems are present in every aspect of life. They are available in watches, mobile phones, tablets, servers, health aids, home security, and other everyday useful technology. To meet the demand for powering up a rising number of embedded devices, energy harvesters emerged as a solution to provide an autonomous solution to power on low-power devices. With energy autonomy, came energy scarcity that introduced intermittent computing, where embedded systems operate intermittently because of lack of constant input power. The intermittent systems store snapshots of their progress as checkpoints in non-volatile memory and restore the checkpoints to resume progress. On the whole, the intermittent system is an emerging area of research that is being deployed in critical locations such as bridge health monitoring. This research is focused on securing intermittent systems comprehensively. We perform a top-down analysis to identify threats, mitigate them, optimize the mitigation techniques, and evaluate the implementation to arrive at secure intermittent systems. We identify security vulnerabilities that arise from checkpoints to demonstrate the weakness in intermittent systems. To mitigate the identified vulnerabilities, we propose secure intermittent solutions to protect intermittent systems using a generic protocol.
Based on the implementation of the generic protocol and its performance, we propose several optimizations based on the needs of the application to securing intermittent systems. And finally, we benchmark the security properties using two-way relation between security and application in intermittent systems. With this research, we create a foundation for designing secure intermittent systems.
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Leon, Santiago Andres. "A Self-Reconfiguring Platform For Embedded Systems." Thesis, Virginia Tech, 2001. http://hdl.handle.net/10919/34725.
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The JBits Application Programming Interface has significantly shortened FPGA reconfiguration times by manipulating the configurable resources of the FPGAs directly under software control. The execution of JBits programs, however, requires a Java Virtual Machine to be implemented on the platform where the configurations will be modified. This presents a problem for embedded systems where a microprocessor to run a Java Virtual Machine may not be available or desirable. This thesis discusses the implementation of a FPGA platform that allows the execution of JBits programs, effectively changing the configuration of a FPGA within a FPGA. This thesis also presents a four step developing and testing strategy for JBits programs that are intended to run on this FPGA platform.<br>Master of Science
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Dugani, Vishwanath. "Continuous system-wide profiling of High Performance Computing parallel applications : Profiling high performance applications." Thesis, KTH, Parallelldatorcentrum, PDC, 2016. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-224926.
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Profiling of an application identifies parts of the code being executed using the hardware performance counters thus providing the application’s performance. Profiling has long been standard in the development process focused on a single execution of a single program. As computing systems have evolved, understanding the bigger picture across multiple machines has become increasingly important. As supercomputing grows in pervasiveness and scale, understanding parallel applications performance and utilization characteristics is critically important, because even minor performance improvements translate into large cost savings. The study surveys various tools for the application. After which, Perfminer was integrated in SCANIA’s Linux clusters to profile CFD and FEA applications exploiting the batch queue system features for continuous system wide profiling, which provides performance insights for high performance applications, with negligible overhead. Perfminer provides stable, accurate profiles and a cluster-scale tool for performance analysis. Perfminer effectively highlights the micro-architectural bottlenecks.<br>Profilering av en ansökan identifierar delar av koden exekveras med hjälp av hårdvara prestandaräknare därmed ger programmets prestanda. Profilering har länge varit standard i utvecklingsprocessen fokuserad på en enda exekvering av ett enda program. Som datorsystem har utvecklats, att förstå helheten på flera datorer har blivit allt viktigare. Som superdatorer växer i genomslagskraft och skala, är förståelsen parallella applikationer prestanda och användningsegenskaper avgörande betydelse, eftersom även prestandaförbättringar mindre översätta till stora kostnadsbesparingar. Studien granskar olika verktyg för tillämpningen. Därefter var Perfminer integrerat i Scanias Linux-kluster att profilera CFD och FEA-program som utnyttjar sats kösystem funktioner för kontinuerlig hela systemet profilering, vilket ger prestanda insikter för högpresterande tillämpningar, med försumbar overhead. Perfminer ger stabila, noggranna profiler och ett kluster skala verktyg för prestandaanalys. Perfminer belyser effektivt mikro arkitektoniska flaskhalsar.
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Koltes, Andreas. "Reconfigurable memory systems for embedded microprocessors." Thesis, University of Cambridge, 2015. https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.709244.
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Rajović, Nikola. "Enabling the use of embedded and mobile technologies for high-performance computing." Doctoral thesis, Universitat Politècnica de Catalunya, 2017. http://hdl.handle.net/10803/461184.
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In the late 1990s, powerful economic forces led to the adoption of commodity desktop processors in High-Performance Computing(HPC). This transformation has been so effective that the November 2016 TOP500 list is still dominated by x86 architecture.
In 2016, the largest commodity market in computing is not PCs or servers, but mobile computing, comprising smartphones andtablets, most of which are built with ARM-based Systems on Chips (SoC). This suggests that once mobile SoCs deliver sufficient performance, mobile SoCs can help reduce the cost of HPC.
This thesis addresses this question in detail.We analyze the trend in mobile SoC performance, comparing it with the similar trend in the 1990s. Through development of real system prototypes and their performance analysis we assess the feasibility of building an HPCsystem based on mobile SoCs. Through simulation of the future mobile SoC, we identify the missing features and suggest improvements that would enable theuse of future mobile SoCs in HPC environment.
Thus, we present design guidelines for future generations mobile SoCs, and HPC systems built around them, enabling the newclass of cheap supercomputers.<br>A finales de la década de los 90, razones económicas llevaron a la adopción de procesadores de uso general en sistemas de Computación de Altas Prestaciones (HPC). Esta transformación ha sido tan efectiva que la lista TOP500 de noviembre de 2016 sigue aun dominada por la arquitectura x86. En 2016, el mayor mercado de productos básicos en computación no son los ordenadores de sobremesa o los servidores, sino la computación móvil, que incluye teléfonos inteligentes y tabletas, la mayoría de los cuales están construidos con sistemas en chip(SoC) de arquitectura ARM. Esto sugiere que una vez que los SoC móviles ofrezcan un rendimiento suficiente, podrán utilizarse para reducir el costo desistemas HPC. Esta tesis aborda esta cuestión en detalle. Analizamos la tendencia del rendimiento de los SoC para móvil, comparándola con la tendencia similar ocurrida en los añosnoventa. A través del desarrollo de prototipos de sistemas reales y su análisis de rendimiento, evaluamos la factibilidad de construir unsistema HPC basado en SoCs móviles. A través de la simulación de SoCs móviles futuros, identificamos las características que faltan y sugerimos mejoras quepermitirían su uso en entornos HPC. Por lo tanto, presentamos directrices de diseño para futuras generaciones de SoCs móviles y sistemas HPC construidos a sualrededor, para permitir la construcción de una nueva clase de supercomputadores de coste reducido.
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P, Joseph Iype. "Accelerating Java on Embedded GPU." Thèse, Université d'Ottawa / University of Ottawa, 2014. http://hdl.handle.net/10393/30684.
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Multicore CPUs (Central Processing Units) and GPUs (Graphics Processing Units) are omnipresent in today’s market-leading smartphones and tablets. With CPUs and GPUs getting more complex, maximizing hardware utilization is becoming problematic. The challenges faced in GPGPU (General Purpose computing using GPU) computing on embedded platforms are different from their desktop counterparts due to their memory and computational limitations. This thesis evaluates the performance and energy efficiency achieved by offloading Java applications to an embedded GPU. The existing solutions in literature address various techniques and benefits of offloading Java on desktop or server grade GPUs and not on embedded GPUs. Our research is focussed on providing a framework for accelerating Java programs on embedded GPUs. Our experiments were conducted on a Freescale i.MX6Q SabreLite board which encompasses a quad-core ARM Cortex A9 CPU and a Vivante GC 2000 GPU that supports the OpenCL 1.1 Embedded Profile. We successfully accelerated Java code and reduced energy consumption by employing two approaches, namely JNI-OpenCL, and JOCL, which is a popular Java-binding for OpenCL. These approaches can be easily implemented on other platforms by embedded Java programmers to exploit the computational power of GPUs. Our results show up to an 8 times increase in performance efficiency and 3 times decrease in energy consumption compared to the embedded CPU-only execution of Java program. To the best of our knowledge, this is the first work done on accelerating Java on an embedded GPU.
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Ortiz, Gual Fernando Enrique. "Novel reconfigurable computing architectures for embedded high performance signal processing and numerical applications." Access to citation, abstract and download form provided by ProQuest Information and Learning Company; downloadable PDF file 1.73 Mb., 102 p, 2006. http://gateway.proquest.com/openurl?url_ver=Z39.88-2004&res_dat=xri:pqdiss&rft_val_fmt=info:ofi/fmt:kev:mtx:dissertation&rft_dat=xri:pqdiss:3221141.
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Zhao, Ran. "Development tools for context aware and secure pervasive computing in embedded systems middleware." Thesis, University of Newcastle upon Tyne, 2013. http://hdl.handle.net/10443/2269.
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The increasing number of devices that are invisibly embedded into our surrounding environment as well as the proliferation of wireless communication and sensing technologies are the basis for visions like ambient intelligence, ubiquitous and pervasive computing. The PErvasive Computing in Embedded Systems (PECES) project developed the technological basis to enable the global cooperation of embedded devices residing in different smart spaces in a context-dependent, secure and trustworthy manner. The PECES development tools aim to help the application developer to build applications using the PECES middleware and simulate the smart space dynamics such as device connections and context changes, etc. To ease the middleware development process, the development tools are implemented as Eclipse plugins and integrated into the Eclipse Integrated Development Environment (IDE). The development tools provide graphical user interface (GUI) to configure, model and test the PECES middleware based smart space applications. This thesis presents the design, implementation and devaluation of three groups of tools namely Configuration Tool (Peces Project, Peces Device Definition, Peces Ontology Instantiation, Peces Security Configuration, Peces Service Definition, Peces Role Specification Definition, Peces Hierarchical Role Specification Definition), Modelling Tool (Peces Event Editor, Peces Event Diagram) and Testing Tool which enalble application developer to build, model and test the PECES middleware based smart space application using the novel concepts such as role assignment, context ontologies and security.
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Atashi, Hossein. "Low-Cost MemBIST for Micro-Controllers." Thesis, Norges teknisk-naturvitenskapelige universitet, Institutt for elektronikk og telekommunikasjon, 2012. http://urn.kb.se/resolve?urn=urn:nbn:no:ntnu:diva-18827.
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The challenge of testing SRAM memories consists in providing realistic fault models and test solutions with minimal application time. While classical memory tests cover the static faults, they are not sufficient to cover dynamic faults which have emerged in VDSM technologies. The purpose of this thesis is implementation of a memory BIST that targets static faults as well as dynamic faults while maintaining an acceptable test time and area overhead.At first, and as a semester project, the functional fault models (FFMs) associated with state-of-the-art SRAM technologies have been studied and state-of-the-art memory testing algorithms, targeting these FFMs have been presented.Next, and as part of this master's thesis, a combination of March LR and March AB memory testing algorithms is selected and modified to support testing word-oriented memories. Furthermore, this algorithm is extended to provide support for detecting Data-Retention Faults. This algorithm is then implemented using Verilog HDL in Register-Transfer Level of abstraction.The implemented MemBIST is then evaluated with respect to area, performance and fault coverage. A bit-oriented March LR-based MemBIST, currently in use on Atmel® AVR® micro-controllers, is used as a reference for benchmarking purposes. All target fault primitives (FPs) have been implemented using behavioral Verilog HDL and simulated with both MemBISTs.Our evaluations show that our word-oriented MemBIST can provide a 500% performance advantage (due to the word-oriented execution) for 32-bit memories and at the same time has a better fault coverage compared to the reference MemBIST. The implemented algorithm can detect all static and realistic dynamic inter-word memory faults as well as most static and realistic dynamic intra-word faults. The implemented MemBIST also maintains a very small area overhead due to sharing the required registers with existing system components.Keywords: MemBIST, Built-In Self Test, Memory Testing, March Test, Fault Model, Fault Coverage, Fault Detection
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Pluzhnikov, Sergey. "Motion Planning and Control of Robot Manipulators." Thesis, Norges teknisk-naturvitenskapelige universitet, Institutt for teknisk kybernetikk, 2012. http://urn.kb.se/resolve?urn=urn:nbn:no:ntnu:diva-18437.
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When a robot performs a task in an unstructured dynamic environment, it has to account for many factors. It should not only keep the track of where it is and how it should move, but also ensure that the kinematic, dynamic and task specific limitations are observed. It is also important that the robot can effectively avoid collisions with static and moving obstacles. In the current thesis we present design and implementation of an algorithm capable to face all these challenges. The system combines principles of dynamic roadmaps and elastic roadmaps frameworks, both of which are the state-of-art approaches to motion planning problem. The suggested solution is presented in the context of a broad overview of the literature in motion planning domain focusing on methodology of sample-based and feedback planning in dynamic environments. The implemented algorithm is applied to a 7-degree-of-freedom manipulator and is demonstrated and analyzed through a variety of simulated test scenarios. The result is an extensible and future-oriented planning system that can plan and execute movement between a starting and target position while preserving task constraints and reacting to environment changes in real time.
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YOUNES, HAMOUD. "Embedded Machine Learning: Emphasis on Hardware Accelerators and Approximate Computing for Tactile Data Processing." Doctoral thesis, Università degli studi di Genova, 2022. http://hdl.handle.net/11567/1069021.
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Machine Learning (ML) a subset of Artificial Intelligence (AI) is driving the industrial
and technological revolution of the present and future. We envision a world with smart
devices that are able to mimic human behavior (sense, process, and act) and perform
tasks that at one time we thought could only be carried out by humans. The vision
is to achieve such a level of intelligence with affordable, power-efficient, and fast hardware
platforms. However, embedding machine learning algorithms in many application domains
such as the internet of things (IoT), prostheses, robotics, and wearable devices is an ongoing
challenge. A challenge that is controlled by the computational complexity of ML algorithms,
the performance/availability of hardware platforms, and the application’s budget (power
constraint, real-time operation, etc.). In this dissertation, we focus on the design and
implementation of efficient ML algorithms to handle the aforementioned challenges. First, we
apply Approximate Computing Techniques (ACTs) to reduce the computational complexity of
ML algorithms. Then, we design custom Hardware Accelerators to improve the performance
of the implementation within a specified budget. Finally, a tactile data processing application
is adopted for the validation of the proposed exact and approximate embedded machine
learning accelerators.
The dissertation starts with the introduction of the various ML algorithms used for
tactile data processing. These algorithms are assessed in terms of their computational
complexity and the available hardware platforms which could be used for implementation.
Afterward, a survey on the existing approximate computing techniques and hardware
accelerators design methodologies is presented. Based on the findings of the survey, an
approach for applying algorithmic-level ACTs on machine learning algorithms is provided.
Then three novel hardware accelerators are proposed: (1) k-Nearest Neighbor (kNN) based
on a selection-based sorter, (2) Tensorial Support Vector Machine (TSVM) based on Shallow
Neural Networks, and (3) Hybrid Precision Binary Convolution Neural Network (BCNN).
The three accelerators offer a real-time classification with monumental reductions in the
hardware resources and power consumption compared to existing implementations targeting
the same tactile data processing application on FPGA. Moreover, the approximate accelerators
maintain a high classification accuracy with a loss of at most 5%.
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Siddiqui, Fahad Manzoor. "FPGA-based programmable embedded platform for image processing applications." Thesis, Queen's University Belfast, 2018. https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.766276.
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A vast majority of electronic systems including medical, surveillance and critical infrastructure employs image processing to provide intelligent analysis. They use onboard pre-processing to reduce data bandwidth and memory requirements before sending information to the central system. Field Programmable Gate Arrays (FPGAs) represent a strong platform as they permit reconfigurability and pipelining for streaming applications. However, rapid advances and changes in these application use cases crave adaptable hardware architectures that can process dynamic data workloads and be easily programmed to achieve ecient solutions in terms of area, time and power. FPGA-based development needs iterative design cycles, hardware synthesis and place-and-route times which are alien to the software developers. This work proposes an FPGA-based programmable hardware acceleration approach to reduce design effort and time. This allows developers to use FPGAs to profile, optimise and quickly prototype algorithms using a more familiar software-centric, edit-compile-run design flow that enables the programming of the platform by software rather than high-level synthesis (HLS) engineering principles. Central to the work has been the development of an optimised FPGA-based processor called Image Processing Processor (IPPro) which efficiently uses the underlying resources and presents a programmable environment to the programmer using a dataflow design principle. This gives superior performance when compared to competing alternatives. From this, a three-layered platform has been created which enables the realisation of parallel computing skeletons on FPGA which are used to eciently express designs in high-level programming languages. From bottom-up, these layers represent programming (actor, multiple actors and parallel skeletons) and hardware (IPPro core, multicore IPPro, system infrastructure) abstraction. The platform allows acceleration of parallel and non-parallel dataflow applications. A set of point and area image pre-processing functions are implemented on Avnet Zedboard platform which allows the evaluation of the performance. The point function achieved 2.53 times better performance than the area functions and point and area functions achieved performance improvements of 7.80 and 5.27 times over sin- gle core IPPro by exploiting data parallelism. The pipelined execution of multiple stages revealed that a dataflow graph can be decomposed into balanced actors to deliver maximum performance by hiding data transfer and processing time through exploiting task parallelism; otherwise, the maximum achievable performance is limited by the slowest actor due to the ripple effect caused by unbalanced actors. The platform delivered better performance in terms of fps/Watt/Area than Embedded Graphic Processing Unit (GPU) considering both technologies allows a software-centric design flow.
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Pouget, Kevin. "Programming-Model Centric Debugging for Multicore Embedded Systems." Thesis, Grenoble, 2014. http://www.theses.fr/2014GRENM008/document.
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Dans cette thèse, nous proposons d'étudier le débogage interactif d'applications pour les systèmes embarqués MPSoC (Multi-Processor System on Chip). Une étude de l'état de l'art a montrée que la conception et le développement de ces applications reposent de plus en plus souvent sur des modèles de programmation et des frameworks de développement. Ces environnements définissent les bonnes pratiques, tant au niveau algorithmique qu'au niveau des techniques de programmation. Ils améliorent ainsi le cycle de développement des applications destinées aux processeurs MPSoC. L'utilisation de modèles de programmation ne garantit cependant pas que les codes pourront être exécutés sans erreur, en particulier dans le cas de la programmation dynamique, où ils offrent très peu d'aide a la vérification. Notre contribution pour résoudre ces challenges consiste en une nouvelle approche pour le débogage interactif, appelée Programming Model-Centric Debugging, ainsi qu'une implémentation d'un prototype de débogueur. Le débogage centré sur les modèles rapproche le débogage interactif du niveau d'abstraction fourni par les modèles de programmation, en capturant et interprétant les évènements générés pendant l'exécution de l'application. Nous avons appliqué cette approche sur trois modèles de programmation, basés sur les composants logiciels, le dataflow et la programmation d'accélérateur par kernels. Ensuite, nous détaillons comment nous avons développé notre prototype de débogueur, basé sur GDB, pour la programmation de la plate-forme STHORM de STMicroelectronics. Nous montrons aussi comment aborder le débogage basé sur les modèles avec quatre études de cas : un code de réalité augmentée construit à l'aide de composants, une implémentation dataflow d'un décodeur vidéo H.264 et deux applications de calcul scientifique<br>In this thesis, we propose to study interactive debugging of applications running on embedded systems Multi-Processor System on Chip (MPSoC). A literature study showed that nowadays, the design and development of these applications rely more and more on programming models and development frameworks. These environments gather established algorithmic and programming good-practices, and hence speed up the development process of applications running on MPSoC processors. However, sound programming models are not always sufficient to reach or approach error-free codes, especially in the case of dynamic programming, where they offer little to no help. Our contribution to lighten these challenges consists in a novel approach for interac- tive debugging, named Programming Model-Centric Debugging, as well as a prototype debugger implementation. Model-centric debugging raises interactive debugging to the level of programming models, by capturing and interpreting events generated during the application execution (e.g. through breakpointed API function calls). We illustrate how we applied this approach to three different programming models, software components, dataflow and kernel-based programming. Then, we detail how we developed a debugger prototype based on GDB, for STMicroelectronics's STHORM programming environment. STHORM development toolkit provides supportive environments for component, dataflow and kernel-based programming. We also demonstrate how to tackle software debugging with our debugger prototype through four case studies: an augmented reality feature tacker built with components, a dataflow implementation of the H.264 video decoding standard and two scientific HPC computing applications
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Jeganathan, Nithyananda Siva. "A CONTROLLER AREA NETWORK LAYER FOR RECONFIGURABLE EMBEDDED SYSTEMS." UKnowledge, 2007. http://uknowledge.uky.edu/gradschool_theses/484.
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Dependable and Fault-tolerant computing is actively being pursued as a research area since the 1980s in various fields involving development of safety-critical applications. The ability of the system to provide reliable functional service as per its design is a key paradigm in dependable computing. For providing reliable service in fault-tolerant systems, dynamic reconfiguration has to be supported to enable recovery from errors (induced by faults) or graceful degradation in case of service failures. Reconfigurable Distributed applications provided a platform to develop fault-tolerant systems and these reconfigurable architectures requires an embedded network that is inherently fault-tolerant and capable of handling movement of tasks between nodes/processors within the system during dynamic reconfiguration. The embedded network should provide mechanisms for deterministic message transfer under faulty environments and support fault detection/isolation mechanisms within the network framework. This thesis describes the design, implementation and validation of an embedded networking layer using Controller Area Network (CAN) to support reconfigurable embedded systems.
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Seznec, Mickaël. "From the algorithm to the targets, optimization flow for high performance computing on embedded GPUs." Electronic Thesis or Diss., université Paris-Saclay, 2021. http://www.theses.fr/2021UPASG074.
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Les algorithmes de traitement numérique actuels nécessitent une puissance de calcul accrue pour obtenir des résultats plus précis et traiter des données plus volumineuses. Dans le même temps, les architectures matérielles se spécialisent, avec des accélérateurs très efficaces pour des tâches spécifiques. Dans ce contexte, le chemin du déploiement de l'algorithme à l'implémentation est de plus en plus complexe. Il est donc crucial de déterminer comment les algorithmes peuvent être modifiés pour tirer parti des capacités du matériel. Dans notre étude, nous nous sommes intéressé aux unités graphiques (GPU), un type de processeur massivement parallèle. Notre travail a consisté à l'adaptation entre l'algorithme et le matériel d'exécution. À l'échelle d'un opérateur mathématique, nous avons modifié un algorithme de convolution d'images pour utiliser les tensor cores et montré qu'on peut en doubler les performances pour de grands noyaux de convolution. Au niveau méthode, nous avons évalué des solveurs de systèmes linéaires pour l'estimation de flux optique afin de trouver le plus adéquat sur GPU. Grâce à ce choix et après de nouvelles optimisations spécifiques, comme la fusion d'itérations ou la réutilisation de zones mémoire, la méthode est deux fois plus rapide que l'implémentation initiale, fonctionnant à 60 images par seconde sur plateforme embarquée (30W). Enfin, nous avons également montré l'intérêt, dans le cadre des réseaux de neurones profonds, de cette méthode de conception d'algorithmes adaptée au matériel. Avec pour exemple l'hybridation entre un réseau conçu pour le flux optique avec une autre architecture préentrainée et conçue pour être efficace sur des cibles à faible puissance de calcul<br>Current digital processing algorithms require more computing power to achieve more accurate results and process larger data. In the meantime, hardware architectures are becoming more specialized, with highly efficient accelerators designed for specific tasks. In this context, the path of deployment from the algorithm to the implementation becomes increasingly complex. It is, therefore, crucial to determine how algorithms can be modified to take advantage of new hardware capabilities. Our study focused on graphics processing units (GPUs), a massively parallel processor. Our algorithmic work was done in the context of radio-astronomy or optical flow estimation and consisted of finding the best adaptation of the software to the hardware. At the level of a mathematical operator, we modified the traditional image convolution algorithm to use the matrix units and showed that its performance doubles for large convolution kernels. At a broader method level, we evaluated linear solvers for the combined local-global optical flow to find the most suitable one on GPU. With additional optimizations, such as iteration fusion or memory buffer re-utilization, the method is twice as fast as the initial implementation, running at 60 frames per second on an embedded platform (30 W). Finally, we also pointed out the interest of this hardware-aware algorithm design method in the context of deep neural networks. For that, we showed the hybridization of a convolutional neural network for optical flow estimation with a pre-trained image classification network, MobileNet, that was initially designed for efficient image classification on low-power platforms
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Jansen, Erwin. "Context-driven programming model for pervasive spaces." [Gainesville, Fla.] : University of Florida, 2005. http://purl.fcla.edu/fcla/etd/UFE0013044.
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Poli, Rossana. "Edge computing e Internet of Things per un sistema di allerta terremoti." Master's thesis, Alma Mater Studiorum - Università di Bologna, 2018. http://amslaurea.unibo.it/15406/.
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Al giorno d'oggi sono moltissimi i dispositivi che si collegano ad Internet, come computer, smartphone, tablet e console di giochi. A questi se ne sono aggiunti altri non convenzionali, come smartwatch, sensori biomedicali, automobili ed elettrodomestici intelligenti, in grado di interagire con gli utenti, generando e acquisendo informazioni dall'ambiente in cui sono situati. In quest'ottica si è sviluppato il concetto di Internet of Things (IoT), dove le cose comunicano direttamente o indirettamente con la rete Internet, in modo da gestire i grandi volumi di dati generati dai propri sensori e renderli accessibili mediante opportuni servizi Web e piattaforme appositamente progettate. Nell'ambito IoT, assume molta importanza l'architettura edge computing, nella quale i dati ottenuti vengono elaborati sul bordo della rete, cioè nei dispositivi, in modo da permetterne l'analisi in tempo reale. Il presente lavoro di tesi è stato sviluppato presso il CNAF (Centro Nazionale per la ricerca e lo sviluppo di tecnologie informatiche e telematiche, sito a Bologna) dell'Istituto Nazionale di Fisica Nucleare (INFN). Questo lavoro si inserisce nell'ambito del progetto COSA (Computing on SoC Architecture), che verte sullo studio delle architetture System-on-Chip low-power e delle loro
tecnologie al fine di utilizzarle nell'ambito della fisica e dell'informatica applicata. L'obiettivo di questo lavoro di tesi è quello di creare un sistema informatico che, utilizzando architetture embedded e low-power di tipo System-On-Chip dotate di sensori di accelerazione, raccoglie e analizza i dati al fine di rilevare un evento sismico e di notificarlo attraverso l'invio di una e-mail e la pubblicazione di un tweet su Twitter.
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Backhouse, Kevin Stuart. "Abstract interpretation of domain-specific embedded languages." Thesis, University of Oxford, 2002. http://ora.ox.ac.uk/objects/uuid:9138936a-145a-4e0e-9a59-f432f8c4e9d0.
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A domain-specific embedded language (DSEL) is a domain-specific programming language with no concrete syntax of its own. Defined as a set of combinators encapsulated in a module, it borrows the syntax and tools (such as type-checkers and compilers) of its host language; hence it is economical to design, introduce, and maintain. Unfortunately, this economy is counterbalanced by a lack of room for growth. DSELs cannot match sophisticated domain-specific languages that offer tools for domainspecific error-checking and optimisation. These tools are usually based on syntactic analyses, so they do not work on DSELs. Abstract interpretation is a technique ideally suited to the analysis of DSELs, due to its semantic, rather than syntactic, approach. It is based upon the observation that analysing a program is equivalent to evaluating it over an abstract semantic domain. The mathematical properties of the abstract domain are such that evaluation reduces to solving a mutually recursive set of equations. This dissertation shows how abstract interpretation can be applied to a DSEL by replacing it with an abstract implementation of the same interface; evaluating a program with the abstract implementation yields an analysis result, rather than an executable. The abstract interpretation of DSELs provides a foundation upon which to build sophisticated error-checking and optimisation tools. This is illustrated with three examples: an alphabet analyser for CSP, an ambiguity test for parser combinators, and a definedness test for attribute grammars. Of these, the ambiguity test for parser combinators is probably the most important example, due to the prominence of parser combinators and their rather conspicuous lack of support for the well-known LL(k) test. In this dissertation, DSELs and their signatures are encoded using the polymorphic lambda calculus. This allows the correctness of the abstract interpretation of DSELs to be proved using the parametricity theorem: safety is derived for free from the polymorphic type of a program. Crucially, parametricity also solves a problem commonly encountered by other analysis methods: it ensures the correctness of the approach in the presence of higher-order functions.
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Li, Jiayin. "ENERGY-AWARE OPTIMIZATION FOR EMBEDDED SYSTEMS WITH CHIP MULTIPROCESSOR AND PHASE-CHANGE MEMORY." UKnowledge, 2012. http://uknowledge.uky.edu/ece_etds/7.
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Over the last two decades, functions of the embedded systems have evolved from simple real-time control and monitoring to more complicated services. Embedded systems equipped with powerful chips can provide the performance that computationally demanding information processing applications need. However, due to the power issue, the easy way to gain increasing performance by scaling up chip frequencies is no longer feasible. Recently, low-power architecture designs have been the main trend in embedded system designs.
In this dissertation, we present our approaches to attack the energy-related issues in embedded system designs, such as thermal issues in the 3D chip multiprocessor (CMP), the endurance issue in the phase-change memory(PCM), the battery issue in the embedded system designs, the impact of inaccurate information in embedded system, and the cloud computing to move the workload to remote cloud computing facilities.
We propose a real-time constrained task scheduling method to reduce peak temperature on a 3D CMP, including an online 3D CMP temperature prediction model and a set of algorithm for scheduling tasks to different cores in order to minimize the peak temperature on chip. To address the challenging issues in applying PCM in embedded systems, we propose a PCM main memory optimization mechanism through the utilization of the scratch pad memory (SPM). Furthermore, we propose an MLC/SLC configuration optimization algorithm to enhance the efficiency of the hybrid DRAM + PCM memory. We also propose an energy-aware task scheduling algorithm for parallel computing in mobile systems powered by batteries.
When scheduling tasks in embedded systems, we make the scheduling decisions based on information, such as estimated execution time of tasks. Therefore, we design an evaluation method for impacts of inaccurate information on the resource allocation in embedded systems. Finally, in order to move workload from embedded systems to remote cloud computing facility, we present a resource optimization mechanism in heterogeneous federated multi-cloud systems. And we also propose two online dynamic algorithms for resource allocation and task scheduling. We consider the resource contention in the task scheduling.
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De, Guzman Ethan Paul Palisoc. "Energy Efficient Computing using Scalable General Purpose Analog Processors." DigitalCommons@CalPoly, 2021. https://digitalcommons.calpoly.edu/theses/2305.
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Due to fundamental physical limitations, conventional digital circuits have not been able to scale at the pace expected from Moore’s law. In addition, computationally intensive applications such as neural networks and computer vision demand large amounts of energy from digital circuits. As a result, energy efficient alternatives are needed in order to provide continued performance scaling. Analog circuits have many well known benefits: the ability to store more information onto a single wire and efficiently perform mathematical operations such as addition, subtraction, and differential equation solving. However, analog computing also comes with drawbacks such as its sensitivity to process variation and noise, limited scalability, programming difficulty, and poor compatibility with digital circuits and design tools. We propose to leverage the strengths of analog circuits and avoid its weaknesses by using digital circuits and time-encoded computation. Time-encoded circuits also operate on continuous data but are implemented using digital circuits. We propose a novel scalable general purpose analog processor using time-encoded circuits that is well suited for emerging applications that require high numeric precision. The processor’s datapath, including time-domain register file and function units are described. We evaluate our proposed approach using an implementation that is simulated with a 0.18µm TSMC process and demonstrate that this approach improves the performance of a scientific benchmark by 4x compared against conventional analog implementations and improves energy consumption by 146x compared against digital implementations.
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Rexroat, Jason T. "PROPOSED MIDDLEWARE SOLUTION FOR RESOURCE-CONSTRAINED DISTRIBUTED EMBEDDED NETWORKS." UKnowledge, 2014. http://uknowledge.uky.edu/ece_etds/63.
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The explosion in processing power of embedded systems has enabled distributed embedded networks to perform more complicated tasks. Middleware are sets of encapsulations of common and network/operating system-specific functionality into generic, reusable frameworks to manage such distributed networks. This thesis will survey and categorize popular middleware implementations into three adapted layers: host-infrastructure, distribution, and common services. This thesis will then apply a quantitative approach to grading and proposing a single middleware solution from all layers for two target platforms: CubeSats and autonomous unmanned aerial vehicles (UAVs). CubeSats are 10x10x10cm nanosatellites that are popular university-level space missions, and impose power and volume constraints. Autonomous UAVs are similarly-popular hobbyist-level vehicles that exhibit similar power and volume constraints. The MAVLink middleware from the host-infrastructure layer is proposed as the middleware to manage the distributed embedded networks powering these platforms in future projects. Finally, this thesis presents a performance analysis on MAVLink managing the ARM Cortex-M 32-bit processors that power the target platforms.
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翁楚灝 and Chor-ho Yung. "A mobile object container for dynamic component composition." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 2001. http://hub.hku.hk/bib/B31225573.
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Yung, Chor-ho. "A mobile object container for dynamic component composition." Hong Kong : University of Hong Kong, 2001. http://sunzi.lib.hku.hk/hkuto/record.jsp?B23234428.
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Wang, Xiaolong. "A Secure Computing Platform for Building Automation Using Microkernel-based Operating Systems." Scholar Commons, 2018. https://scholarcommons.usf.edu/etd/7589.
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Building Automation System (BAS) is a complex distributed control system that is widely deployed in commercial, residential, industrial buildings for monitoring and controlling mechanical/electrical equipment. Through increasing industrial and technological advances, the control components of BAS are becoming increasingly interconnected. Along with potential benefits, integration also introduces new attack vectors, which tremendous increases safety and security risks in the control system. Historically, BAS lacks security design and relies on physical isolation and "security through obscurity". These methods are unacceptable with the "smart building" technologies. The industry needs to reevaluate the safety and security of the current building automation system, and design a comprehensive solution to provide integrity, reliability, and confidentiality on both system and network levels.
This dissertation focuses on the system level in the effort to provide a reliable computing foundation for the devices and controllers. Leveraged on the preferred security features such as, robust modular design, small privilege code, and formal verifiability of microkernel architecture, this work describes a security enhanced operating system with built-in mandatory access control and a proxy-based communication framework for building automation controllers. This solution ensures policy-enforced communication and isolation between critical applications and non-critical applications in a potentially hostile cyber environment.
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SECCHI, SIMONE. "Simulating complex multi-core computing systems: techniques and tools." Doctoral thesis, Università degli Studi di Cagliari, 2011. http://hdl.handle.net/11584/266327.
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Fons, Lluís Francisco. "Embedded electronic systems driven by run-time reconfigurable hardware." Doctoral thesis, Universitat Rovira i Virgili, 2012. http://hdl.handle.net/10803/83494.
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Abstract
This doctoral thesis addresses the design of embedded electronic systems based on run-time reconfigurable hardware technology –available through SRAM-based FPGA/SoC devices– aimed at contributing to enhance the life quality of the human beings. This work does research on the conception of the system architecture and the reconfiguration engine that provides to the FPGA the capability of dynamic partial reconfiguration in order to synthesize, by means of hardware/software co-design, a given application partitioned in processing tasks which are multiplexed in time and space, optimizing thus its physical implementation –silicon area, processing time, complexity, flexibility, functional density, cost and power consumption– in comparison with other alternatives based on static hardware (MCU, DSP, GPU, ASSP, ASIC, etc.). The design flow of such technology is evaluated through the prototyping of several engineering applications (control systems, mathematical coprocessors, complex image processors, etc.), showing a high enough level of maturity for its exploitation in the industry.<br>Resumen
Esta tesis doctoral abarca el diseño de sistemas electrónicos embebidos basados en tecnología hardware dinámicamente reconfigurable –disponible a través de dispositivos lógicos programables SRAM FPGA/SoC– que contribuyan a la mejora de la calidad de vida de la sociedad. Se investiga la arquitectura del sistema y del motor de reconfiguración que proporcione a la FPGA la capacidad de reconfiguración dinámica parcial de sus recursos programables, con objeto de sintetizar, mediante codiseño hardware/software, una determinada aplicación particionada en tareas multiplexadas en tiempo y en espacio, optimizando así su implementación física –área de silicio, tiempo de procesado, complejidad, flexibilidad, densidad funcional, coste y potencia disipada– comparada con otras alternativas basadas en hardware estático (MCU, DSP, GPU, ASSP, ASIC, etc.). Se evalúa el flujo de diseño de dicha tecnología a través del prototipado de varias aplicaciones de ingeniería (sistemas de control, coprocesadores aritméticos, procesadores de imagen, etc.), evidenciando un nivel de madurez viable ya para su explotación en la industria.<br>Resum
Aquesta tesi doctoral està orientada al disseny de sistemes electrònics empotrats basats en tecnologia hardware dinàmicament reconfigurable –disponible mitjançant dispositius lògics programables SRAM FPGA/SoC– que contribueixin a la millora de la qualitat de vida de la societat. S’investiga l’arquitectura del sistema i del motor de reconfiguració que proporcioni a la FPGA la capacitat de reconfiguració dinàmica parcial dels seus recursos programables, amb l’objectiu de sintetitzar, mitjançant codisseny hardware/software, una determinada aplicació particionada en tasques multiplexades en temps i en espai, optimizant així la seva implementació física –àrea de silici, temps de processat, complexitat, flexibilitat, densitat funcional, cost i potència dissipada– comparada amb altres alternatives basades en hardware estàtic (MCU, DSP, GPU, ASSP, ASIC, etc.). S’evalúa el fluxe de disseny d’aquesta tecnologia a través del prototipat de varies aplicacions d’enginyeria (sistemes de control, coprocessadors aritmètics, processadors d’imatge, etc.), demostrant un nivell de maduresa viable ja per a la seva explotació a la indústria.
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Eise, Justin. "A Secure Architecture for Distributed Control of Turbine Engine Systems." University of Dayton / OhioLINK, 2019. http://rave.ohiolink.edu/etdc/view?acc_num=dayton1552556049435026.
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Santhana, Krishnan Archanaa. "Surplus and Scarce Energy: Designing and Optimizing Security for Energy Harvested Internet of Things." Thesis, Virginia Tech, 2018. http://hdl.handle.net/10919/83450.
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Internet of Things require a continuous power supply for longevity and energy harvesting from ambient sources enable sustainable operation of such embedded devices. Using selfpowered power supply gives raise two scenarios, where there is surplus or scarce harvested energy. In situations where the harvester is capable of harvesting beyond its storage capacity, the surplus energy is wasted. In situations where the harvester does not have sufficient resources, the sparse harvested energy can only transiently power the device. Transiently powered devices, referred to as intermittent computing devices, ensure forward progress by storing checkpoints of the device state at regular intervals. Irrespective of the availability of energy, the device should have adequate security.
This thesis addresses the security of energy harvested embedded devices in both energy scenarios. First, we propose precomputation, an optimization technique, that utilizes the surplus energy. We study two cryptographic applications, namely bulk encryption and true random number generation, and we show that precomputing improves energy efficiency and algorithm latency in both applications. Second, we analyze the security pitfalls in transiently powered devices. To secure transiently powered devices, we propose the Secure Intermittent Computing Protocol. The protocol provides continuity to underlying application, atomicity to protocol operations and detects replay and tampering of checkpoints. Both the proposals together provide comprehensive security to self-powered embedded devices.<br>Master of Science<br>Internet of Things(IoT) is a collection of interconnected devices which collects data from its surrounding environment. The data collected from these devices enable emerging technologies like smart home and smart cities, where objects are controlled remotely. With the increase in the number of such devices, there is a demand for self-powered devices to conserve electrical energy.
Energy harvesters are suitable for this purpose because they convert ambient energy into electrical energy to be stored in an energy buffer, which is to be used when required by the device. Using energy harvesters as power supply presents us with two scenarios. First, when there is sufficient ambient energy, the surplus energy, which is the energy harvested beyond the storage capacity of the buffer, is not consumed by the device and thus, wasted. Second, when the harvested energy is scarce, the device is forced to shutdown due to lack of power.
In this thesis, we consider the overall security of an energy harvested IoT device in both energy scenarios. We optimize cryptographic algorithms to utilize the surplus energy and design a secure protocol to protect the device when the energy is scarce. Utilizing both the ideas together provides adequate security to the Internet of Things.
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Gunupudi, Vandana. "Exploring Trusted Platform Module Capabilities: A Theoretical and Experimental Study." Thesis, University of North Texas, 2008. https://digital.library.unt.edu/ark:/67531/metadc6101/.
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Trusted platform modules (TPMs) are hardware modules that are bound to a computer's motherboard, that are being included in many desktops and laptops. Augmenting computers with these hardware modules adds powerful functionality in distributed settings, allowing us to reason about the security of these systems in new ways. In this dissertation, I study the functionality of TPMs from a theoretical as well as an experimental perspective. On the theoretical front, I leverage various features of TPMs to construct applications like random oracles that are impossible to implement in a standard model of computation. Apart from random oracles, I construct a new cryptographic primitive which is basically a non-interactive form of the standard cryptographic primitive of oblivious transfer. I apply this new primitive to secure mobile agent computations, where interaction between various entities is typically required to ensure security. I prove these constructions are secure using standard cryptographic techniques and assumptions. To test the practicability of these constructions and their applications, I performed an experimental study, both on an actual TPM and a software TPM simulator which has been enhanced to make it reflect timings from a real TPM. This allowed me to benchmark the performance of the applications and test the feasibility of the proposed extensions to standard TPMs. My tests also show that these constructions are practical.