Academic literature on the topic 'FPGA Spartan 3 development board'

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Journal articles on the topic "FPGA Spartan 3 development board"

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Kulesza, Zbigniew, and Zdzisław Gosiewski. "An FPGA Implementation of the Robust Controller for the Active Magnetic Bearing System." Solid State Phenomena 147-149 (January 2009): 399–409. http://dx.doi.org/10.4028/www.scientific.net/ssp.147-149.399.

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The article presents the project design flow that leads to the implementation of the robust controller law in the FPGA chip. The designed robust FPGA controller is going to be used in the heteropolar active magnetic bearing system. The hardware and software architectures of the designed controller are presented. The hardware consists of the market available Spartan-3 Development Board and two specially designed A/D and D/A converters boards. The software architecture is made of several VHDL entities that are translated into the target FPGA chip. The results of the experimental preliminary tests show that the dynamic properties of the designed controller are very good and the authors hope that the dynamic performance, especially the stability of the whole active magnetic bearing system, will improve.
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Barlian, Henryranu Prasetio, and Syauqy Dahnial. "Design of Digital to Analog Voice Data Packet Conversion from Ethernet Protocol using FPGA." TELKOMNIKA Telecommunication, Computing, Electronics and Control 15, no. 2 (2017): 646–53. https://doi.org/10.12928/TELKOMNIKA.v15i2.3612.

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This paper describes a system that is designed to be able to receive packet voice signal using the Ethernet protocol in local networks using FPGA which was programmed decode the data packets. The digital data packets are then converted back into analog data that will be used to control another system. The design was implemented as four components consisting of frame starter unit, address matching unit, buffer unit and DAC processing unit. The system was designed on Xilinx development board using ISE design suite and simulated on ISIM. The test results showed that the system response was less than 40 ms. The result also showed that our proposed design only occupies 11% of number of slices and it also requires 5% of total IOBs on Xilinx Spartan 3-E.
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Piyush, .A. Nitnaware, and A.P.Khandait Dr. "Fpga Based Soil Irrigation Robot." International Journal of Innovative Science and Research Technology 7, no. 6 (2022): 35–37. https://doi.org/10.5281/zenodo.6865146.

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The design of FPGA based soil irrigation robot is proposed. The soil moisture sensor senses the moisture level and gives output to the FPGA board. gives This board gives signal to motor drives which turn on the motor pump. The obstacle detection is done by using IR sensor. This simulation is done on Xilinx software with Spartan 3.
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Lei, Dong Ming, Ping Li, and Nian Yu Zou. "4PSK Signal Based on FPGA." Advanced Materials Research 694-697 (May 2013): 2870–73. http://dx.doi.org/10.4028/www.scientific.net/amr.694-697.2870.

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Based on the traditional demodulation method of four phase shift keying (QPSK), a QPSK demodulation model was proposed. The FPGA-based QPSK modulation and demodulation system and circuit had been achieved. In Xilinx ISE12.3 development environment, using the SPARTAN-3E development board, the simulation results demonstrate the feasibility of this design.
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Bespalov, Nikolay, and Yury Goryachkin. "Device for Current Test Pulse Development Through a Diode in a Direct Direction." International Journal of Engineering & Technology 7, no. 3.19 (2018): 81. http://dx.doi.org/10.14419/ijet.v7i3.19.16991.

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The article is devoted to the development of a device that allows to generate control current pulses to determine the current-voltage characteristic of diodes in the forward direction. To implement the device, we use NI Digital Electronics FPGA Board, which includes FPGA XC3S500E Xilinx Spartan-3E FPGA and the Linear Technology LTC2624 chip, containing four 12-bit DACs. We consider the creation of a software module via VHDL language that generates 12-bit digital code to create rectangular voltage control pulses with a successively increasing amplitude and transmitted via SPI interface as the part of 32-bit data transfer protocol, using Xilinx WebPACK ISE software.
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Petrovic, Miljan, and Milica Jovanovic. "Realization of universal periodic sequence generator on FPGA." Serbian Journal of Electrical Engineering 13, no. 1 (2016): 59–70. http://dx.doi.org/10.2298/sjee1601059p.

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This paper presents mathematical modeling and performance evaluation of different realizations of universal periodic digital signal generator based on infinite impulse response filter. The development kit used was Spartan 3E-Starter Board. Using Xilinx software environment and VHDL, the generator has been described and then synthesized and implemented on FPGA chip on the board. Included realizations are direct form II (canonical form) of the filter, as well as hardware optimized single register structure with different control mechanism. Comparative analysis of these two digital systems points to their differences, advantages and weaknesses.
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Yan, Ziqi. "The application of Verilog in the development of casual games." Applied and Computational Engineering 76, no. 1 (2024): 245–49. http://dx.doi.org/10.54254/2755-2721/76/20240600.

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Verilog is a hardware description language (HDL) that is widely used in digital circuit design and simulation. Its development is closely related to computer science and electrical engineering. Verilog gained popularity in the early 1980s as digital circuit designs became increasingly complex, requiring more efficient circuit design and verification tools. At the same time, rapid advances in computer hardware also stimulated the demand for digital circuit design languages. Furthermore, the popularity and adoption of Verilog highlight the growing necessity for digitisation, automation, and intelligence in modern society. As digital technology continues to advance across various industries, the need for effective and dependable digital circuit design languages is also increasing. This paper delves into the complex process of recreating the timeless arcade classic Pac-Man on the Spartan 3E FPGA platform using hardware description and digital circuit techniques and the Verilog programming language. Through a comprehensive review of existing literature and research, this study investigates the fusion of traditional game design principles with state-of-the-art hardware programming methods, demonstrating the seamless integration of software-driven game mechanics with hardware-based implementation. Through careful design and coding strategies, Pac-Man's basic functionality, such as maze traversal, ghost AI, and pellet consumption, is faithfully replicated using Verilog modules customized for the Spartan 3E FPGA board. By bridging the realms of game development and hardware engineering, this paper not only showcases the versatility of Field Programmable Gate Array (FPGA) technology in entertainment applications but also underscores the interdisciplinary nature of modern computing endeavours.
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Amar, Hebibi, Bartil Arres, and Ziet Lahcene. "Comparison of two new methods for implementa BPSK modulator using FPGA." Indonesian Journal of Electrical Engineering and Computer Science (IJEECS) 19, no. 2 (2020): 819–27. https://doi.org/10.11591/ijeecs.v19.i2.pp819-827.

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The design of electronic systems has become mainly dependent on FPGAs applications. This is due to the softness effectiveness progress by reconfigurable computing and reduced time to develop solutions for digital signal processing. In this article, we present the theoretical backgrounds of a BPSK modulation and hardware designs of the BPSK system, a firstly with the help of Matlab/Simulink reliant on the System Generator and a second with Xilinx ISE VERILOG Hardware Description Language. In order to show the differences between them, in terms of efficiency, duration of development and how many resources are used in FPGA. For the projected system, we have a tendency to aimed toward employing a moderately sized, low-value FPGA to implement the system. The Atlys development board by Digilent to configure develops, and run the system, based on a Xilinx Spartan-6 LX45 FPGA.
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Zulfikar, Zulfikar, Shuja A. Abbasi, and Abdul Rahman M. Alamoud. "FPGA Hardware Realization: Addition of Two Digital Signals Based on Walsh Transforms." International Journal of Electrical and Computer Engineering (IJECE) 6, no. 6 (2016): 2688. http://dx.doi.org/10.11591/ijece.v6i6.12040.

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<p>This paper presents hardware realization of addition of two digital signals based on Walsh transforms and inverse Walsh transforms targeted to the Xilinx FPGA Spartan 3 board. The realization utilizes Walsh Transform to convert the input data to frequency domain and the inverse Walsh transform to reconvert the data from frequency domain. The designed system is capable of performing addition, subtraction, multiplication and Arbitrary Waveform Generation (AWG). However, in the present work, the hardware realization of addition only has been demonstrated. The Clock frequency for realization into the board is supplied by an external function generator. Output results are captured using a logic analyzer. Input data to the board (system) is passed manually through the available slide switches on-board.</p>
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Amar, Hebibi, Arres Bartil, and Lahcene Ziet. "Comparison of two new methods for implementa BPSK modulator using FPGA." Indonesian Journal of Electrical Engineering and Computer Science 19, no. 2 (2020): 819. http://dx.doi.org/10.11591/ijeecs.v19.i2.pp819-827.

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<span>The design of electronic systems has become mainly dependent on FPGAs applications. This is due to the softness effectiveness progress by reconfigurable computing and reduced time to develop solutions for digital signal processing. In this article, we present the theoretical backgrounds of a BPSK modulation and hardware designs of the BPSK system, a firstly with the help of Matlab/Simulink reliant on the System Generator and a second with Xilinx ISE VERILOG Hardware Description Language. In order to show the differences between them, in terms of efficiency, duration of development and how many resources are used in FPGA. For the projected system, we have a tendency to aimed toward employing a moderately sized, low-value FPGA to implement the system. The Atlys development board by Digilent to configure develops, and run the system, based on a Xilinx Spartan-6 LX45 FPGA.</span>
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Dissertations / Theses on the topic "FPGA Spartan 3 development board"

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Lertlaokul, Kawin. "Virtual Partial Reconfiguration Framework for the Digilent Nexys 3 Board." 2019. https://monarch.qucosa.de/id/qucosa%3A35354.

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The modern embedded system is getting more complicated due to the functional requirements of the system are rapidly increasing. The modern system must have more reliable, as it deals with a lot of data. The distributed systems are used in variety technologies field due to it has more reliable than single control unit. It can transfer task to other processing unit when the one part of system failed while the single control unit failed cause the system to stop operate. The FPGA are being used increasingly in the distributed system due to the benefit of FPGA over microcontroller and ASIC. FPGA is flexible than ASIC due to the ability to reconfiguration its function. FPGA processes the data in parallel, therefore, it computes the data faster than the microcontroller that computes the data in concurrence. The flexibility of FPGA supports the development of reliable distributed system. When one of FPGA failed, the other FPGA can reconfiguration itself to operate on the task of the failed FPGA. The method to reconfigure the FPGA structure is a process of loading new bitstream file into FPGA. For generating variety configurations of distributed system. The developer must develop number of bitstream file according to number of reconfiguration designs. Although the FPGA is flexible and can reconfiguration anytime, the development process of configuration file is a redundancy workload. One FPGA design structure equals one configuration file. This project focus on reduce the redundancy workload, therefore, it can reduce the development time and make the development project launching faster. This virtual partial reconfiguration framework is developed to assist the developer in generating many configuration files without coding. The framework will determine all possible combination of modules and generates all combination design files. One set of the design contain the VHDL file and UCF file. The developer can use these files to synthesise in FPGA vendor development tool and generate bitstream. This virtual partial reconfiguration framework also provides the partial reconfiguration benefits except runtime reconfiguration.
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Liao, Yuan-Jhang, and 廖原樟. "Applications with the LC-3 Soft Core on an FPGA Development Board." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/92684427661491864251.

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碩士<br>國立雲林科技大學<br>電子與光電工程研究所碩士班<br>101<br>Assembly language is closest to the operation of the underlying computer hardware programming language. The benefits of learning assembly language can help programmers to grasp the characteristic and limitation of computer in order to develop more efficient programs. ARM and NIOSII are two of the most commonly used processors in embedded systems. So many people use ARM platform to learn assembly language and hardware architecture. However, there are many instructions in the instruction sets of ARM or NIOS II, which might be difficult for beginning students to learn. This study is about the design of a course on microprocessor using a soft processor LC-3 that runs on an FPGA platform called DE0 from Altera. I/O devices of DE0 board and Lego NXT devices can be driven by an LC-3 core. Student can use LC-3 assembly language to program their applications to control I/O devices. This should add more fun to learning assembly language programming and computer organization, and flatten the learning curve for students.
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Ρώσση, Μαρία-Ευγενία. "Διερεύνηση επιδόσεων αρχιτεκτονικών υλικού-λογισμικού για εφαρμογές ψηφιακής επεξεργασίας σε FPGA". Thesis, 2012. http://hdl.handle.net/10889/5394.

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Οι συστοιχίες προγραμματιζόμενων πυλών (FPGAs) αποτελούν μια σημαντική τεχνολογία, η οποία επιτρέπει στους σχεδιαστές κυκλωμάτων την παραγωγή συγκεκριμένου σκοπού ολοκληρωμένων κυκλωμάτων σε σύντομο χρόνο. Tα σημαντικότερα των χαρακτηριστικών τους είναι η αρχιτεκτονική τους και η δυνατότητα σχεδιασμού τους μέσω υπολογιστών, η χαμηλή κατανάλωση ισχύος καθώς και το μικρό χρονικό διάστημα που απαιτείται για τον επαναπρογραμματισμό τους. Τα FPGAs είναι κατάλληλα σχεδιασμένα για ψηφιακές εφαρμογές φιλτραρίσματος. Η πυκνότητα των προγραμματιζόμενων αυτών συστημάτων είναι τέτοια ώστε πολύ μεγάλος αριθμός αριθμητικών πράξεων όπως αυτές που προκύπτουν μέσω ψηφιακού φιλτραρίσματος να μπορεί να εφαρμοστεί σε μία μόνο συσκευή. Τα πλεονεκτήματα των FPGA στην υλοποίηση ψηφιακών φίλτρων είναι μεταξύ άλλων οι υψηλότεροι ρυθμοί δειγματοληψίας από παραδοσιακούς DSP chip, το χαμηλότερο κόστος από μια μέτρια ASIC (Application Specific Integrated Circuit, Kύκλωμα οριζόμενο από εφαρμογή) για εφαρμογές μεγάλου όγκου, καθώς και η μεγαλύτερη ευελιξία από όλες τις εναλλακτικές προσεγγίσεις για την υλοποίηση των FIR φίλτρων. Σπουδαιότερο όλων είναι ότι προγραμματίζονται μέσα στο σύστημα και έχουν δυνατότητα επαναπρογραμματισμού για την υλοποίηση διαφόρων εναλλακτικών λειτουργιών φιλτραρίσματος. Στόχος της παρούσας διπλωματικής είναι να συνδυασθούν τεχνικές VLSI και ψηφιακής επεξεργασίας σήματος και μέσω κατανόησης της αρχιτεκτονικής του υπολογιστή να δημιουργηθεί μια χρήσιμη εφαρμογή. Επιλέχθηκε για τον λόγο αυτό: α) η ανάπτυξη ενός FIR φίλτρου σε γλώσσα περιγραφής υλικού, β) υλοποίησή του σε FPGA, γ) εισαγωγή αυτού σε ενσωματωμένο σύστημα και σύνδεση σε διάδρομο δεδομένων επεξεργαστή και δ) έλεγχος του φίλτρου με τη βοήθεια του επεξεργαστή μέσω γλώσσας υψηλού επιπέδου. Η συγγραφή του κώδικα του φίλτρου έγινε σε γλώσσα VHDL, με structural μεθόδους και η προσομοίωση του συστήματος στο Modelsim. Επιπροσθέτως χρησιμοποιήθηκε ο Project Navigator ISE της Xilinx για τον έλεγχο του κώδικα αλλά και τον προγραμματισμό του FPGA Spartan 3E Starter Board. Χρησιμοποιήθηκαν ακόμα τα υποπρογράμματα Plan Ahead και ChipScope Pro του ISE ώστε να ελεγχθεί η λειτουργία του κυκλώματος στο FPGA. To κύκλωμα τελικά εισάγεται σε ενσωματωμένο σύστημα με τη βοήθεια του εργαλείου σχεδίασης EDK της Xilinx και ελέγχεται η λειτουργία του προγραμματίζοντας τον επεξεργαστή Microblaze. Ακόμα ελέγχεται η λειτουργία του φίλτρου για διαφορετικούς συντελεστές FIR φίλτρων που χρησιμοποιούν διαφορετικά παράθυρα και συγκρίνονται οι «ιδανικές» τιμές που παράγονται από το Matlab με αυτές που παράγονται από το φίλτρο. Τέλος μετράται η ενέργεια (δυναμική και στατική) που καταναλώνεται κατά τη λειτουργία του κυκλώματος στο FPGA με τη βοήθεια του XPower Analyzer.<br>Field-programmable gate arrays (FPGAs) is a technology of great importance that allows the designers to produce specific purpose integrated circuits in a limited amount of time. The most important of their characteristics are their architecture and the ability of their design with the help of computers, the low power dissipation, as well as the need of a short amount of time to be reprogrammed. FPGAs are properly designed for digital filtering applications. The density of these programmable systems is such that a great amount of numerical calculations such as those that result via digital filtering can be applied to one device only. The advantages of FPGAs as for the implementation of digital filters is between others the great rates of sampling compared to traditional DSP chips, their low cost compared to a moderate ASIC (Application Specific Integrated Circuit) for applications that take up a large area, as well as the flexibility compared to alternative approaches for the implementation of FIR filters. Their most important characteristic is that they can be programmed on-chip and that they have the ability of being reprogrammed for the implementation of different filtering purposes. The aim of this thesis is to combine VLSI techniques and digital signal processing techniques and via the understanding of the computer architecture to create a useful application. To fulfill that purpose: a) a FIR filter was designed with the use of a hardware description language b) the filter was implemented by using an FPGA c) the filter was imported to an embedded system and it was connected to the bus of a microprocessor d) the filter was controlled by the microprocessor via a high-level programming language. The filter was designed using the VHDL language, specifically using structural methods, and its simulation was performed with Modelsim. Also the Project Navigator ISE of Xilinx was used to correct unwanted warnings and to program the FPGA Spartan 3E Starter Board. Some other subprograms of ISE were also used, such as Plan Ahead and ChipScope Pro in order to check the performance of the filter. The circuit is finally imported to an embedded system using the Embedded Developer’s Kit (EDK) of Xilinx. Microblaze was the microprocessor that was used to control the filter’s performance. Additionally, the performance of the filter is checked by using different coefficients of FIR filters by different windowing methods. The ideal values that are produced from Matlab are compared to those of the filter. Finally the power dissipation (static and dynamic) of the filter is measured using XPower Analyzer.
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Book chapters on the topic "FPGA Spartan 3 development board"

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Liao, Yuan-Jhang, and Wing-Kwong Wong. "Using LC-3 Soft Core on an FPGA Development Board for Microprocessor Labs." In Intelligent Technologies and Engineering Systems. Springer New York, 2013. http://dx.doi.org/10.1007/978-1-4614-6747-2_71.

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Mañón Juárez, J. Brandon, and Eusebio Ricárdez Vázquez. "Implementation of a Digital Electromyographic Signal Processor Synthesized on an FPGA Development Board for Biocontrol Systems." In Advances in Soft Computing. Springer Nature Switzerland, 2023. http://dx.doi.org/10.1007/978-3-031-47640-2_15.

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Conference papers on the topic "FPGA Spartan 3 development board"

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Ekaputri, Cahyantari, and Arief Syaichu-Rohman. "Model predictive control (MPC) design and implementation using algorithm-3 on board SPARTAN 6 FPGA SP605 evaluation kit." In 2013 3rd International Conference on Instrumentation Control and Automation (ICA). IEEE, 2013. http://dx.doi.org/10.1109/ica.2013.6734056.

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Gogu, Dragos-Georgel, Călin-George Mihalache, Florin-Adrian Stancu, et al. "GMVISION: CO-PROCESSOR FOR COMPLEX VISION-BASED AUTONOMOUS NAVIGATION IN SPACE." In ESA 12th International Conference on Guidance Navigation and Control and 9th International Conference on Astrodynamics Tools and Techniques. ESA, 2023. http://dx.doi.org/10.5270/esa-gnc-icatt-2023-215.

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As current and future space exploration missions are getting bolder, so do the requirements on the navigation algorithms and subsequently on their implementation in the avionics modules and on the associated data interfaces. To achieve the high level of autonomy and reliability required in today’s space missions, vision-based navigation making use of high resolution images and processed on-board at high frame-rates is mandatory. The increased complexity of these computer vision algorithms and the data fusion of measurements acquired from various on-board instruments and sensors mandate the development and use of high-performance avionics to provide one or two order of magnitude faster execution than today's conventional space-grade processors. As consequence, nowadays substantial efforts are done to develop high frequency, high accuracy navigations systems, to improve on-board spacecraft power consumption and to optimize the processing times of the computational loads to achieve near real time operation. This paper focuses on the development of GMVision, a highly versatile space-oriented image processing unit that can provide interfacing SpaceWire control and management of up to 8 links and the opportunity for integrating computationally demanding image processing algorithms. The GMVision board can provide various redundant Vision-based Navigation solutions for autonomous operations in space missions, as GMV has previously developed within different ESA activities (CAMPHORVNAV, NEOGNC-2, Lunar-Lander, PILOTB+, HERA, HIPNOS, ORCO, NEOSHIELD, HERACLES or Mars Sample Return) several image processing algorithms and navigation filters based on autonomous relative or absolute navigation, suitable for rendezvous-search-capture, active debris removal and in-orbit servicing, descent and landing into small or massive bodies or to accommodate computer-vision solutions for rover exploration. From the mechanical point of view, GMVision fits inside an envelope of 16 cm x 28 cm x 5.9 cm (dimensions adjustable by re-design), and it can be provided as independent boards with metallic enclosure box accumulating a total mass of approximately 1.5 kg, or it can be provided as rackable electronics boards to integrate with an OBC. The image processing board can adapt to different redundancy concepts, depending on mission needs or system requirements. The GMVision system provides 2 boards isolation for Image Processing Function and Interfaces function, as it is relying on a two FPGAs architecture for each board. Both FPGAs are rad-hard European BRAVE units with allocated external volatile and non-volatile memories: an NG-MEDIUM dedicated to interfaces control unit and monitoring, and a powerful NG-LARGE to perform as computer vision co-processor, improving the execution times with 2 orders of magnitude compared to space processors. The image processing algorithms functionality can be divided between the processing FPGA and a SW processor, making use of a HW/SW co-design approach, as GMVision can be interfaced via SpaceWire with an On-board computer. This is the case for the two use-case scenarios for the development of GMVision Mars Sample Return mission concept Vision-Based GNC Rendezvous with ERO platform or Lunar lander with both absolute and relative navigation. The SpaceWire interfaces allow TM/TC exchange between GMVision and up to 3 devices/instruments using nominal and redundant Spacewire links (nominal/redundant 1 on-board computer and 2 navigation cameras or eventually 8 different components). The design and development of the computer-vision algorithms for GMVision are facilitated by the architectural design of the processing FPGA code, which provides an internal interfacing wrapper to integrate the required image processing module satisfying a client-consumer simple interface. GMVision board can also include pre-processing functions for the navigation cameras or other sensors, as well as managing the redundancy concept. The high performance, fast and complex computer vision solutions are focused on the needed processing, so both FPGAs of the board are SRAM reprogrammable devices which allow flexibility and many options for the design and implementation of complex functionalities, such as high-data rate interfaces management and hardware accelerators. Thanks to the reprogramming capabilities it can also be possible to accommodate different computer-vision accelerators which are not used in the same moment of time by replacing partially or fully bitstreams in the processing FPGA to save a potentially needed second FPGA unit. The GMVsion concept is promising technology and it has high exploitation applicability also to other missions, such as Lunar Missions with Roadmap as a Smart sensor. Being reference architecture for complex high performance algorithms, the product is a feasible solution for space-based surveillance system, or to the Mars exploration missions. Interconnected to a space processor, GMVision is the perfect avionics platform for integrating vision-based system for autonomous rover navigation, implemented in full HW or as a HW/SW co-design with most computationally intensive operations implemented in FPGA, and those requiring additional precision implemented on a space processor. The TRL to be achieved by the GMVision concept is 6, so the product has not been qualified for flight yet, being built with commercial components. Nevertheless, extensive analysis were performed in terms of analysis and shock, and tests at ambient conditions. The roadmap towards an actual flight model is deemed with high probability of success, as all the electronics components of the existent EM have space qualified counterparts, so the flight model shall be able to withstand the harsh space environment. In summary, the paper presents a highly versatile, fast and complex avionics development deemed as co-processor for space computer-vision applications. The features, performance and the evolution of the concept from breadboard model to engineering model, as well as the roadmap towards a powerful flight hardware are presented.
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Reports on the topic "FPGA Spartan 3 development board"

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Yang, Yu, Hen-Geul Yeh, and Cesar Ortiz. Battery Management System Development for Electric Vehicles and Fast Charging Infrastructure Improvement. Mineta Transportation Institute, 2024. http://dx.doi.org/10.31979/mti.2024.2325.

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The electric vehicle (EV) has become increasingly popular due to its being zero-emission. However, a significant challenge faced by EV drivers is the range anxiety associated with battery usage. Addressing this concern, this project develops a more efficient battery management system (BMS) for electric vehicles based on a real-time, state-of-charge (SOC) estimation. The proposed study delivers three modules: (1) a new equivalent circuit model (ECM) for lithium-ion batteries, (2) a new SOC estimator based on the moving horizon method, and (3) an on-board FPGA implementation of the classical Coulomb counting method for SOC estimation. The research team extends the traditional ECM by incorporating more functional features through the least absolute shrinkage and selection operator (LASSO). Then the first-order transfer function model identification and LASSO are iteratively executed to minimize the data fitting error. Given this model, the research team employs the moving horizon estimator (MHE) to determine the SOC by fitting the measured terminal voltage. Subsequently, the research team implements the SOC estimation scheme on an FPGA board. This hardware-in-the-loop simulation is demonstrated in this report step by step. The proposed research has broad societal impacts. It aligns with SB1 objectives in several ways. First, EVs with a more efficient BMS can improve their cruise range, reducing energy consumption and traffic congestion. Second, the resulting BMS can be applied in the solar-power and battery-assisted charging stations to make more reliable infrastructure in an age of sustainable transportation.
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