Academic literature on the topic 'Hybrid multilevel inverter'

This thesis investigates a novel DC/AC resonant inverter of Induction Heating (IH) system presenting a Multilevel Neutral Point Clamped (MNPCI) topology, as a new part of power supply design. The main function of the prototype is to provide a maximum and steady state power transfer from converter to the resonant load tank, by achieving zero current switching (ZCS) with selecting the best design of load tank topology, and utilizing the advantage aspects of both the Voltage Fed Inverter (VFI) and Current Fed Inverter (CFI) kinds, therefore it can considered as a hybrid-inverter (HVCFI) category . The new design benefits from series resonant inverter design through using two bulk voltage source capacitors to feed a constant voltage delivery to the MNPCI inverter with half the DC rail voltage to decrease the switching losses and mitigate the over voltage surge occurred in inverter switches during operation which may cause damage when dealing with high power systems. Besides, the design profits from the resonant load topology of parallel resonant inverter, through using the LLC resonant load tank. The design gives the advantage of having an output current gain value of about Quality Factor (Q) times the inverter current and absorbs the parasitic components. On the contrary, decreasing inverter current means decreasing the switching frequency and thus, decreasing the switching losses of the system. This aspect increases the output power, which increases the heating efficiency. In order for the proposed system to be more reliable and matches the characteristics of IH process , the prototype is modelled with a variable LLC topology instead of fixed load parameters with achieving soft switching mode of ZCS and zero voltage switching (ZVS) at all load conditions and a tiny phase shift angle between output current and voltage, which might be neglected. To achieve the goal of reducing harmonic distortion, a new harmonic control modulation is introduced, by controlling the ON switching time to obtain minimum Total Harmonic Distortion (THD) content accompanied with optimum power for heating energy.

CoordenaÃÃo de AperfeiÃoamento de Pessoal de NÃvel Superior<br>Este trabalho apresenta uma topologia de inversor multinÃvel hÃbrido simÃtrico trifÃsico de cinco nÃveis, concebido a partir das estruturas meia ponte e inversor com grampeamento ativo do neutro, adequado para aplicaÃÃes com alta tensÃo e alta potÃncia. SÃo apresentados os possÃveis estados de comutaÃÃo, lÃgica de acionamento, cÃlculo dos esforÃos nos semicondutores, assim como um estudo de perdas. Duas estratÃgias de modulaÃÃo sÃo selecionadas possibilitando a operaÃÃo concomitante de metade dos interruptores em baixa frequÃncia (60 Hz) e a outra em alta frequÃncia (1020 Hz), reduzindo o nÃmero de comutaÃÃes, consequentemente as perdas nos semicondutores e o conteÃdo harmÃnico da tensÃo de saÃda. Para validar a proposta, foi desenvolvido um protÃtipo com potÃncia de 7,5 kVA e tensÃo de saÃda eficaz de linha 380 V. AlÃm disso, à apresentada a implementaÃÃo de ambas as modulaÃÃes no dispositivo lÃgico programÃvel escolhido, FPGA. Os resultados experimentais da estrutura trifÃsica validam a topologia proposta. A estrutura, operando com a modulaÃÃo baseada na PD-PWM, apresentou DHT de 29,71% e WTHD de 1,93%, enquanto que a baseada na CSV-PWM apresentou DHT de 38,45% e WTHD de 7,21%. AlÃm disso, o rendimento da estrutura proposta à superior se comparado ao da topologia Half-Bridge/NPC, conforme esperado em funÃÃo das perdas na estrutura Half-Bridge/NPC serem maiores e mal distribuÃdas.<br>This work presents a new topology of a hybrid five-level inverter, conceived from the halfbridge and active neutral point clamped structures, suitable for high-voltage, high-power applications. The possible commutation stages, the switching drive logic, the semiconductors stresses mathematical analysis, and the losses study are presented. Two modulation techniques were selected in order to allow low-frequency (60 Hz) switches operate together with high-frequency switches (1020 Hz), reducing the number of commutations and, consequently, the overall losses and the output voltage total harmonic distortion. In order to validate the proposal, it was developed a 7.5 kVA prototype and AC line output voltage of 380 V. The digital implementation from both modulation techniques on the chosen programmable logic device FPGA is also presented. The experimental results relative to the three-phase structure validate the proposed topology. The topology, operating with the modulation based on Sinusoidal In-Phase Disposition - PWM, presented a THD of 29.71%, and WTHD of 1.93%, while the one based on the Centered Space Vector - PWM presented a THD of 38.45%, and a WTHD of 7.21%. Besides, the overall efficiency is superior when compared to the Half-Bridge/NPC topology, as expected, due to the fact that losses on this structure are higher and misdistributed.

Ces dernières années, l’utilisation des systèmes de transport aérien s'est considérablement amplifié. Par conséquent, les considérations environnementales actuelles poussent à réduire leur utilisation. Des projets tels que Clean Sky 2 tentent d’apporter une réponse à ce problème, en proposant une réduction des émissions de CO2 et des nuisances sonores. Le recours à l’hybridation de la propulsion des avions réduirait ces émissions en réduisant la taille et la masse des systèmes et en utilisant des systèmes électriques plus efficaces ce qui permettrai d’augmenter le nombre de passager. Cela permettrait de réduire la consommation de carburant et donc les émissions polluantes. Ces travaux s'inscrivent dans le cadre du projet européen HASTECS Clean Sky 2 qui vise à optimiser l'ensemble de la chaîne électrique de l'avion à propulsion hybride en intégrant toutes les contraintes aéronautiques telles que les décharges partielles pour les équipements électriques placés en zone non pressurisée. Le projet HASTECS s'est fixé le défi de doubler la densité de puissance des machines électriques pour passer de 5 kW/kg à 10 kW/kg, y compris leur refroidissement, tandis que pour l'électronique de puissance, avec son système de refroidissement, le but sera de passer à 15 kW/kg en 2025 et à 25 kW/kg en 2035. Pour augmenter la densité de puissance, la masse du système de refroidissement doit être diminuée dans un premier temps soit en optimisant ses composants, ce qui est fait par le 4ème lot de travail (WP4), soit en réduisant les pertes. La réduction des pertes de l'onduleur pourrait être obtenue en utilisant de semi-conducteurs de faible calibre en tension, en jouant sur les stratégies de modulation ou en utilisant des semi-conducteurs plus performants. La première option peut être faite en utilisant des architectures multi-niveaux pour éviter l'association en série direct. Contrairement à l'association directe en série, l'association parallèle est plus facile à gérer en termes de commande de interrupteurs, ce qui a été autorisé dans nos études. Plusieurs topologies d'onduleurs (topologies à 2, 3 et 5 niveaux) et stratégies de modulation (PWM, injection de troisième harmonique, PWM discontinu et pleine onde) ont été comparées en utilisant plusieurs technologies de semi-conducteurs pour choisir la solution la plus performante en termes de rendement et de densité de puissance. Pour le profil de mission considéré, l'onduleur pourrait être dimensionné pour le point de puissance maximum (décollage) ou la phase de vol la plus longue (croisière). Une étude comparative des stratégies de modulation a été réalisée pour mettre en évidence la structure et la modulation présentant les meilleures performances afin de minimiser les pertes pour les points de dimensionnement choisis en utilisant les topologies les plus intéressantes pour le profil de mission étudié en utilisant deux configurations différentes de bobinage du moteur électrique proposées par le WP1<br>Recently, the use of air transport systems has increased considerably. Therefore, the current environmental considerations are pushing to reduce their ecological impact. Projects such as Clean Sky 2 provide an answer to this problem, by proposing a reduction in CO2 emissions and noise pollution. The development of a hybrid-electric aircraft would reduce these emissions by reducing the size and weight of the systems and using more efficient electrical systems. This would reduce fuel consumption and therefore pollutant emissions. This work takes part into HASTECS Clean Sky 2 European project which aims to optimize the complete electrical chain of the hybrid aircraft integrating all aeronautical constraints such as partial discharges for electrical equipment placed in the non-pressurized zone. HASTECS project has set itself the challenge of doubling the specific power of electric machines including their cooling from 5 kW/kg to 10 kW/kg, while the power electronics, with their cooling system, would evolve from 15 kW/kg in 2025 to 25 kW/kg in 2035. To increase the specific power, the cooling system mass should be decreased either by optimizing its components which is done by the 4th work package (WP4) or by reducing power losses. Inverter losses reduction could be achieved by using small voltage rating components, by playing on modulation strategies or by using more performant semiconductors. The first option could be done by using multilevel architectures to avoid the direct series association. Unlike direct series association, the parallel one is easier to manage in terms of switches command so it was allowed in our studies. Several inverter topologies (2-, 3- and 5-level topologies) and modulation strategies (PWM, third harmonic injection, discontinuous PWM and full-wave) were compared using several semiconductors generations to choose the most performant solution in terms of efficiency and specific power. For the considered mission profile, the inverter could be sized for the maximum power point (takeoff) or the most extended flight phase (cruise). A comparative study of modulation strategies was carried out to highlight the structure and modulation presenting the best performance to minimize the losses for the chosen sizing points using most interesting topologies for the studied mission profile using two electrical motor windings configurations proposed by WP1

The Queensland University of Technology (QUT) allows the presentation of theses for the Degree of Doctor of Philosophy in the format of published or submitted papers, where such papers have been published, accepted or submitted during the period of candidature. This thesis is composed of ten published /submitted papers and book chapters of which nine have been published and one is under review. This project is financially supported by an Australian Research Council (ARC) Discovery Grant with the aim of investigating multilevel topologies for high quality and high power applications, with specific emphasis on renewable energy systems. The rapid evolution of renewable energy within the last several years has resulted in the design of efficient power converters suitable for medium and high-power applications such as wind turbine and photovoltaic (PV) systems. Today, the industrial trend is moving away from heavy and bulky passive components to power converter systems that use more and more semiconductor elements controlled by powerful processor systems. However, it is hard to connect the traditional converters to the high and medium voltage grids, as a single power switch cannot stand at high voltage. For these reasons, a new family of multilevel inverters has appeared as a solution for working with higher voltage levels. Besides this important feature, multilevel converters have the capability to generate stepped waveforms. Consequently, in comparison with conventional two-level inverters, they present lower switching losses, lower voltage stress across loads, lower electromagnetic interference (EMI) and higher quality output waveforms. These properties enable the connection of renewable energy sources directly to the grid without using expensive, bulky, heavy line transformers. Additionally, they minimize the size of the passive filter and increase the durability of electrical devices. However, multilevel converters have only been utilised in very particular applications, mainly due to the structural limitations, high cost and complexity of the multilevel converter system and control. New developments in the fields of power semiconductor switches and processors will favor the multilevel converters for many other fields of application. The main application for the multilevel converter presented in this work is the front-end power converter in renewable energy systems. Diode-clamped and cascade converters are the most common type of multilevel converters widely used in different renewable energy system applications. However, some drawbacks – such as capacitor voltage imbalance, number of components, and complexity of the control system – still exist, and these are investigated in the framework of this thesis. Various simulations using software simulation tools are undertaken and are used to study different cases. The feasibility of the developments is underlined with a series of experimental results. This thesis is divided into two main sections. The first section focuses on solving the capacitor voltage imbalance for a wide range of applications, and on decreasing the complexity of the control strategy on the inverter side. The idea of using sharing switches at the output structure of the DC-DC front-end converters is proposed to balance the series DC link capacitors. A new family of multioutput DC-DC converters is proposed for renewable energy systems connected to the DC link voltage of diode-clamped converters. The main objective of this type of converter is the sharing of the total output voltage into several series voltage levels using sharing switches. This solves the problems associated with capacitor voltage imbalance in diode-clamped multilevel converters. These converters adjust the variable and unregulated DC voltage generated by renewable energy systems (such as PV) to the desirable series multiple voltage levels at the inverter DC side. A multi-output boost (MOB) converter, with one inductor and series output voltage, is presented. This converter is suitable for renewable energy systems based on diode-clamped converters because it boosts the low output voltage and provides the series capacitor at the output side. A simple control strategy using cross voltage control with internal current loop is presented to obtain the desired voltage levels at the output voltage. The proposed topology and control strategy are validated by simulation and hardware results. Using the idea of voltage sharing switches, the circuit structure of different topologies of multi-output DC-DC converters – or multi-output voltage sharing (MOVS) converters – have been proposed. In order to verify the feasibility of this topology and its application, steady state and dynamic analyses have been carried out. Simulation and experiments using the proposed control strategy have verified the mathematical analysis. The second part of this thesis addresses the second problem of multilevel converters: the need to improve their quality with minimum cost and complexity. This is related to utilising asymmetrical multilevel topologies instead of conventional multilevel converters; this can increase the quality of output waveforms with a minimum number of components. It also allows for a reduction in the cost and complexity of systems while maintaining the same output quality, or for an increase in the quality while maintaining the same cost and complexity. Therefore, the asymmetrical configuration for two common types of multilevel converters – diode-clamped and cascade converters – is investigated. Also, as well as addressing the maximisation of the output voltage resolution, some technical issues – such as adjacent switching vectors – should be taken into account in asymmetrical multilevel configurations to keep the total harmonic distortion (THD) and switching losses to a minimum. Thus, the asymmetrical diode-clamped converter is proposed. An appropriate asymmetrical DC link arrangement is presented for four-level diode-clamped converters by keeping adjacent switching vectors. In this way, five-level inverter performance is achieved for the same level of complexity of the four-level inverter. Dealing with the capacitor voltage imbalance problem in asymmetrical diodeclamped converters has inspired the proposal for two different DC-DC topologies with a suitable control strategy. A Triple-Output Boost (TOB) converter and a Boost 3-Output Voltage Sharing (Boost-3OVS) converter connected to the four-level diode-clamped converter are proposed to arrange the proposed asymmetrical DC link for the high modulation indices and unity power factor. Cascade converters have shown their abilities and strengths in medium and high power applications. Using asymmetrical H-bridge inverters, more voltage levels can be generated in output voltage with the same number of components as the symmetrical converters. The concept of cascading multilevel H-bridge cells is used to propose a fifteen-level cascade inverter using a four-level H-bridge symmetrical diode-clamped converter, cascaded with classical two-level Hbridge inverters. A DC voltage ratio of cells is presented to obtain maximum voltage levels on output voltage, with adjacent switching vectors between all possible voltage levels; this can minimize the switching losses. This structure can save five isolated DC sources and twelve switches in comparison to conventional cascade converters with series two-level H bridge inverters. To increase the quality in presented hybrid topology with minimum number of components, a new cascade inverter is verified by cascading an asymmetrical four-level H-bridge diode-clamped inverter. An inverter with nineteen-level performance was achieved. This synthesizes more voltage levels with lower voltage and current THD, rather than using a symmetrical diode-clamped inverter with the same configuration and equivalent number of power components. Two different predictive current control methods for the switching states selection are proposed to minimise either losses or THD of voltage in hybrid converters. High voltage spikes at switching time in experimental results and investigation of a diode-clamped inverter structure raised another problem associated with high-level high voltage multilevel converters. Power switching components with fast switching, combined with hard switched-converters, produce high di/dt during turn off time. Thus, stray inductance of interconnections becomes an important issue and raises overvoltage and EMI issues correlated to the number of components. Planar busbar is a good candidate to reduce interconnection inductance in high power inverters compared with cables. The effect of different transient current loops on busbar physical structure of the high-voltage highlevel diode-clamped converters is highlighted. Design considerations of proper planar busbar are also presented to optimise the overall design of diode-clamped converters.

Détection de défaut d'arcs intégrée dans un convertisseur intelligent contrôlé par FPGA pour les panneaux photovoltaïques. La mise au point de convertisseur intelligents intégrant des dispositifs de protection est une thématique que cherche à développer l'Institut Technologique de Morelia (Mexique) avec laquelle nous collaborons sur ce projet. L'objectif plus spécifique de ce travail repose sur la détection de défauts d'arc électrique en se basant sur le contrôle intelligent des onduleurs utilisés dans la gestion de l'énergie produite par des panneaux photovoltaïques. Depuis plusieurs années, le développement croissant des panneaux solaires photovoltaïques comme source d’énergie s’est imposé et la sécurité de ces dispositifs liée à la détection de défauts d’arcs électriques est devenu un enjeu majeur. L'approche que nous proposons dans ce travail est le développement d'une stratégie novatrice pour la surveillance et la prédiction de défaillance du réseau électrique constitué de panneaux solaires en présence de défauts d’arcs. Actuellement, la majorité des systèmes de détection comprennent des modules détecteurs disposés dans le circuit électrique à protéger dont la robustesse est loin d'être optimale. L'approche que nous proposons consiste à développer un dispositif de surveillance et de détection de défaut directement intégré dans l'onduleur intelligent. Le contrôle optimal de l'onduleur intelligent assurera une détection fiable de défaut d'arc sans déclenchement intempestif. Le dispositif comprendra également un système de coupure. La méthode de détection que nous privilégions sera basée sur l'analyse du courant et de la tension de ligne. Les algorithmes seront basés sur une analyse temps/fréquence des signatures courant et de tension suivie par une logique pertinente de décision de telle manière à minimiser le taux de fausses détections.Le noyau du convertisseur intelligent est constitué par un FPGA. Le parallélisme des traitements de données assurera le respect des contraintes temps réel. Dans le cadre du projet de thèse, la mise en œuvre, le test des algorithmes de détection et l’implémentation optimale afin de respecter les contraintes temps réel dans le FPGA sera mené dans le cadre d’une cotutelle de thèse entre l’institut technologique de Morelia et l’Université de Lorraine<br>In this research work, the development of a multilevel inverter for PV applications is presented. The PV inverter, has two stages one DC/DC converter and one DC/AC inverter, and is capable of generating an AC multilevel output of nine levels, it's a transformerless inverter and uses a reduced number of components compared to other topologies. The conception of a novel DC/DC converter is capable of generating two isolated DC voltage levels needed to feed the DC/AC stage. This DC/DC stage is developed in two variants, buck and boost, the _rst to perform the reduction of voltage when the DC bus is too high, and second to increase the voltage when the DC bus is too low to perform interconnection with the grid through the DC/AC inverter. This is achieved thanks to the parallel functioning of the developed topology, which make use of moderated duty cycles, that reduces the stress in the passive and switching components, reducing potential losses. The validation of the PV inverter is performed in simulation and experimental scenarios. In the other hand, the response of the inverter facing an arc fault in the DC bus is studied by performing a series of tests where the fault is generated in strategic points of the DC side, this is possible thanks to the design and construction of an arc fault generator based in the specifications of the UL1699B norm. During the tests is observed that with the apparition of an arc fault, there is a lost in the half-wave symmetry of the AC multilevel output voltage waveform, generating even harmonics which aren't present during normal operation, only when an arc fault is present in the DC system. The monitoring of even harmonics set the direction for developing the detection technique. Since the magnitude of even harmonics in the inverter is very low, the total even harmonic distortion is employed as a base for the detection technique presented in this thesis. The effectiveness of this method is verified with a series of tests performed with different loads

Made available in DSpace on 2016-12-12T20:27:38Z (GMT). No. of bitstreams: 1 Marcos Vinicius Bressan.pdf: 3794882 bytes, checksum: c55b9af15d7d913dc3d962a990a792c4 (MD5) Previous issue date: 2014-02-18<br>Coordenação de Aperfeiçoamento de Pessoal de Nível Superior<br>This work present a new three-phase hybrid multilevel inverter, that is composed of two topologies in cascaded association. The three-phase NPC and the half-bridge modules are connected in series. This con¬nection increases the number of the output voltage levels, improves the output voltage quality and rises the power process by inverter. The theoretical analysis is presented, the switching states are investigated and the average and the RMS currents values in the semiconductors are verified. Based on the current values are projected the dc capacitors, and analyzed the semicondutors loss energy and the input currents of the inverter. Two modulation scheme are presented at proposed inver¬ter, the hybrid PWM and SVM modulation scheme. The first part of the experimental results are verified behavior of the multilevel power structure developed in laboratory. The second part of the experimen¬tal results evaluates quality of output voltage with different modulation scheme using of the mathematical tools THD and WTHD.<br>Este trabalho apresenta um novo inversor multinível híbrido trifásico, que é formado pela associação em cascata de duas topologias. No caso, um conversor NPC trifásico conectado em série a módulos de converso¬res meia ponte. A ligação em série desses conversores permite ampliar o número de níveis de tensão sintetizados pelo inversor, melhorar a qualidade da forma de onda da tensão de saída e o aumento da energia processada pelo inversor. Uma análise teórica do inversor é apresen¬tada, averiguando as etapas de operação e determinando os valores médio e eficaz da corrente nos semicondutores de potência. Com base nas análises dos valores médio e eficaz da corrente nos semicondutores dimensiona-se os capacitores de barramento, assim com a energia dissi¬pada pelos semicondutores e a análise teórica das correntes de entradas do inversor empregando de retificadores multipulsos. Também são apre¬sentadas duas técnicas de modulação ao inversor proposto: a técnica de modulação PWM híbrida e a SVM. Os resultados experimentais, em sua primeira parte, avaliam o comportamento da estrutura multinível desenvolvida em laboratório. Na segunda parte dos resultados experi¬mentais, avalia-se qualidade da forma de onda de tensão com diferentes técnicas de modulação utilizando das ferramentas matemáticas THD e WTHD.

碩士<br>國立虎尾科技大學<br>機械與機電工程研究所<br>98<br>This thesis proposed a hybrid multi-level inverters having 3 inverters in series with distinct dc link voltages to generate 13 voltage levels in order to reduce output voltage and current distortion and power switch stress and switching frequency. Therefore, EMI (Electro Magnetic Interference) can be alleviated due to lower switching frequency. The experiments are conducted to show the performance of the proposed hybrid multi-level inverters that in stand-alone system to reduce the voltage distortion significantly in load-variation, rectifier load, and phase-controlled load conditions; for the grid-tied system, the output current is closed to sinusoidal waveform and current ripple is reduced as well.

Today many efforts are made to research and use new energy sources because the potential for an energy crisis is increasing. Multilevel converters have gained much attention in the area of energy distribution and control due to its advantages in high power applications with low harmonics. They not only achieve high power ratings, but also enable the use of renewable energy sources. The general function of the multilevel converter is to synthesize a desired high voltage from several levels of dc voltages that can be batteries, fuel cells, etc. This dissertation presents a new hybrid multilevel inverter for voltage boost. The inverter consists of a standard 3-leg inverter (one leg for each phase) and H-bridge in series with each inverter leg. It can use only a single DC power source to supply a standard 3-leg inverter along with three full H-bridges supplied by capacitors or batteries. The proposed inverter could be applied in hybrid electric vehicles (HEVs) and fuel cell based hybrid electric vehicles (FCVs). It is of voltage boosting capability and eliminates the magnetics. This feature makes it suitable for the motor running from low to high power mode. In addition to hybrid electric vehicle applications, this paper also presents an application where the hybrid multilevel inverter acts as a renewable energy utility interface. In this dissertation, the structure, operation principle, and modulation control schemes of the proposed hybrid multilevel inverter are introduced. Simulation models and results are described and analyzed. An experimental 5 kW prototype inverter is built and tested.