Relevant bibliographies by topics / Image processing FPGA

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers

Academic literature on the topic 'Image processing FPGA'

Author: Grafiati
Published: 5 June 2025
Last updated: 15 July 2025

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Journal articles on the topic "Image processing FPGA"

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Ai, Duong Huu, Van Loi Nguyen, Khanh Ty Luong, and Viet Truong Le. "Design of mean filter using field programmable gate arrays for digital images." Indonesian Journal of Electrical Engineering and Computer Science 36, no. 3 (2024): 1430. http://dx.doi.org/10.11591/ijeecs.v36.i3.pp1430-1436.

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In this paper, we design and analysis of mean filter using field programmable gate arrays (FPGAs) for digital images, FPGAs are integrated circuits consisting of interconnections that connect programmable internal hardware blocks allows users to customize operations for a specific application. FPGA is an ideal choice for real-time image processing, these FPGA devices are controlled in Verilog or VHDL languages, allowing to design at different levels and adapt to design changes or even support new applications throughout the life of the component. Digital image filtering is the most important task in image processing and with the help of computers, image recognition involves identifying and classifying objects in an image. This paper design of mean filter for digital image processing, implementation and analysis of image processing algorithms on FPGAs. The results obtained on the FPGA are compared and analyzed with the results by MATLAB software.
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Bundschuh, Sina, Jan Kunze, and Klaus-Dieter Kuhnert. "Implementation of an FPGA-Based System to Process Images and Match Keypoints on High-Resolution Pictures." Electronics 13, no. 23 (2024): 4774. https://doi.org/10.3390/electronics13234774.

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Processing scenery and finding points of interest is crucial for applications in robotics and aerospace missions. Those areas require efficient and reliable visual input processing. Here, field programmable gate arrays (FPGAs) offer essential advantages, like low power consumption compared to CPUs, performing a large number of calculations simultaneously, and having compact hardware. This paper presents an FPGA system that processes incoming camera data, finds points of interest, and matches them across different images on high-resolution images (2048 × 1088). It is a novel approach to implement the complete image processing pipeline on high-resolution images within the FPGA fabric without additional hardware. For keypoint detection and matching, our work uses a modified SIFT algorithm optimized for FPGA implementation processing and a nearest neighbor-based matching method. It was implemented on a Xilinx Kintex-7 FPGA and partially on a NanoXplore NG-Ultra to evaluate a radiation-hardened FPGA for space applications. On the Kintex-7, the keypoint detection achieves a speed of 33 ms per image, and its features are matched on up to 5 images per second. Judging by the resource utilization of one image processing module on the NG-Ultra, porting the entire system on a radiation-hardened FPGA appears feasible.
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B, Devanathan, Selvaraju P, Thulasimani T, and Vishal Ratansing Patil. "FPGA-BASED HARDWARE ACCELERATION OF MACHINE LEARNING ALGORITHM FOR REAL-TIME IMAGE PROCESSING." ICTACT Journal on Microelectronics 9, no. 3 (2023): 1613–19. https://doi.org/10.21917/ijme.2023.0280.

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In real-time image processing, the demand for efficient solutions has surged with the proliferation of applications spanning from autonomous vehicles to medical diagnostics. This study addresses the imperative need for accelerated machine learning algorithms to enhance the processing speed of image-related tasks. The research focuses on leveraging Field-Programmable Gate Arrays (FPGAs) to implement hardware acceleration, exploiting their parallel computing capabilities. The advent of machine learning in image processing has revolutionized various industries, yet real-time applications encounter computational bottlenecks. This research delves into hardware acceleration using FPGAs to overcome these constraints, offering a novel approach to expedite machine learning algorithms. Traditional software implementations of machine learning algorithms often fall short in meeting real-time processing requirements. This research aims to bridge this gap by exploring FPGA-based hardware acceleration, addressing the performance limitations hindering the seamless integration of machine learning into real-time image processing systems. While existing literature acknowledges the potential of FPGA-based acceleration, a comprehensive exploration of its application for real-time image processing is lacking. This research fills the void by presenting a detailed method and empirical results, contributing to the limited body of knowledge on FPGA-accelerated machine learning in the of image processing. The study employs a systematic approach, integrating machine learning algorithms onto FPGAs through hardware description languages. The implementation is optimized to exploit parallelism inherent in FPGAs, resulting in a tailored hardware solution for real-time image processing. Comparative analyses against software implementations provide insights into the performance gains achieved. The experimental results demonstrate a significant enhancement in processing speed, validating the efficacy of FPGA-based hardware acceleration for machine learning algorithms in real-time image processing applications.
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Bailey, Donald G. "Image Processing Using FPGAs." Journal of Imaging 5, no. 5 (2019): 53. http://dx.doi.org/10.3390/jimaging5050053.

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Nine articles have been published in this Special Issue on image processing using field programmable gate arrays (FPGAs). The papers address a diverse range of topics relating to the application of FPGA technology to accelerate image processing tasks. The range includes: Custom processor design to reduce the programming burden; memory management for full frames, line buffers, and image border management; image segmentation through background modelling, online K-means clustering, and generalised Laplacian of Gaussian filtering; connected components analysis; and visually lossless image compression.
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Vesely, Jaroslav. "FPGA and GPU Utilization in Industrial Image Processing: Comparative Study and Application." International Journal Software Engineering and Computer Science (IJSECS) 5, no. 1 (2025): 88–101. https://doi.org/10.35870/ijsecs.v5i1.3273.

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This work aims to investigate the FPGA (Field-Programmable Gate Array) and GPU (Graphical Processing Unit) technology in image optimization research for an industrial frontier study. Using an experimental method, the research compared the efficiency of two technologies as implemented in some many image processing algorithms. NI CompactRIO platform for FPGA implementation and NVIDIA GeForce GTX 970 in GPU processing performed differently. As is well known, low-lag applications (camera synchronization, real-time data processing etc.) were very well suited for FPGAs. GPUs with architecture CUDA, on the other hand could be a thousand times faster than traditional CPUs in parallel data processing. Other challenges identified through analysis were FPGA design optimization and GPU resource wise utilization. The results give recommendation in terms of selecting technologies based on the features for image industrial processing applications
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Janmane, Akshay S., Apeksha S. Patil, and Madhuri V. Huilgol. "FPGA Based Real Time Medical Image Processing." Bonfring International Journal of Research in Communication Engineering 6, Special Issue (2016): 113–16. http://dx.doi.org/10.9756/bijrce.8214.

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Duong, Huu Ai, Dat Vuong Cong, Ty Luong Khanh, and Truong Le Viet. "Field programmable gate array implementation of edge detection system based on an improved sobel edge detector." Indonesian Journal of Electrical Engineering and Computer Science 32, no. 3 (2023): 1378–83. https://doi.org/10.11591/ijeecs.v32.i3.pp1378-1383.

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Field programmable gate array (FPGA) is an integrated circuit consisting of internal hardware blocks with programmable link connections for users to customize operations for a particular application. Link connections can be easily reprogrammed, allowing the FPGA to adapt to changes to the design or even support a new application throughout the department's uptime. One of the important tasks in image processing is image edge detection image, with computer aided, image recognition is concerned with the recognition and classification of objects in an image, so edge detection is an important tool. In this paper, we design filter for edge detection in image processing using FPGA kit. We analysis and implementation of algorithm for image processing on FPGA, load the code and run the results. Comparative analysis with images processed by MATLAB software.
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Huu Ai, Duong, Cong Dat Vuong, Khanh Ty Luong, and Viet Truong Le. "Field programmable gate array implementation of edge detection system based on an improved sobel edge detector." Indonesian Journal of Electrical Engineering and Computer Science 32, no. 3 (2023): 1378. http://dx.doi.org/10.11591/ijeecs.v32.i3.pp1378-1383.

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<p>Field programmable gate array (FPGA) is an integrated circuit consisting of internal hardware blocks with programmable link connections for users to customize operations for a particular application. Link connections can be easily reprogrammed, allowing the FPGA to adapt to changes to the design or even support a new application throughout the department's uptime. One of the important tasks in image processing is image edge detection image, with computer aided, image recognition is concerned with the recognition and classification of objects in an image, so edge detection is an important tool. In this paper, we design filter for edge detection in image processing using FPGA kit. We analysis and implementation of algorithm for image processing on FPGA, load the code and run the results. Comparative analysis with images processed by MATLAB software.</p>
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Fu, Qing Qing, and Zheng Bin Liang. "The Design of Textile Image Processing System." Applied Mechanics and Materials 148-149 (December 2011): 250–53. http://dx.doi.org/10.4028/www.scientific.net/amm.148-149.250.

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According to the drawback of high cost and complicated circuit and inadequate use of resources in DSP and FPGA structure of textile image processing, an image processing system based on Nios II in FPGA is designed. FPGA is the core of the system.Nios II processor is created in FPGA.Video image is acquired by CCD and processed in FPGA. The result shows that the system has some characteristics of small size, low cost, high integration, high stability and flexibility.
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Zhou, Guangshao, Shuai Guo, and Zhibo Chen. "FPGA-Based Improved Sobel Operator Edge Detection." Frontiers in Computing and Intelligent Systems 5, no. 2 (2023): 6–11. http://dx.doi.org/10.54097/fcis.v5i2.12122.

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Image edge detection is an important field in image processing, with its primary goal being to identify edge information of various objects in images. Traditional edge detection programs are mostly executed serially, resulting in low detection efficiency. This paper proposes an FPGA-based improved Sobel operator edge detection method, harnessing the parallel processing capability of FPGA to enhance detection efficiency. Building upon the Sobel operator in edge detection algorithms, this method increases the convolution calculation dimensions of the Sobel operator, expanding it from 2 directions to 8 directions for more precise edge information. Images captured by OV5640 are processed within the FPGA and displayed via VGA. Compared to other edge detection algorithms, the FPGA-based improved Sobel operator edge detection method efficiently and rapidly detects image edges, ensuring stable image display and accurate edge information.
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Dissertations / Theses on the topic "Image processing FPGA"

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Zhao, Jin. "Video/Image Processing on FPGA." Digital WPI, 2015. https://digitalcommons.wpi.edu/etd-theses/503.

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Video/Image processing is a fundamental issue in computer science. It is widely used for a broad range of applications, such as weather prediction, computerized tomography (CT), artificial intelligence (AI), and etc. Video-based advanced driver assistance system (ADAS) attracts great attention in recent years, which aims at helping drivers to become more concentrated when driving and giving proper warnings if any danger is insight. Typical ADAS includes lane departure warning, traffic sign detection, pedestrian detection, and etc. Both basic and advanced video/image processing technologies are deployed in video-based driver assistance system. The key requirements of driver assistance system are rapid processing time and low power consumption. We consider Field Programmable Gate Array (FPGA) as the most appropriate embedded platform for ADAS. Owing to the parallel architecture, an FPGA is able to perform high-speed video processing such that it could issue warnings timely and provide drivers longer time to response. Besides, the cost and power consumption of modern FPGAs, particular small size FPGAs, are considerably efficient. Compared to the CPU implementation, the FPGA video/image processing achieves about tens of times speedup for video-based driver assistance system and other applications.
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Nnolim, Uche. "Fpga architectures for logarithmic colour image processing." Thesis, University of Kent, 2009. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.509634.

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Harris, Matthew Joshua. "Accelerating Reverse Engineering Image Processing Using FPGA." Wright State University / OhioLINK, 2019. http://rave.ohiolink.edu/etdc/view?acc_num=wright155535529307322.

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Xu, Haifeng. "Digital Image Processing Algorithms Research Based on FPGA." Thesis, KTH, Skolan för informations- och kommunikationsteknik (ICT), 2011. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-91039.

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As we can find through the development of TV systems in America, the digital TV related digital broadcasting is just the road we would walk into. Nowadays digital television is prevailing in China, and the government is promoting the popularity of digital television. However, because of the economic development, analog television will still take its place in the TV market during a long period. But the broadcasting system has not been reformed, as a result, we should not only take use of the traditional analog system we already have, but also improve the quality of the pictures of analog system. With the high-speed development of high-end television, the research and application of digital television technique, the flaws caused by interlaced scan in traditional analog television, such as color-crawling, flicker and fast-moved object's boundary blur and zigzag, are more and more obvious. Therefore the conversion of interlaced scan to progressing scan, which is de-interlacing, is an important part of current television production. At present there are many kinds of TV sets appearing in the market. They are based on digital processing technology and use various digital methods to process the interlaced, low-field rate video data, including the de-interlacing and field rate conversion. The digital process chip of television is the heart of the new-fashioned TV set, and is the reason of visual quality improvement. As a requirement of real time television signal processing, most of these chips has developed novel hardware architecture or data processing algorithm. So far, the most quality effective algorithm is based on motion compensation, in which motion detection and motion estimation will be inevitably involved, in despite of the high computation cost. in video processing chips, the performance and complexity of motion estimation algorithm have a direct impact on speed area and power consumption of chips. Also, motion estimation determined the efficiency of the coding algorithms in video compression. This thesis proposes a Down-sampled Diamond NTSS algorithm (DSD-NTSS) based on New Three Step Search (NTSS) algorithm, taking both performance and complexity of motion estimation algorithms into consideration. The proposed DSD-NTSS algorithm makes use of the similarity of neighboring pixels in the same image and down-samples pixels in the reference blocks with the decussate pattern to reduce the computation cost. Experiment results show that DSD-NTSS is a better tradeoff in the terms of performance and complexity. The proposed DSD-NTSS reduces the computation cost by half compared with NTSS when having the equivalent image quality. Further compared with Four Step Search(FSS) Diamond Search(DS)、Three Step Search(TSS) and some other fast searching algorithms, the proposed DSD-NTSS generally surpasses in performance and complexity. This thesis focuses on a novel computation-release motion estimation algorithm in video post-processing system and researches the FPGA design of the system.
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Siddiqui, Fahad Manzoor. "FPGA-based programmable embedded platform for image processing applications." Thesis, Queen's University Belfast, 2018. https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.766276.

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A vast majority of electronic systems including medical, surveillance and critical infrastructure employs image processing to provide intelligent analysis. They use onboard pre-processing to reduce data bandwidth and memory requirements before sending information to the central system. Field Programmable Gate Arrays (FPGAs) represent a strong platform as they permit reconfigurability and pipelining for streaming applications. However, rapid advances and changes in these application use cases crave adaptable hardware architectures that can process dynamic data workloads and be easily programmed to achieve ecient solutions in terms of area, time and power. FPGA-based development needs iterative design cycles, hardware synthesis and place-and-route times which are alien to the software developers. This work proposes an FPGA-based programmable hardware acceleration approach to reduce design effort and time. This allows developers to use FPGAs to profile, optimise and quickly prototype algorithms using a more familiar software-centric, edit-compile-run design flow that enables the programming of the platform by software rather than high-level synthesis (HLS) engineering principles. Central to the work has been the development of an optimised FPGA-based processor called Image Processing Processor (IPPro) which efficiently uses the underlying resources and presents a programmable environment to the programmer using a dataflow design principle. This gives superior performance when compared to competing alternatives. From this, a three-layered platform has been created which enables the realisation of parallel computing skeletons on FPGA which are used to eciently express designs in high-level programming languages. From bottom-up, these layers represent programming (actor, multiple actors and parallel skeletons) and hardware (IPPro core, multicore IPPro, system infrastructure) abstraction. The platform allows acceleration of parallel and non-parallel dataflow applications. A set of point and area image pre-processing functions are implemented on Avnet Zedboard platform which allows the evaluation of the performance. The point function achieved 2.53 times better performance than the area functions and point and area functions achieved performance improvements of 7.80 and 5.27 times over sin- gle core IPPro by exploiting data parallelism. The pipelined execution of multiple stages revealed that a dataflow graph can be decomposed into balanced actors to deliver maximum performance by hiding data transfer and processing time through exploiting task parallelism; otherwise, the maximum achievable performance is limited by the slowest actor due to the ripple effect caused by unbalanced actors. The platform delivered better performance in terms of fps/Watt/Area than Embedded Graphic Processing Unit (GPU) considering both technologies allows a software-centric design flow.
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Ericsson, Kenneth, and Robert Grann. "Image optimization algorithms on an FPGA." Thesis, Mälardalen University, School of Innovation, Design and Engineering, 2009. http://urn.kb.se/resolve?urn=urn:nbn:se:mdh:diva-5727.

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<p> </p><p>In this thesis a method to compensate camera distortion is developed for an FPGA platform as part of a complete vision system. Several methods and models is presented and described to give a good introduction to the complexity of the problems that is overcome with the developed method. The solution to the core problem is shown to have a good precision on a sub-pixel level.</p><p> </p>
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Isaksson, Johan. "FPGA-Accelerated Image Processing Using High Level Synthesis with OpenCL." Thesis, Linköpings universitet, Datorteknik, 2017. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-143213.

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High Level Synthesis (HLS) is a new method for developing applications for use on FPGAs. Instead of the classic approach using a Hardware Descriptive Language (HDL), a high level programming language can be used. HLS has many perks, including high level debugging and simulation of the system being developed. This shortens the development time which in turn lowers the development cost. In this thesis an evaluation is made regarding the feasibility of using SDAccel as the HLS tool in the OpenCL environment. Two image processing algorithms are implemented using OpenCL C and then synthesized to run on a Kintex Ultrascale FPGA. The implementation focuses both on low latency and throughput as the target environment is a video distribution network used in vehicles. The network provides the driver with video feeds from cameras mounted on the vehicle. Finally the test result of the algorithm runs are presented, displaying how well the HLS tool has preformed in terms of system performance and FPGA resource utilization.
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Serguienko, Anton. "Evaluation of Image Warping Algorithms for Implementation in FPGA." Thesis, Linköping University, Department of Electrical Engineering, 2008. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-11849.

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<p>The target of this master thesis is to evaluate the Image Warping technique and propose a possible design for an implementation in FPGA. The Image Warping is widely used in the image processing for image correction and rectification. A DSP is a usual choice for implantation of the image processing algorithms, but to decrease a cost of the target system it was proposed to use an FPGA for implementation.</p><p>In this work a different Image Warping methods was evaluated in terms of performance, produced image quality, complexity and design size. Also, considering that it is not only Image Warping algorithm which will be implemented on the target system, it was important to estimate a possible memory bandwidth used by the proposed design. The evaluation was done by implemented a C-model of the proposed design with a finite datapath to simulate hardware implementation as close as possible.</p>
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Laptik, Raimond. "Ant colony technologies for image processing." Doctoral thesis, Lithuanian Academic Libraries Network (LABT), 2010. http://vddb.laba.lt/obj/LT-eLABa-0001:E.02~2009~D_20100303_133726-51617.

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In this work ant colony technologies for image processing are analyzed. Modifications of Max-Min ant system for automatic image pre-processing are proposed. Image segmentation by multiple ant colonies technique based on pheromone competition is proposed. Modified ant system is implemented in FPGA and MicroBlaze core units influence on performance is analyzed.<br>Darbe nagrinėjamos skruzdžių kolonijų technologijos vaizdams apdoroti. Pasiūlomos max-min skruzdžių sistemos modifikacijos tinkamos automatizuoti pirminį vaizdų apdorojimą. Pristatoma vaizdų segmentavimo metodika grįsta skruzdžių kolonijų varžymusi feromono pagalba. Nagrinėjama, įgyvendintos LPLM įrenginyje, modifikuotos skruzdžių sistemos sparta ir MicroBlaze modulių įtaka spartai.
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Qureshi, Kamran. "Pedestrian Detection on FPGA." Thesis, Mittuniversitetet, Avdelningen för elektronikkonstruktion, 2014. http://urn.kb.se/resolve?urn=urn:nbn:se:miun:diva-21509.

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Image processing emerges from the curiosity of human vision. To translate, what we see in everyday life and how we differentiate between objects, to robotic vision is a challenging and modern research topic. This thesis focuses on detecting a pedestrian within a standard format of an image. The efficiency of the algorithm is observed after its implementation in FPGA. The algorithm for pedestrian detection was developed using MATLAB as a base. To detect a pedestrian, a histogram of oriented gradient (HOG) of an image was computed. Study indicates that HOG is unique for different objects within an image. The HOG of a series of images was computed to train a binary classifier. A new image was then fed to the classifier in order to test its efficiency. Within the time frame of the thesis, the algorithm was partially translated to a hardware description using VHDL as a base descriptor. The proficiency of the hardware implementation was noted and the result exported to MATLAB for further processing. A hybrid model was created, in which the pre-processing steps were computed in FPGA and a classification performed in MATLAB. The outcome of the thesis shows that HOG is a very efficient and effective way to classify and differentiate different objects within an image. Given its efficiency, this algorithm may even be extended to video.
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Books on the topic "Image processing FPGA"

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Bailey, Donald G. Design for Embedded Image Processing on FPGAs. John Wiley & Sons (Asia) Pte Ltd, 2011. http://dx.doi.org/10.1002/9780470828519.

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Paik, Soumi. Design & Implementation of Digital Image Processing using FPGA: FPGA-based digital image processing. LAP LAMBERT Academic Publishing, 2011.

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Roome, Kerry. Image Processing Design Using Xilinx FPGA : Easy Guide with Examples for Beginners: Document Image Processing Systems. Independently Published, 2021.

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Avie, Venita. Tutorial on the Development of Image Processing Systems : with Xilinx Devices: Fpga Video Processing Tutorial. Independently Published, 2021.

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Antonik, Piotr. Application of FPGA to Real‐Time Machine Learning: Hardware Reservoir Computers and Software Image Processing. Springer, 2019.

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Antonik, Piotr. Application of FPGA to Real‐Time Machine Learning: Hardware Reservoir Computers and Software Image Processing. Springer, 2018.

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Image Processing Using FPGAs. MDPI, 2019. http://dx.doi.org/10.3390/books978-3-03897-919-7.

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Bailey, Donald G. Design for Embedded Image Processing on FPGAs. Wiley & Sons, Incorporated, John, 2011.

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Bailey, Donald G. Design for Embedded Image Processing on FPGAs. Wiley & Sons, Limited, John, 2011.

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Design for Embedded Image Processing on FPGAs. Wiley & Sons, Incorporated, John, 2023.

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Book chapters on the topic "Image processing FPGA"

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He, Xinxin, and Linbo Tang. "FPGA-Based High Definition Image Processing System." In Wireless and Satellite Systems. Springer International Publishing, 2019. http://dx.doi.org/10.1007/978-3-030-19156-6_20.

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Yuan, Haohao, Jianhe Zhou, and Suqiao Li. "FPGA-Based Image Acquisition System Designed for Wireless." In Intelligent Information Processing VI. Springer Berlin Heidelberg, 2012. http://dx.doi.org/10.1007/978-3-642-32891-6_47.

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Wiatr, Kazimierz. "Dedicated hardware processors for a real-time image data pre-processing implemented in FPGA structure." In Image Analysis and Processing. Springer Berlin Heidelberg, 1997. http://dx.doi.org/10.1007/3-540-63508-4_107.

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Cai, YuXin, ZhiGuo Yan, Jia Yang, and Bo Zhao. "Research on Image Feature Processing Based on FPGA." In Application of Intelligent Systems in Multi-modal Information Analytics. Springer International Publishing, 2020. http://dx.doi.org/10.1007/978-3-030-51556-0_66.

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Kasik, Vladimir, Martin Cerny, Marek Penhaker, Václav Snášel, Vilem Novak, and Radka Pustkova. "Advanced CT and MR Image Processing with FPGA." In Intelligent Data Engineering and Automated Learning - IDEAL 2012. Springer Berlin Heidelberg, 2012. http://dx.doi.org/10.1007/978-3-642-32639-4_93.

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Rupani, Ajay, Sayamuddin Ahmed Jilani, F. H. A. Shibly, and Tanupriya Choudhury. "FPGA Implementation of Image Processing Filters using IoT." In Innovations in Cyber Physical Systems. Springer Singapore, 2021. http://dx.doi.org/10.1007/978-981-16-4149-7_36.

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Nascimento, José, and Mário Véstias. "FPGA Compressive Sensing Method Applied to Hyperspectral Imagery." In Signal and Image Processing for Remote Sensing, 3rd ed. CRC Press, 2024. http://dx.doi.org/10.1201/9781003382010-21.

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Al-Shamma, Omran, Mohammed A. Fadhel, and Haitham S. Hasan. "Employing FPGA Accelerator in Real-Time Speaker Identification Systems." In Recent Trends in Signal and Image Processing. Springer Singapore, 2019. http://dx.doi.org/10.1007/978-981-13-6783-0_12.

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Wang, Mingyu, Yan Han, Rui Wang, Xiaopeng Liu, and Yuji Qian. "FPGA-Based Image Processing for Seamless Tiled Display System." In Proceedings of International Conference on Soft Computing Techniques and Engineering Application. Springer India, 2013. http://dx.doi.org/10.1007/978-81-322-1695-7_52.

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Samanta, Swagata, Soumi Paik, Shreedeep Gangopadhyay, and Amlan Chakrabarti. "Processing of Image Data Using FPGA-Based MicroBlaze Core." In High Performance Architecture and Grid Computing. Springer Berlin Heidelberg, 2011. http://dx.doi.org/10.1007/978-3-642-22577-2_32.

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Conference papers on the topic "Image processing FPGA"

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Atef, Benhaoues, Rabehi Abdelhalim, Souahlia Abdelkerim, and Yacine Djeghader. "FPGA Implementation of Flexible Architecture for Image Processing." In 2024 International Conference on Telecommunications and Intelligent Systems (ICTIS). IEEE, 2024. https://doi.org/10.1109/ictis62692.2024.10893969.

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Tsai, Lifen, Chin Ta Chen, Chihchung Yang, et al. "FPGA-based image signal processing CEPST module design." In Second International Conference on Frontiers of Applied Optics and Computer Engineering (AOCE 2025), edited by Gefeson Mendes Pacheco, Dayan Liu, and Bikash Nakarmi. SPIE, 2025. https://doi.org/10.1117/12.3059932.

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Chu, Xiaohui, Qiang Jiang, Zhichao Zhang, Tong Chen, Xin Wang, and Yi Yuan. "FPGA-Based Multi-Channel Image Acquisition and Processing System." In 2024 2nd International Conference on Signal Processing and Intelligent Computing (SPIC). IEEE, 2024. http://dx.doi.org/10.1109/spic62469.2024.10691624.

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Zhou, Hui, Xiaofeng Wang, YuJia Xie, et al. "FPGA-based Real-time High-resolution Image Processing for rocket on-board processing." In 2025 IEEE 17th International Conference on Computer Research and Development (ICCRD). IEEE, 2025. https://doi.org/10.1109/iccrd64588.2025.10963212.

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Dhanabal R, Sarat Kumar Sahoo, Bharathi V, Bh S. R. Phanindra Varma, D. Kalyan, and V. Divya. "FPGA based image processing unit." In 2015 IEEE 9th International Conference on Intelligent Systems and Control (ISCO). IEEE, 2015. http://dx.doi.org/10.1109/isco.2015.7282380.

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Balakhontsev, K. S., and M. V. Trigub. "DIGITAL IMAGE PROCESSING ON FPGA USING SLIDING WINDOW METHOD." In Actual problems of physical and functional electronics. Ulyanovsk State Technical University, 2024. http://dx.doi.org/10.61527/appfe-2024.108-111.

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Abstract:
The report examines the implementation features of a sliding window for digital image processing on the Altera Cyclone II EP2C20F484C7 FPGA and the Baumer CX series camera. The result will present ways to solve problems that arise when implementing a sliding window on the FPGA
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Siddiqui, Fahad Manzoor, Matthew Russell, Burak Bardak, Roger Woods, and Karen Rafferty. "IPPro: FPGA based image processing processor." In 2014 IEEE Workshop on Signal Processing Systems (SiPS). IEEE, 2014. http://dx.doi.org/10.1109/sips.2014.6986057.

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Hu, Yi, and Benyuan Chen. "FPGA-based image processing algorithm design." In IPMML 2024: 2024 International Conference on Image Processing, Multimedia Technology and Maching Learning. ACM, 2024. https://doi.org/10.1145/3722405.3722417.

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Rahangdale, Shammi, Paul Keijzer, and P. Kruit. "MBSEM image acquisition and image processing in LabView FPGA." In 2016 International Conference on Systems, Signals and Image Processing (IWSSIP). IEEE, 2016. http://dx.doi.org/10.1109/iwssip.2016.7502728.

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Li, Silong, Jiaming Qiu, Yijin Huang, Xiaoying Tang, and Tao Ye. "An FPGA-based edge computing and accelerating platform for fast diabetic retinopathy diagnosis." In Image Processing, edited by Ivana Išgum and Olivier Colliot. SPIE, 2023. http://dx.doi.org/10.1117/12.2653021.

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