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1
Ouma, Dennis Okumu. "Optimal design of channel doping for fully depleted SOI MOSFETs." Thesis, Massachusetts Institute of Technology, 1995. http://hdl.handle.net/1721.1/37032.
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Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1995.<br>Includes bibliographical references (leaves 87-89).<br>by Dennis Okumu Ouma.<br>M.Eng.
2
Banyai, William Charles. "Optical nonlinearities in semiconductor doped glass channel waveguides." Diss., The University of Arizona, 1988. http://hdl.handle.net/10150/184505.
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The nonlinear optical properties of a semiconductor-doped glass (SDG) channel waveguide were measured on a picosecond time-scale; namely, fluence-dependent changes in the absorption and the refractive index as well as the relaxation time of the nonlinearity. Slower, thermally-induced changes in the refractive index were also observed. The saturation of the changes in the absorption and the refractive index with increasing optical fluence is explained using a plasma model with bandfilling as the dominant mechanism. The fast relaxation time of the excited electron-hole plasma (20 ps) is explained using a surface-state recombination model. A figure of merit for a nonlinear directional coupler fabricated in a material with a saturable nonlinear refractive index is presented. The measured nonlinear change in the refractive index of the SDG saturates below the value required to effect fluence-dependent switching in a nonlinear directional coupler. Experiments with a channel-waveguide directional coupler support this prediction. However, absorption switching due to differential saturation of the absorption in the two arms of the directional coupler was observed.
3
Sundararajan, Abhishek. "A STUDY ON ATOMICALLY THIN ULTRA SHORT CONDUCTING CHANNELS, BREAKDOWN, AND ENVIRONMENTAL EFFECTS." UKnowledge, 2015. http://uknowledge.uky.edu/physastron_etds/27.
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We have developed a novel method of producing ultra-short channel graphene field effect devices on SiO2 substrates and have studied their electrical transport properties. A nonlinear current behavior is observed coupled with a quasi-saturation effect. An analytical model is developed to explain this behavior using ballistic transport, where the charge carriers experience minimal scattering. We also observe multilevel resistive switching after the device is electrically stressed. In addition, we have studied the evolution of the electrical transport properties of few-layer graphene during electrical breakdown. We are able to significantly increase the time scale of break junction formation, and we are able to observe changes occurring close to breakdown regime. A decrease in conductivity along with p−type doping of the graphene channel is observed as the device is broken. The addition of structural defects generated by thermal stress caused by high current densities is attributed to the observed evolution of electrical properties during the process of breakdown. We have also studied the effects of the local environment on graphene devices. We encapsulate graphene with poly(methyl methacrylate) (PMMA) polymer and study the electrical transport through in situ measurements. We have observed an overall decrease in doping level after low-temperature annealing in dry-nitrogen, indicating that the solvent in the polymer plays an important role in doping. For few-layer encapsulated graphene devices, we observe stable n−doping. Applying the solvent onto encapsulated devices demonstrates enhanced hysteretic switching between p and n−doped states.
4
Shin, Nara [Verfasser], Karl [Gutachter] Leo, Stefan [Gutachter] Mannsfeld, and Sebastian [Gutachter] Reineke. "Enhancement of n-channel Organic Field-Effect Transistor Performance through Surface Doping and Modification of the Gate Oxide by Aminosilanes / Nara Shin ; Gutachter: Karl Leo, Stefan Mannsfeld, Sebastian Reineke." Dresden : Technische Universität Dresden, 2019. http://d-nb.info/1230578196/34.
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Lemoigne, Pascal. "Simulation de la variabilité du transistor MOS." Thesis, Aix-Marseille 1, 2011. http://www.theses.fr/2011AIX10214/document.
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L’augmentation de la densité d’intégration des circuits intégrés nous a amené à étudier, dans le cadre du développement de la technologie CMOS 45 nm, les sources de variabilité inhérentes aux procédés de fabrication utilisés pour ce nœud technologique, et à en déterminer les composantes principales,dans le but ultime de permettre la simulation précise de l’impact de la variabilité technologique à la fois au niveau transistor et circuit. Après un état de l’art des sources de variabilité du transistor MOS et des moyens de simulation associés,ce travail s'est orienté sur les fluctuations d'un facteur technologique difficilement accessible à la mesure statistique qu'est le dopage canal. Ensuite le nœud 45 nm a été étudié expérimentalement via un plan d'expériences.Ceci a permis de connaitre les variations naturelles des facteurs technologiques mais surtout les sensibilités des performances électriques vis-à-vis de ces facteurs.Nous avons pu ainsi identifier les causes prépondérantes de variabilité dues au procédé.Enfin, nous proposons d’améliorer la prise en compte des déviations des facteurs process dans les simulations Monte-Carlo et pire-cas appliquées aux modèles compacts au regard de ces observations expérimentales<br>Continuous improvement in integrated circuits density of integration lead us to study process-induced variations in the framework of the 45 nm node, and to determine their principal contributions with the ultimate goal being to allow an accurate simulation of both transistor and circuit level variability. This work starts with a study of the state of the art of variability sources of the MOS transistor and associated simulation means. Then it focuses on the fluctuations of the channel doping, which is a difficult factor to measure statistically.After that we study the 45 nm node through a design of experiment which let us learn about natural variations of process factors but mostly about electrical performances sensitivity to those factors.Thanks to that we could identify major causes of process-induced variability at this stage of this node development. At last, with respect to those experimental results, we propose to enhance the taking in account of process variations in Monte-Carlo and corner simulations applied to compact models
6
Honoré, Jean-Charles. "Contribution à l'optimisation d'architectures de transistors MOS fortement submicroniques." Grenoble INPG, 1994. http://www.theses.fr/1994INPG0168.
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Ce memoire est consacre a l'optimisation de transistors fortement submicroniques. Apres avoir expose les effets physiques limitant la reduction des dimensions, l'analyse des differentes architectures de transistors en concurrence nous a permis de degager celles offrant le meilleur compromis entre la simplicite de realisation et les performances les plus elevees. La caracterisation detaillee des differentes variantes technologiques (canal, drain, oxyde de grille) des transistors cmos 0,25 m realises dans le cadre de cette etude a permis de definir des points de fonctionnement pour une future filiere cmos 0,25 m. Une methode d'optimisation du canal, basee sur des simulations numeriques a courant de blocage constant fut proposee et appliquee dans un premier temps a des nmos 0,2 m avec et sans ldd et differents parametres geometriques (profondeur de jonction, epaisseur d'oxyde de grille). A l'aide de cette methode, nous avons egalement etudie l'impact des differents profils de dopage du canal sur les caracteristiques electriques des transistors (pente en faible inversion, niveaux de courant, capacite de jonction, estimateur de vitesse des circuits, etc). Puis dans un second temps l'optimisation a ete appliquee a deux types de profil de dopage du canal d'un nmos 0,12 m avec extension de drain, l'un implante conventionnellement et l'autre en creneau (psd). La comparaison des deux optima obtenus a montre les avantages potentiels des profils en creneau dans le domaine fortement submicronique. De plus une optimisation du drain a permis la mise en evidence d'une taille optimale d'espaceur pour un nmos 0,12 m avec extension de drain. Enfin nous avons termine par une etude de sensibilite de l'angle d'implantation du drain d'un nmos 0,2 m avec latid, qui nous a montre les avantages et limites de cette architecture et mis en evidence l'existence d'un angle d'implantation optimal de l'ordre de 45
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Benistant, Francis. "Études d'architectures NMOS 0,10 µm réalisées à partir d'implantations d'ions lourds." Grenoble INPG, 1996. http://www.theses.fr/1996INPG0048.
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La realisation de transistors mos de longueur de grille 0,10 m se heurte aux effets de canal court. Afin de conserver un comportement identique a celui d'un transistor a canal long, il est necessaire de reduire ces effets de canal court. Cette reduction passe par l'optimisation du profil de dopage dans le canal, qui doit etre retrograde. Un tel profil de dopage est obtenu par implantation d'ions de masse atomique beaucoup plus grande que le bore. Ainsi, l'indium et le gallium ont ete utilises pour doper le canal. Dans une premiere partie, l'implantation, la diffusion et l'activation de ces impuretes sont etudies, ainsi que l'influence du type de profil de dopage dans le canal sur le fonctionnement electrique du mos. La realisation de transistors mos ultra-submicroniques demande des oxydes de grille de plus en plus fins, qui necessitent des methodes de caracterisation nouvelles. Certaines de ces methodes sont developpees dans cette premiere partie. Dans la seconde partie, des transistors nmos de longueur de grille 0,10 m realises avec des ions lourds (indium et gallium) dans le canal et dans les poches sont compares a des transistors dopes avec du bore. Certains dispositifs ont ete optimises par plan d'experiences. La reduction des effets de canal court grace a un dopage retrograde dans le canal est largement mis en evidence. Enfin, le dernier chapitre donne les perspectives technologiques pour les transistors mos de longueur de grille 0,10 m et en deca
8
Szelag, Bertrand. "Étude des propriétés physiques et electriques de transistors mos fortement submicroniques." Grenoble INPG, 1999. http://www.theses.fr/1999INPG0022.
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La reduction des dimensions des transistors mos fait apparaitre des effets nefastes au bon fonctionnement des composants electroniques. L'objectif de ce travail de these est d'etudier les proprietes physiques et electriques des mosfets fortement submicroniques. Les longueurs de grille minimum utilisees au cours de cette etude sont de 75nm. Dans le premier chapitre, nous rappelons les principes de fonctionnement des transistors mos en introduisant les effets lies a la reduction des dimensions. Le second chapitre est entierement dedie aux effets de canaux courts. La tension de seuil est etudiee en fonction de nombreux parametres. Nous presentons une analyse fine de l'effet de canal court inverse a partir de mesures effectuees a basse temperature et en determinons l'origine. Enfin, nous presentons un phenomene original d'augmentation de la transconductance avec la polarisation de substrat. Le troisieme chapitre traite des effets de porteurs chauds. Nous analysons en detail les courants de grille et de substrat et presentons des resultats relatifs au vieillissement des composants. Enfin, le phenomene d'emission de photons est analyse. Le quatrieme chapitre presente une etude comparative des methodes d'extraction de la longueur effective de canal et des resistances serie. Nous proposons certaines ameliorations permettant d'utiliser ces methodes pour les composants fortement submicroniques. Le cinquieme chapitre est un travail de caracterisation electrique de transistors avances realises avec differentes architectures. Nous comparons un dopage conventionnel obtenu par implantation de bore a un dopage retrograde realise par implantation d'indium.
9
Brut, Hugues. "Contribution à la modélisation et à l'extraction des paramètres de tension de seuil, de résistance série et de réduction de longueur dans les transistors MOS submicroniques." Grenoble INPG, 1996. http://www.theses.fr/1996INPG0192.
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La conception des circuits integres a l'aide de simulateurs de type spice, necessite l'elaboration de modeles physiques, precis et simples. Pour cela, une bonne comprehension du comportement des dispositifs est indispensable. Par ailleurs la reduction constante des dimensions de ces dispositifs entraine l'apparition de nouveaux phenomenes physiques qu'il est primordial d'isoler et de caracteriser d'un point de vue experimental, afin d'en faire une modelisation aussi proche que possible de la realite. C'est dans ce cadre de recherche que s'inscrit ce memoire. Les dispositifs etudies ici sont les transistors metal oxyde semiconducteur, largement utilises dans les circuits integres de type numerique. Les modeles et les procedures d'extraction directes developpes sont appliques sur un large panel de technologies allant de 1. 2 m a 0. 1 m. Apres un bref rappel du fonctionnement des transistors mos et des problemes technologiques et de modelisation lies aux dimensions reduites des dispositifs (chapitre 1), trois parametres fondamentaux sont traites: la tension de seuil, la resistance serie et la longueur de canal effective. Dans le chapitre 2, la modelisation de la tension de seuil et l'extraction des profils de dopage transverses sur les transistors a canaux longs sont abordes. Le chapitre 3 est ensuite consacre a la modelisation de la tension de seuil et a l'extraction des profils de dopage lateraux dans les transistors a canaux courts. Dans cette partie, sont notamment decorreles l'effet canal court classique associe au partage de charge et l'effet canal court inverse relatif a une non homogeneite des profils de dopage lateraux. Enfin, le chapitre 4 est dedie a l'etude de la resistance serie et de la longueur de canal effective. En particulier, l'evolution de ces deux parametres avec la polarisation de grille, ainsi que sa modelisation, sont traites dans le cas de transistors ayant des regions source et drain a zone faiblement dopees (ldd)
10
Fu-Min, Wang, and 王富民. "Investigation of AlGaN/GaN Doping-Channel High Electron Mobility Transistors." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/75941597127919252758.
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碩士<br>國立高雄師範大學<br>電子工程學系<br>103<br>Investigation of AlGaN/GaN Doping-Channel High Electron Mobility Transistors
Fu-Min Wang* Jung-Hui Tsai**
Department of Electronics, National Kaohsiung Normal University, Kaohsiung, Taiwan, R.O.C
Abstract
In this dissertation, we will fabricate and investigate the impact of doping channel on the AlGaN/GaN doping-channel high electron mobility transistors, and the influence of doped thickness on AlGaN/GaN doping-channel high electron mobility transistors will be included. The structures were designed as follows:
(1) AlGaN/GaN doping-channel high electron mobility transistor with channel doping region thickness of 20 nm (called Device A).
(2) AlGaN/GaN high electron mobility transistor without GaN doping-channel layer (called Device B).
(3) AlGaN/GaN doping-channel high electron mobility transistor with a channel doping region thickness of 19.5, 19, 17.5, 15, 10, and 5 nm, respectively, and with a spacer close to the AlGaN/GaN heterojunction of 0.5, 1, 2.5, 5, 10, and 15 nm, respectively (called Devices C, D, E, F, G, and H).
The device (Device A) was fabricated by metal-organic chemical vapor deposition system on a sapphire substrate. The experimental results exhibit a maximum drain saturation current of 506.9 mA/mm and a maximum transconductance of 52.475 mS/mm. Also, we will simulate the DC performance of device A with doping channel according to the experimental data. The simulated characteristics are close to the experimental results by choosing the proper parameters.
Simulation results show that the 2DEG concentration of the device A is higher than the device B without the doping-channel layer. The doping channel will enable the 2DEG concentration to increase. However, the impurity scattering of carriers in the doping channel will lead to the electron mobility to decrease. The results show that the device A with a doping channel has poor output saturation current, transconductance, gate leakage current, breakdown voltage, and high-frequency characteristics. In addition, the doping layer of devices C, D, E, F, G, and H are away from the 2DEG. It can decrease the effect of impurity scattering. The result exhibits that the DC and high-frequency characteristics of the devices F, G, and H are better than the device B. In the devices F, G, and H, the 2DEG carrier concentrations are 1.158 × 1020, 1.155 × 1020, and 1.154 × 1020 cm-3, the maximum output currents are of 672, 682, and 689.7 mA/mm, and transconductance are 84.4, 87, and 89.4 mS/mm, respectively. Furthermore, the unity gain cut-off frequencies are 17.8, 18.1, and 18.3 GHz, and maximum oscillation frequencies are 28.3, 29.1, and 29.2 GHz respectively.
* Author
** Advisor
KEYWORDS : AlGaN/GaN, high electron mobility transistor, doping channel, impurity scattering
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Chao, Yi-Ting, and 趙怡婷. "Investigation of channel profile on the performance of InGaP/InGaAs pseudomorphic doping-channel field-effect transistors." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/67388089979246328959.
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碩士<br>國立高雄師範大學<br>電子工程學系<br>103<br>In this dissertation, two sets of InGaP/InGaAs pseudomorphic doping-channel field-effect transistors (DCFETs), doped by various In mole fraction in InGaAs channel, were analyzed and discussed. Through the different arrangement of channels, the device characteristics including the energy band diagrams, distribution of carrier, DC and microwave performance are investigated. Simultaneously, each of the studied devices show different device characteristics. We will study and make some inclusions at the end of this thesis. However, all the devices exhibit some good characteristics, such as high turn-on voltage, low leakage current, high current density, large swing, and high as well as linear transconductance. The studied devices show a great promise for high-speed, and high-frequency applications.
First, three kinds of DCFETs, including GaAs/In0.1Ga0.9As/In0.2Ga0.8As (device A), In0.2Ga0.8As/In0.1Ga0.9As/GaAs (device B), and In0.1Ga0.9As (device C) doping channels, are studied as the total thickness of multiple channels is fixed at constant. Due to the high barrier and good carrier confinement, the device B shows a maximum drain saturation current of 52.9674 mA and a maximum transconductance value of 303.067 mS/mm. Compared with device A, though the conduction band discontinuity (ΔEc) at InGaP/In0.2Ga0.8As heterojunction in the device B is larger than that at InGaP/GaAs junction in the device A, the confinement effect for channel electrons in the device A is still good attributed to the sum of ΔEc values at three triple junctions. Moreover, in device A, a gate turn-on voltage of 0.9887V, a breakdown voltages of -10.51V, and a threshold voltages of -0.9V are obtained at equilibrium. However, the device C shows the best microwave characteristic among of the three devices. Second, the characteristics of InGaP/In0.1Ga0.9As (device C), InGaP/GaAs (device D), and InGaP/In0.2Ga0.8As (device E) DCFETs are discussed. Three kinds of DCFETs are studied as the thickness of channels is the same. Due to the highest barrier heights of the InGaP/In0.2Ga0.8As discontinuities and the best channel carrier confinement capability, the device E shows the best properties, including a maximum drain saturation current of 53.6875 mA, a maximum transconductance value of 294.576 mS/mm, and the good microwave properties in the three devices. Finally, we will make some conclusions to clarify the differences between these devices.
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Lin, K. W., and 林坤緯. "Investigation of InGaP/InGaAs/GaAs Step-Compositioned Doping-Channel Field-Effect Transistor." Thesis, 1997. http://ndltd.ncl.edu.tw/handle/26060909650930207025.
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碩士<br>國立成功大學<br>電機工程學系<br>85<br>In this thesis, we propose a novel structure of In0.49 Ga0.51 P/In GaAs/GaAs step-compositioned doped-channel field-effect transistor (SCDCFET). Due to the presence of V-shaped like energy band formed by the step-compositioned doped-channel structure, a large current density, a large gate voltage swing with high average transconductance and a high breakdown voltage are obtained.
The physical properties of the SDCCFET are investigated in detailed experimentially and theoretically. In theoretically, we can clearly find the distribution of wave functions and electron density in the In GaAs V-shaped like channel. In addition, compared with triangle structure, the modulation of threshold voltage is obtained, too.
Based on the theoretical analysis, the properties of each layer and the characteristics of interface may be obtained. This can improve the device performance.
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Lee, Jian-Dong, and 李建東. "The Characteristics of Junctionless Accumulation-Mode Transistor with Localized Anti-channel Doping." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/3w629r.
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碩士<br>逢甲大學<br>電子工程學系<br>105<br>Junctionless FETs (JLFETs) suffer an optimum design (or trade-off) on the channel doping to gain high drain current and low off current. This because high channel doping can get the high driving current, but it suffers the higher device leakage (off) current. In the other hand, the device with low channel doping, the devices will reduce the driving current due to the higher channel resistance and parasitic source/drain resistance. This thesis studies the characteristics and performance improvements of JLFET with and without localized anti-channel doping, different implanted tilt angles (30º, 45º and 60º), and the effects of JLFET with spacer capping. The JLFET structure is TiN/Al2O3/Poly-Si. The device channel material is the polysilicon.
This work mainly studies the device electrical characteristics, including threshold voltage (Vth), subthreshold swing (S.S.), drain induced barrier lowering (DIBL) and device ON/OFF ratio (ION/IOFF). In addition, the short channel effects of JLFET with different gate length are also investigated. The experiment results of JLFET with anti-channel doping are divided into two parts. The first part is the comparison of the JLFET with and without anti-channel doping. The second part is the comparison of JLFET with different implanted tilt angles of 30°, 45° and 60°. In addition, the JLFET with spacer capping and the short channel effect are also investigated.
In the results of the JLFET with anti-channel doping, the S.S., DIBL and device driving current of JLFETs are decrease, but the current ratio of ION/IOFF is increase. For the results of device with different implanted tilt angles of anti-channel doping, the S.S. and DIBL of p-type JLFET are decrease with increasing the tilt angle, but the current ratio of ION/IOFF is increase. Additionally, the driving current is decrease with increasing the implanted tilt angle. For the investigation of the JLFET with spacer, the S.S. and DIBL of the devices are decrease, but the current ratio of ION/IOFF is increase and the driving current degradation is lower. For the JLFET with spacer, the decrease of the current ratio (ION/IOFF) of JLFET with larger gate width is lower than that of the device with smaller gate width. Finally, the short channel effects of JLFET with anti-channel doping, different implanted tilt angles and spacer capping are compared. According to the experimental results, the short channel effect of JLFET with localized anti-channel doping is lower. In addition, the implanted tilt angle of 30º and the device with spacer capping are beneficial for suppressing the short channel effect.
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Wang, Shi-Hao, and 王士豪. "Study of UTBB-SOI MOSFET device reliability with various concentration of channel doping." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/74491718024098075819.
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碩士<br>國立高雄師範大學<br>電子工程學系<br>101<br>As the MOSFET devices have been scaling down, short channel effects become serious problems for traditional bulk MOSFETs. As the result, alternative MOSFET structure has been proposed. Lightly doped drain and Halo implantation are the most popular methods to suppress short channel effect.
In this thesis, the ultra-thin-body and box silicon-on-insulator devices with above dopant conditions were investigated and the characteristic and the reliability of device with various dopant concentrations were discussed. Hot carrier injection was used to test reliability in this work. It is observed that the drain current, threshold voltage and gate leakage current would be affected due to the difference of dopant concentration. The device with high dose has batter characteristic such as higher drain current. However, the degradation is more serious for the high dose device after hot carrier injection stress.
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Tseng, Huang-Wen, and 曾皇文. "The Study of Channel Doping and Hydrogenation Effects on Polysilicon Thin Film Transistors." Thesis, 1993. http://ndltd.ncl.edu.tw/handle/77528471304542503129.
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碩士<br>國立交通大學<br>電子研究所<br>81<br>With regard to the unpassivated poly-Si TFTs with undoped
channel, the magnitude of the threshold voltage is greater than
5V and the leakage current is usually not available. Thus the
necessary channel doping and hydrogenation are required to
reduce threshold voltages to acceptable values. In this thesis
, we have studied the characteristics of the p-channel TFTs
with boron and arsenic implantation doses before and
after hydrogenation. From the experimental results, it is seen
that the thicker films of 86nm exhibit the characteristics just
as those we have predicted that the threshold voltage
increases with the channel arsenic dose and decreases with
the channel boron dose for properly channel implantation.
However, the thinner films of 26nm show the features of
passivation for very lightly channel implantation. In addition,
it is seen that the increase of the Source/Drain resistance
after hydrogenation becomes more significant as the thickness
of the polysilicon is scaled down. Therefore, though the TFT
with thinner channel thickness(26nm) exhibits better
characteristics, its on current is limited by the drastically
increased Source/Drain resistance after hydrogenation. In view
of the reason mentioned aboved, it is recommended that the
length of Source/Drain region should be decreased in order to
minimize the influence of Source/Drain resistance on electrical
characteristics.
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Shih, Syuan, and 施璇. "Study of Bridged-Grain Poly-Si Thin-Film-Transistors with Patterned-Channel Doping." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/35373871013508206661.
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碩士<br>國立暨南國際大學<br>電機工程學系<br>104<br>In this thesis, we focus on the study of bridged-grain polycrystalline-silicon thin-film-transistors with patterned-channel doping. The patterned doping regions in channel were fabricated by ion implantation through the PMMA, patterned with thermal nanoimprint lithography. Then the thin-film-transistors were fabricated by the conventional TFTs process. Finally, the electrical characteristics of proposed TFTs were investigated.
In our results, the bridged-grain Poly-Si TFTs with 400/800 and 400/400 nm patterned-channel structures in all patterns (dot, line, dash) were fabricated successfully. The proposed Poly-Si TFTs show lower threshold voltage, higher ON/OFF ratio, better subthreshold swing, higher field-effective mobility, and higher drain current than that with a conventional channel. This technique will be suitable for the fabrication of high-performance poly-Si TFTs at low cost in the future.
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Lai, Chun-ming, and 賴俊銘. "The Investigation of Characteristic and Reliability for UTBBSOI with different concentration of channel doping." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/79435911855303496184.
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碩士<br>國立高雄大學<br>電機工程學系碩士班<br>101<br>Lightly doped drain and halo implantation had been one of the methods used to
suppress short channel effect, in this thesis, we used ultra thin body and box silicon on insulator device which have the structure above description, we investigate the characteristic and the reliability of device with different dopant concentration at different temperatures, observe the situation and the mechanism of the device degradation from positive bias temperature instability and hot carrier effect. We found that different concentration of channel doping has a significant impact on the characteristics and reliability of the device, which contains the increase of gate leakage current, turn on current, carrier mobility, and so on. From the result of theexperiment we can found although higher dopant concentration device has batter characteristic, but has much worse reliability of hot carrier effect and positive bias temperature instability when stress by temperature or electrical voltage. Not only the
gate leakage current become larger, but also the characteristics of device has more serious degradation.
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Liu, Cheng, and 劉政. "Effects of Mg doping on Double Channel Layer AP-PECVD Fabricated a-IGZO Thin Film Transistors." Thesis, 2019. http://ndltd.ncl.edu.tw/handle/67meh8.
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碩士<br>國立交通大學<br>國際半導體產業學院<br>107<br>a-IGZO has been proved to be a suitable material for the channel layer in a thin film transistor, showing high mobility even in low temperature fabrication, device electrical characteristic exceeds a-Si or other metal oxide semiconductor materials. Ever since it was first discovered to show semiconductor like characteristic in 2004, researches around the world has been conducted to further improve device performance. In this work we fabricate bottom gate top contact TFT, depositing a-IGZO as channel layer by AP-PECVD. A double channel layer is used in this work, with Mg dopant added in the bottom layer. This research focus on how the Mg doping concentration in the bottom layer affects device electrical characteristic. We get a best device performance with proper Mg doping concentration of 5%, showing highest mobility, lowest threshold voltage, and nearly 108 in Ion/off. A suitable doping concentration can lower interface defect density and affect grain size, which both leads to a better device performance. However, device performance show sign of degradation with excess dopant concentration.
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HUANG, Shao-Jia, and 黃紹嘉. "Study of Doping Layered-WSe2 Material as Field Effect Transistor Channel for Source/Drain Contact Resistance Reduction." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/04091130890836214975.
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碩士<br>國立臺灣師範大學<br>光電科技研究所<br>104<br>Recently, two dimensional transition metal dichalcogenides (TMDs) compounds have drawn much interest due to their potential in TFT channel application than Graphene which without bandgap. Among these 2D materials, p-type WSe2 is particularly attractive. However, precise doping of WSe2 is difficult due to the absence of a controllable doping technique. In this paper, a controllable WSe2 doping method by co-sputtering process followed by post selenization treatment is demonstrated. Using this technique, high acceptor doping concentration and good hole mobility were obtained. Low sheet resistance and contact resistance were obtained.
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Chen, Chia-Hsin, and 陳家新. "High Performance Amorphous Indium-Gallium-Zinc-Oxide Thin Film Transistor with Nano-Dot Doping and Back Channel Effect." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/66789436868335836540.
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碩士<br>國立交通大學<br>光電工程學系<br>99<br>With a high mobility (>10 cm2/Vs) than conventional amorphous silicon semiconductor and a low operating voltage (&lt; 5 V) and small sub-threshold voltage swing, amorphous In-Ga-Zn-O thin-film transistors (a-IGZO TFTs) draw a lot of attentions. However, when a-IGZO TFTs are developed for low-power consumption, high-frequency operating of circuit, improved electron mobility and a low parasitic capacitance are required. In this study, we used a novel, simple process to improve the mobility of the a-IGZO TFTs, and proposed an efficient manufacturing method to obtain a high carrier mobility of a-IGZO TFTs, called “nano-dot doping”. The influences of dot and doping concentrations on device performance are investigated. We applied the top gate and bottom gate structure to analyze and compare the different of electric characteristic to clarify the a-IGZO TFTs increase in carrier mobility mechanism. Self-organized polystyrene spheres with diameters of 200 nm are utilized to form a dot-like mask on the gate dielectric. Following a few simple process steps, the dot-like pattern is transferred to produce dot-like doping on the IGZO channel region. After using argon plasma treatment, the bared region of active layer became high conductivity region. Therefore, a nano dot-doping a-IGZO TFTs is completed. Self-aligned a-IGZO TFT is also realized to suppress the parasitic capacitance between gate and source/drain. With NDD process, the optimized electric characteristic of a-IGZO TFT was attained with field-effect mobility ~79cm2/(V-s), sub-threshold swing ~1V/dec., and on/off ratio ~106. Furthermore, we utilize ultraviolet rays to replace argon plasma and successfully demonstrate the effect of nano-dot doping.
In addition, this thesis found the carrier mobility significantly increase by silicon oxide (SiOx) capping. We presume that the oxygen in IGZO films be captured by silicon oxide and transfer to the oxide surface or bulk. Therefore the oxygen vacancy is created to dramatically increase the carrier concentration and leaded the mobility significantly improved. In this study, we propose a novel structure with capping silicon oxide layer onto the active layer of bottom-gate a-IGZO TFT to provide a powerful solution of enhancement of device performance that would not cause current leakage and performance degradation. In summary, the method of oxide capping layer is a simple and effective approach to fabricate a feasible metal oxide transistor.
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Mu, Shou-Chun, and 穆守駿. "Short-Channel Effects and Reliability of the Different LDD and Pocket Doping Concentration on Ultra Thin Body SOI Devices." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/27470713785967649769.
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碩士<br>明新科技大學<br>電子工程系碩士班<br>103<br>As process technology at progress, so that the element size increasingly miniature, let component reliability becomes more important, research is also an important indicator. In the case of miniature components, But also led to SCE(Short Channel Effects),DIBL(Drain-Induced Barrier Lowering),HCE(Hot Carrier Effect), Component reliability problems and so on like an extension, so we use the UTB SOI (Ultra Thin Body Silicon On Insulator, UTB SOI) to avoid latch door effect, and to reduce the leakage current component, and combined with the LDD (Light Doped Drain) to suppress hot carrier effects, and the Pocket(Pocket Implant) to improve the short channel effect element ; In this and we will use these two processes, the amount of doping and implantation of different concentrations in UTB SOI device, to explore the different level of doping concentration LDD and Pocket degree of influence on the electrical components and reliability.
The experimental results, p-FET high LDD doping element will have better electrical performance, Because of the higher amount of carrier diffusion doping reduce resistance characteristics, however, for the gate tunneling leakage current significantly increased cases, this is a higher doping elements have a more serious case of Eg lower (Band-to-band tunneling effect, BTBT) and direct tunneling gate oxide, the concentration of the similarity of the n-FET of the LDD and Pocket, Make two threshold voltage VT and leakage current IG similar, It can be observed that the relative corresponding relationship LDD and Pocket; In the SCE of the experimental results, highly doped n-FET because the amount of S/D and affect Pocket on threshold voltage degradation suppression, DIBL and S.S from the highly doped Pocket and the presence of LDD, have better performance; The reliability of results, high doping concentration in HCI and PBTI have better stability.
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Shin, Nara. "Enhancement of n-channel Organic Field-Effect Transistor Performance through Surface Doping and Modification of the Gate Oxide by Aminosilanes." Doctoral thesis, 2019. https://tud.qucosa.de/id/qucosa%3A35131.
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In this these, in order to enhance the n-channel organic field-effect transistor (OFET) performance, amino functionalized self-assembled monolayers (A-SAMs) which consist of amino groups, a well-known n-type dopant candidate, were introduced from the top of OFET surfaces and on the gate oxide surfaces. To obtain better understanding for optimization of OFET performances we attempted to elucidate the mechanism of surface doping and surface modification by A-SAMs. Both the surface doping and surface modification of the gate oxide approaches have individual pros and cons. One needs to take into account the surface energy properties of SAMs and the resulting OSC film structure and pick the most suitable method to introduce the SAM material to the OFET (either doping or oxide modification) in order to obtain optimized device performances. Our study strongly suggests that both surface doping and surface modification of the gate oxide with A-SAMs could enhance other semiconductor-based electronic device performances.:Abstract v
Chapter 1. Introduction 1
Chapter 2. Theoretical Background 7
2.1. Organic Semiconductors (OSCs) 8
2.1.1. Semiconducting properties of organic molecules 8
2.1.2. Charge Transport Mechanism in OSCs 10
2.2. Organic Field-Effect Transistors (OFETs) 18
2.2.1. Operation Principle 18
2.2.2. Device Geometry of OFETs 20
2.2.3. Contacts (metal/semiconductor junction) in OFETs 21
2.2.4. Dielectric material for OFETs 23
2.2.5. Current-Voltage Characteristics of OFETs 25
2.3. Dominant contributors to OFET Performance 32
2.3.1. Molecular structure and Orientation of OSCs 32
2.3.2. Dielectric/OSC Interface 33
2.3.3. OSC/Contact Interface (Contact resistance) 35
2.3.4. Shallow and deep traps 36
2.4. Strategies to improve OFET performance 37
2.4.1. Introducing dopants to OFETs 37
2.4.2. Modification of Gate Oxide Layer with SAMs 44
Chapter 3. Experimental 51
3.1. Device Fabrication 52
3.1.1. Device type I - Substrate/ODTMS/PTCDI-C8/Au 53
3.1.2. Device type II - Substrate/ODTCS/N2200 (PNDI2OD-2T)/Au 53
3.1.3. Device type III - Substrate/SAMs/PTCDI-C8/Au 54
3.2. Surface doping process 56
3.2.1. Surface dopant – Aminosilanes (A-SAMs) 56
3.2.2. Surface doping method 56
3.3. Characterization 59
3.3.1. Material characterization 59
3.3.2. Surface-wetting characterization - Contact angle measurement 61
3.3.3. Micro-structure characterization - Atomic Force Microscopy (AFM) 62
3.3.4. Surface potential characterization – Kelvin Probe Force Microscopy (KPFM) 63
3.3.5. Molecular Structure Characterization - Grazing Incidence Wide Angle X-ray Scattering (GIWAXS) 64
3.3.6. Electrical Characterization - Current-voltage (I-V) measurement 66
Chapter 4. Result and Discussion 69
4.1. Optimization of OFETs based on PTCDI-C8 and N2200 70
4.1.1. PTCDI-C8 OFETs 70
4.1.2. N2200 OFETs 72
4.1.3. Device measurement condition 75
4.2. Investigation of Surface doping mechanism of Aminosilanes 77
4.2.1. Surface doping effect depending on the dopant processing method 77
4.2.2. Surface doping effect for different types of organic semiconductors 80
4.2.3. Surface doping effect for different types of surface dopants 89
4.2.4. Surface doping effect for different OSC grain sizes 92
4.2.5. Surface doping effect for different OSC film thicknesses 103
4.2.6. Molecular structure of the doped films identified by GIWAXS 106
4.2.7. Stability of the surface doped OFETs 107
4.2.8. Summary 111
4.3. Modification of the gate oxide with various self-assembled monolayers 112
4.3.1. The surface property of SAM-treated substrates 112
4.3.2. The relation between the OSC morphology and the field-effect mobility 115
4.3.3. The origin of the threshold voltage shift 126
4.3.4. Memristive effects in PTCDI-C8 devices on ODTMS 133
4.3.5. Summary 137
4.4. Comparison of the surface doping and the modification of the gate dielectric 138
4.4.1. The reliability factor of OFETs 138
4.4.2. The threshold voltages and field-effect mobility of OFETs 141
4.4.3. Density of Interfacial trap sites and SAM induced mobile carriers 143
4.4.4. Summary 144
Chapter 5. Conclusion 145
Bibliography 148
List of Figures 158
List of Tables 166
List of Equations 167
Acknowledgment 168
Erklärung zur Eröffnung des Promotionsverfahrens 169
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Che-Yu, Lin, and 林哲佑. "Simulation and Analysis of High Performance Double-Channel Poly-Silicon Thin Film Transistor with RSD and Different Doping LDD Design." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/3dky58.
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碩士<br>逢甲大學<br>電子工程學系<br>106<br>With the progress of technology now, LCD has been inseparable with our lives. It’s current to a large number of applications in mobile phones, computers, televisions, LCD display screen and other electronic products. The polycrystalline silicon thin film transistor is one of the important electronic components.
The complex crystalline silicon thin film transistor has been developed in many aspects such as storage element, solar cell, active liquid crystal display and so on due to its high field effect mobility and driving current. However, the traditional complex crystalline silicon thin film transistor has the characteristics are not enough to copy with the new type of electronic products.
It is learned from previous discussions that the dual-channel structure can effectively enhance the driving current of the complex crystalline silicon thin film transistor. Although the high-performance dual-channel complex crystalline silicon thin film transistor can effectively reduce the leakage current, It has a considerable parasitic resistance generation. So we propose a dual-channel structure combined with different light doping to reduce the parasitic resistance of the polycrystalline silicon thin film transistor and increase the driving current.
In this study, we propose a new dual-channel combined uplift raised source/drain (RSD) and swabbing-light doped drain (LDD) poly-crystalline silicon thin film transistor (DCLDD-TFT). This structure by adding the uplift-type source pole structure (raised source/drain, RSD), we got the better component characteristics and higher conduction currents. The lower leakage current and switching current ratio can be obtained by the design of different-light-doped-drain (DLDD). From the simulation results, compared with the traditional components, the new design has a lower electric field and can effectively reduce the leakage current in addition to improve its unsatisfactory effect.
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Wu, Chun-Yi, and 吳俊毅. "Study on the Low-Temperature p-Channel Polycrystalline-Germanium Thin-Film Transistors with the Continuous Wave Laser Crystallization and Counter Doping." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/01271643781626016836.
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Huang, Ching-Yu, and 黃敬餘. "Study on the Characteristics of Low-Temperature p-Channel Polycrystalline-Germanium Thin-Film Transistors with the Excimer Laser Crystallization and Counter Doping." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/85fe8r.
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Hsu, Chia-Lin, and 許嘉麟. "Studies on the Effect of Al- and Ge-incorporation on ZrO2 Gate Dielectric and Effect of Channel Doping on Ge n-MOSFET." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/y2wz4y.
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碩士<br>國立交通大學<br>電子研究所<br>107<br>In this thesis, the properties of Al- and Ge-doped ZrO2 dielectric stacks on Ge devices are investigated thoroughly. It is found that the doping of Al suppresses the crystallization of ZrO2, resulting in the reduce of accumulation capacitance; however, it also reduces the leakage current and promotes the hysteresis performance without the deterioration of interface state density. In contrast, the Ge-doped samples exhibit similar performance as the samples with pure ZrO2. On the other hand, the effects of different structures and several Al doping concentrations with various post-metal annealing (PMA) temperatures are also discussed and evaluated, and the best condition is proposed and suggested.
In order to further understand the influence of the incorporation of Al into ZrO2 as gate dielectric, the samples with thicker physical thickness and higher PMA temperatures are fabricated. It is discovered that the doping of Al will increase the critical crystallization temperature and the onset crystallization thickness of ZrO2, which accounts for the retardation of crystallization.
Overall, the pure ZrO2 samples still exhibit better J_G-EOT behavior, while the Al-doped samples own lower leakage current. In addition, all the Al- and Ge- doped samples have better hysteresis than the pure ZrO2 ones without the deterioration of the interfacial layer.
Next, Germanium (Ge) n-MOSFETs with various channel doping concentration are fabricated, and the effects of channel doping are fully discussed and investigated. The overall electrical properties are evaluated, including transfer and output characteristics, the number of interface traps and border traps, and the channel mobility. In previously proposed researches, it is found that the on-current and mobility will severely degrade when the substrate doping concentration reaches 1e18. However, in this thesis, only slight deterioration of on-current and mobility is observed at the higher doping concentration, probably due to the Coulomb scattering of interface trap densities generated after implantation.
Then, for the samples with severe on-current and mobility degradation, the possible speculation and solution are proposed. it is suspected that the severe degradation may result from the extra Coulomb scattering caused by the defects generated at the interface after implantation with high energy. In addition, the quality of Ge wafer may also be a concern. On the other hand, it is discovered that the Coulomb scattering and the surface roughness scattering are more serious in Ge n-MOSFET compared to silicon. As a result, if the interface and substrate of Ge n-MOSFET can be improved more with appropriate thermal budget or high-quality wafer, it is possible to achieve better performance.
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Weng, Shuo-Yang, and 翁碩陽. "Study on the p-channel Polycrystalline-Germanium Thin-Film Transistors with Light Counter Doping and High-k Al2O3 Gate Dielectric via Continuous Wave Laser Crystallization." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/55ny3u.
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碩士<br>國立交通大學<br>電子研究所<br>107<br>The monolithic stacking technology was widely investigated for the three-dimensional integrated circuits (3-D ICs) because of the best alignment precision between the device levels and thus the highest packing density. Nevertheless, the major challenge for the monolithic stacking was to fabricate the high quality top active layers on the insulator with the low thermal budget to prevent the under-layered devices from the thermal degradation.
Germanium (Ge) has the advantages of much higher carrier mobility and lower melting point than silicon (Si) and can be expected to further promote the electrical characteristics of 3-D ICs. However, a high leakage current and poor electrical characteristics have been typically found for polycrystalline-germanium (poly-Ge) thin-film transistors (TFTs) since the hole concentration of Ge thin films resulting from the acceptor-like defects was extremely high owing to the poor crystallinity. The continuous wave laser crystallization (CLC) has been considered as a suitable approach to reduce these defects. In order to further overcome this problem, the counter-doping (CD) process with a suitable dose of n-type dopants was employed to convert the carrier type in Ge thin films. In this thesis, poly-Ge thin films via CLC and CD processes would be investigated and then we utilize high-k Al2O3 gate dielectric to improve gate controllability. Eventually, p-channel poly-Ge TFTs would be fabricated and characterized.
At first, CLC has been utilized to attain the high-quality poly-Ge thin films. The grain size of poly-Ge thin films could reach about 1.2 X 1.2 µm. Moreover, the hole concentration of Ge films was effectively reduced after CLC. On the other hands, Ge thin films could be successfully converted to n-type via the appropriate CD process of the phosphorus (P) ion implantation with a suitable dose and a subsequent furnace annealing. As a result, high quality n-type poly-Ge thin films could be performed by means of the combination of CLC and CD.
We discussed the impact of different concentrations of CD processes on p-channel poly-Ge TFTs and found that the Ge TFTs fabricated via CD with a P dose of 1 × 1013 cm-2 processes showed the transistor characteristics with the superior high hole field-effect mobility of 692 cm2/V-s and on/off current ratio of 3.3 × 103. Moreover, Ge TFTs by means of proper CD dose attained better performance due to a reduced Coulomb scattering. After finding the optimal condition of CD processes, we use the same CD condition and high-k Al2O3 gate dielectric to improve transistor characteristics with the high hole field-effect mobility of 636 cm2/V-s, the subthreshold swing of 278 mV/decade, and the on/off current ratio of 1.5×104 owing to larger oxide capacitance of Al2O3. Besides, the passivation of GeO2 could reduce the interface states and further improved the device performance. Therefore, the high-performance poly-Ge TFTs via the CLC with light CD and high-k Al2O3 gate dielectric demonstrated the future potential for the monolithic 3-D stacking applications.