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Journal articles on the topic 'Linear Feedback Shift Register (LFSR)'

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Published: 4 June 2021

Last updated: 16 June 2025

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Manuel, Ugalde-Franco Juan, Martinez-Gonzalez Ricardo Francisco, and Mejia-Perez Juan Francisco. "Linear Feedback Shift Register Genetically Adjusted for Sequence Copying." International Journal of Computer Science and Information Technology 15, no. 2 (2023): 27–37. http://dx.doi.org/10.5121/ijcsit.2023.15203.

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The present manuscript proposes a comparison between two types of shift registers; the first one, a traditional one with a linear feedback (LFSR); on the other corner, a register designed one register with genetically-controlled feedback loop (NLFGR). Being more traditional, the linear feedbacked register works as reference to offer comparison metrics, meanwhile the NLFGR is our research focus, since our proposal relies in its good features to replicate certain behaviours, with shorter parsing time than linear feedback shift register.

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Shin, Hwasoo, Soyeon Choi, Jiwoon Park, Byeong Yong Kong, and Hoyoung Yoo. "Area-Efficient Error Detection Structure for Linear Feedback Shift Registers." Electronics 9, no. 1 (2020): 195. http://dx.doi.org/10.3390/electronics9010195.

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This paper presents a novel error detection linear feedback shift register (ED-LFSR), which can be used to realize error detection with a small hardware overhead for various applications such as error-correction codes, encryption algorithms and pseudo-random number generation. Although the traditional redundancy methods allow the incorporation of the error detection/correction capability in the original LFSRs, they suffer from a considerable amount of hardware overheads. The proposed ED-LFSR alleviates such problems by employing the parity check technique. The experimental results indicate that the proposed ED-LFSR requires an additional area of only 31.1% compared to that required by the conventional LFSR and it saves 39.1% and 31.9% of the resources compared to the corresponding utilization of the hardware and time redundancy methods.

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Susaritha, M., and J. Senthilkumar. "Design and Analysis of High Performance FinFET-Based Linear Feedback Shift Register for Cryptography Applications." Journal of Nanoelectronics and Optoelectronics 19, no. 6 (2024): 588–99. http://dx.doi.org/10.1166/jno.2024.3613.

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Nowadays, all the elements of our surrounding is occupied by electronics. Electronics occupies major role on our day today life. Electronics device integration on a single chip enhances performance in terms of speed, low-power circuits, and area. Integration of VLSI provides better scalability and reliability. This research paper focused on the implementation of Linear feedback shift registers (LFSR) using FinFET techniques at the layout level for various applications, including cryptography. FinFETs are highlighted as a replacement for CMOS technology, offering advantages such as improved performance in terms of speed, low-power circuits, and area. Linear feedback shift registers are commonly used in digital systems and cryptography for generating pseudo-random sequences. The use of FinFET technology in the layout level suggests an interest in exploring advanced semiconductor technologies to enhance the performance of these circuits. The paper appears to cover different design methods of LFSRs, which could include aspects like circuit optimization, power efficiency, and reliability. The integration of electronics on a single chip, particularly with FinFET technology, is noted for its potential to provide better scalability and reliability. The first architecture is created using bulk CMOS techniques; whereas the second is constructed using two fin FinFET LFSRs. Using the Microwind designing tool, the third technique is developed with a 3-fin FinFET LFSR. It provides a solution for a novel FinFET architecture that implements LFSR. When comparing CMOS and FinFET circuit designs for LFSR, the latter achieves superior performance in terms of area and power efficiency. An analysis is conducted on the design techniques and performance of CMOS LFSR, 2 fin FinFET based LFSR, and 3 fin FinFET. According to the experimental findings, the CMOS-based LFSR uses 1.243 mW of power; the FinFET-based LFSR uses 90.47 μW, and the two fin FinFET LFRS uses 0.254 mW.

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Manju Bhargavi, K., and B. Sreekanth Reddy. "Low Power Linear Feedback Shift Register Using DY-CML." ECS Transactions 107, no. 1 (2022): 15545–54. http://dx.doi.org/10.1149/10701.15545ecst.

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A Linear Feedback Shift Register (LFSR) is a sequential shift register that cycles through a succession of binary values in a pseudo-random way using combinational logic. Pseudo-noise sequences, whitening sequences, and fast digital counters are some of the applications of LFSR. The design of a 4-bit LFSR employing CMOS, MOS Current-Mode Logic (MCML), and Dynamic Current-Mode Logic (DY-CML) approaches are shown in this paper. MCML has low power consumption and better performance. The disadvantage of MCML approach is that it has more static power dissipation due to the constant current source. In order to solve the issues of MCML approach, the DY-CML with a dynamic current source is used to design the LFSR. All designs are simulated using the Mentor graphics tool, which uses 90nm technology. This paper also includes a comparison of LFSR’s in terms of power, delay, and transistor count.

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Nguyen, Hai T., Giao N. Pham, Anh N. Bui, Binh A. Nguyen, Ngoc T. Le, and Hanh T. Pham. "Linear Feedback Shift Register and its Applications in Digital System Design." International Journal of Emerging Technology and Advanced Engineering 11, no. 11 (2021): 204–8. http://dx.doi.org/10.46338/ijetae1121_24.

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In digital system design, the Linear Feedback Shift Register (LFSR) is the queen of logic functions, and the design engineers can use LFSR in both hardware (HW) or software (SW) implementation. In this paper, LFSR will be discussed in its HW implementation via Hardware description language. In addition, the application of LFSR in of pseudorandom number generator (PRNG), direct sequence spread spectrum (DSSS), cyclic redundancy check (CRC) is also given. Keywords-- Digital system design, System on chip, ASIC digital design, Linear feedback shift register

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Tripathi, Sajal, Sharad Gupta, Shivanshu Pratap Singh, and Kamal Bhatia. "Design and Implementation of 32 Bit Linear Feedback Shift Register using FPGA." International Journal for Research in Applied Science and Engineering Technology 12, no. 5 (2024): 4844–49. http://dx.doi.org/10.22214/ijraset.2024.59217.

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Abstract: Shift register is a common device for generating signals and sequences. Usually register is the combination of flipflops.The shift register is of two types which are: linear and nonlinear. Various sequences including pseudorandom codes are generated by linear and nonlinear feedback shift registers, respectively. Linear feedback shift register (LFSR) is composed of dynamic or static master-slave flip-flop. Its characteristics are usually characterized by a characteristic polynomial. The twoinput XOR gate is used to calculate the characteristic polynomial of the maximum or near maximum length of the feedback function without rectifying the register.

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Aakanksha, Devrari, and Kumar Adesh. "Reconfigurable linear feedback shift register for wireless communication and coding." International Journal of Reconfigurable and Embedded Systems (IJRES) 12, no. 2 (2023): 195–204. https://doi.org/10.11591/ijres.v12.i2.pp195-204.

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Linear feedback shift register (LFSR) is the basic building block of the communication system used in different coding, error detection and correction codes, such as gold, low-density parity check (LDPC), polar, and turbo codes. There are simple shift register-based n-bit counters with a few XOR gates that behave pseudo-randomly. The LFSR is used in chip hardware for high-speed operations, error control, and the generation of pseudo-random numbers. The hardware chip design and performance estimation of the LFSR is the problem for specific communication system. The motivation of the work is to generate the Gold code sequence by the integration of two LFSR. The article proposes the hardware chip design and simulation of two 5-bit LFSR modules used for the gold sequence generator applicable for the communication systems. The novelty of the work is that the design is scalable and can be extended based on the requirements of the systems which is synthesized and experimentally verified on the Zynq-7000 field programmable gate array (FPGA) board. The concept of this design is programmable and can be extended to n-bit based on the applications. The work is supported, and formulated using very high speed integrated circuit hardware description language (VHDL) programming in Xilinx ISE 14.7 software.

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Devrari, Aakanksha, and Adesh Kumar. "Reconfigurable linear feedback shift register for wireless communication and coding." International Journal of Reconfigurable and Embedded Systems (IJRES) 12, no. 2 (2023): 195. http://dx.doi.org/10.11591/ijres.v12.i2.pp195-204.

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Linear feedback shift register (LFSR) is the basic building block of the communication system used in different coding, error detection and correction codes, such as gold, low-density parity check (LDPC), polar, and turbo codes. There are simple shift register-based n-bit counters with a few XOR gates that behave pseudo-randomly. The LFSR is used in chip hardware for high-speed operations, error control, and the generation of pseudo-random numbers. The hardware chip design and performance estimation of the LFSR is the problem for specific communication system. The motivation of the work is to generate the Gold code sequence by the integration of two LFSR. The article proposes the hardware chip design and simulation of two 5-bit LFSR modules used for the gold sequence generator applicable for the communication systems. The novelty of the work is that the design is scalable and can be extended based on the requirements of the systems which is synthesized and experimentally verified on the Zynq-7000 field programmable gate array (FPGA) board. The concept of this design is programmable and can be extended to n-bit based on the applications. The work is supported, and formulated using very high speed integrated circuit hardware description language (VHDL) programming in Xilinx ISE 14.7 software.

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Lurina, Manda, Sugondo Hadiyoso, and Rina Pudji Astuti. "Scrambling and De-Scrambling Implementation Using Linear Feedback Shift Register Method on FPGA." IJAIT (International Journal of Applied Information Technology) 1, no. 02 (2017): 59–67. http://dx.doi.org/10.25124/ijait.v1i02.876.

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communication system, a long sequence of bits ‘0’ or ‘1’ will inherits the loss of bit synchronization, and hence it can cause the false detection on the receiver. To avoid this, long sequence of bits will be randomized first so that long sequence of bits ‘0’ or ‘1’ can be removed. This randomization process is called scrambling and the circuit that works for the process is a scrambler. In the receiver there is a descrambler that serves to return the bits to their original information. This paper presents a design of scrambler and descrambler using a combination of Linear Feedback Shift Register (LFSR) with 15 registers, XOR logic gates, and Pseudo Random Binary Sequence (PRBS) generator structure with polynomial 1 + x14 + x15. One of the two main parts of LFSR is the shift register while the other is the feedback. In LFSR, the bits contained within the selected position in the shift register will be combined in a function and the result will be put back into this register's input bit. Feedback also makes the system more stable and no error occurrence. Then special tap is taken from a certain point in XOR and returned as a feedback register. The system is implemented on FPGA board Altera De0-Nano EP4CE22F17C6 Cyclone IV E. Resource memory required <1% of available memory. Bit rate that can be achieved with clock speed 50MHz is 335570.47 bps.

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Falih, Saad. "A Pseudorandom Binary Generator Based on Chaotic Linear Feedback Shift Register." Iraqi Journal for Electrical and Electronic Engineering 12, no. 2 (2016): 155–60. http://dx.doi.org/10.37917/ijeee.12.2.5.

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This paper presents a simple method for the design of Chaotic Linear Feedback Shift Register (CLFSR) system. The proposed method is based on a combination of two known systems. The first is called Linear Feedback Shift Register (LFSR) system, and the other is called Chaotic Map system. The main principle of the proposed system is that, the output of the LFSR is modified by exclusive-or (XOR) it with the stream bit that is generated by using the chaotic map system to eliminate the linearity and the repeating in the output of the LFSR system. The proposed system is built under Matlab environment and the quality of sequence generation tested by using standard tests which shows that the proposed system is a good random number generator that overcome the linearity and repeating disadvantages.

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Garbolino, Tomasz. "A New, Fast Pseudo-Random Pattern Generator for Advanced Logic Built-In Self-Test Structures." Applied Sciences 11, no. 20 (2021): 9476. http://dx.doi.org/10.3390/app11209476.

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Digital cores that are currently incorporated into advanced Systems on Chip (SoC) frequently include Logic Built-In Self-Test (LBIST) modules with the Self-Test Using MISR/Parallel Shift Register Sequence Generator (STUMPS) architecture. Such a solution always comprises a Pseudo-Random Pattern Generator (PRPG), usually designed as a Linear Feedback Shift Register (LFSR) with a phase shifter attached to the register and arranged as a network of XOR gates. This study discloses an original and innovative structure of such a PRPG unit referred to as the DT-LFSR-TPG module that needs no phase shifter. The module is designed as a set of identical linear registers of the DT-LFSR type with the same primitive polynomial. Each register has a form of a ring made up exclusively of D and T flip-flops. This study is focused on the investigation of those parameters of DT-LFSR registers that are essential to use these registers as components of PRPG modules. The investigated parameters include phase shifts and the correlation between sequences of bits appearing at outputs of T flip-flops, implementation cost, and the maximum frequency of the register operation. It is demonstrated that PRPG modules of the DT-LFSR-TPG type enable much higher phase shifts and substantially higher operation frequencies as compared to competitive solutions. Such modules can also drive significantly more scan paths than other PRPGs described in reference studies and based on phase shifters. However, the cost of the foregoing advantages of DT-LFSR-TPG modules is the larger hardware overhead associated with the implementation of the solution proposed.

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Pramod, Chouhan, and Priyanshu Pandey Prof. "Design and Implementation of Multiple Input Multiple Output Reversible Sequential Circuit." Journal of Advances in Electrical Devices 3, no. 3 (2018): 14–18. https://doi.org/10.5281/zenodo.1564930.

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The repetition of arbitrary production relies upon the quantity of stages in the LFSR. In this way, it is an imperative part in correspondence framework where it play important role in various application such as cryptography application, CRC generator and regulator circuit, gold code generator, for generation of pseudorandom sequence, for designing encoder and decoder in different communication channels to ensure network security. We employ of various inputs and various output shift registers for LFSR on FPGA by using VHDL and analysis the behavior of randomness.

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Caballero-Gil, Pino, Amparo Fúster-Sabater, and Candelaria Hernández-Goya. "Graph-Based Approach to the Edit Distance Cryptanalysis of Irregularly Clocked Linear Feedback Shift Registers." JUCS - Journal of Universal Computer Science 15, no. (15) (2009): 2981–98. https://doi.org/10.3217/jucs-015-15-2981.

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This paper proposes a speed-up of a known-plaintext attack on some stream ciphersbased on Linear Feedback Shift Registers (LFSRs). The algorithm consists of two basic steps: first, to guess the initial seed value of one of the LFSRs, and then to use the resulting binarysequence in order to deduce useful information about the cipher parameters. In particular, the proposed divide-and-conquer attack is based on a combination of graph-based techniques withedit distance concepts. While the original edit distance attack requires the exhaustive search over the set of all possible initial states of the involved LFSR, this work presents a new heuristic op-timization that avoids the evaluation of an important number of initial states through the identification of the most promising branches of the search graph. The strongest aspects of the proposalare the facts that the obtained results from the attack are absolutely deterministic, and that many inconsistent initial states of the target LFSRs are recognized and avoided during search.

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Bhargavi, K. Manju. "Design of Linear Feedback Shift Register for Low Power Applications." International Journal for Research in Applied Science and Engineering Technology 9, no. VII (2021): 3912–18. http://dx.doi.org/10.22214/ijraset.2021.37251.

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This paper presents the design & implementation of the Linear Feedback Shift Register (LFSR) using the Mentor Graphics tool in 90nm technology. LFSR’s have a wide variety of applications. They are used in pseudo-random variety generation, whitening sequences and pseudo-noise sequences. MOS current-mode logic (MCML) and Dynamic current-mode logic (DYCML) are employed to design an LFSR. MCML is widely used in high-speed applications and these MCML circuits are based on current steering logic. The advantages of the MCML method are that they have high noise immunity due to their differential nature of inputs. The disadvantage of MCML approach is static power dissipation. To overcome these issues of MCML logic, Dynamic CML logic is used. Its advantages include low static power dissipation and high performance. This paper shows the comparison results of CMOS, Dynamic CML and MCML designs in terms of delay, power and transistor count.

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Hameed, Isam Salah, Salah Alkurwy, and Heba Hadi Ali. "Implementation of Pass Transistor Logic and C2MOS Linear Feedback Shift Register (LFSR) Circuit using FPGA and PSpice." International Journal of Electrical and Electronics Research 13, no. 1 (2025): 164–70. https://doi.org/10.37391/ijeer.130121.

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In this paper, a 4-bit Linear Feedback Shift Register (LFSR) is implemented based on a well-designed architecture combining using Pass-Transistor (PT) and Clock Complementary Metal Oxide Semiconductor (C2MOS) logic techniques. The D-flip flop registers and the XOR gates are the main parts of the propose LFSR. Number of transistors along with the speed of LFSR were positively enhanced since the exploited logic design techniques tends to blend the flavor of NMOS and PMOS devices. The PSpice and Field Programmable Gate Array (FPGA) based on Hardware Description Language (HDL) are the two different LFSR implementation environments. It has been observed that LFSR performance was effectively improved in terms of size and speed. Therefore, paper’s main aim refers to decreasing in number of transistors as well as speeding up LFSR circuit. A minimum clock time of 5ns was recorded under clearly correct LFSR output patterns. The LFSR circuit Based CMOS techniques can reduce the exploited transistors up to 43% of the conventional C2MOS logic. Besides, the number of transistors being reduced reflects the achieved circuit’s size reduction. It was concluded that paying attention to the design of the main LFSR circuit parts contributes mainly in the enhancement of the whole circuit performance.

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Laung-Terng Wang and McCluskey. "Condensed Linear Feedback Shift Register (LFSR) Testing—A Pseudoexhaustive Test Technique." IEEE Transactions on Computers C-35, no. 4 (1986): 367–70. http://dx.doi.org/10.1109/tc.1986.1676772.

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Rahayu, Rivi Tri, Abduh Riski, and Ahmad Kamsyakawuni. "PENYANDIAN CITRA MENGGUNAKAN ALGORITMA 4D PLAYFAIR CIPHER DENGAN PEMBANGKITAN KUNCI MODIFIKASI LINEAR FEEDBACK SHIFT REGISTER." Majalah Ilmiah Matematika dan Statistika 19, no. 1 (2019): 17. http://dx.doi.org/10.19184/mims.v19i1.17261.

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The fast development of sophisticated technology make it easier for someone to send a message to other but can also make it easier for third parties to sabotage the content of the message, so a technique called cryptography is needed to secure the message. Image encoding is one of the techniques for securing messages in cryptography. In enhancing security in image encoding, this study discusses about Playfair Cipher, 3D Playfair Cipher and 4D Playfair Cipher with key generation using LFSR Modification. The encryption process using 4D Playfair Cipher with key generation using LFSR Modification visually produces cipher image that is different from the original image compared to using Playfair Cipher and 3D Playfair Cipher. In the decryption process using Playfair Cipher, 3D Playfair Cipher and 4D Playfair Cipher-Modification LFSR can return cipher image to its original image. The result of the study shows that the proposed method can be used to secure the message. Keywords: Playfair Cipher, 3D Playfair Cipher, 4D Playfair Cipher, LFSR

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Mittal, Parangat, and Daksh Shah. "Linear Feedback Shift Register-Based Test Pattern Generators: A Comparative Study." International Journal of Advanced Research in Electronics and Communication Engineering (IJARECE) 9, no. 8 (2020): 60–62. https://doi.org/10.5281/zenodo.5039922.

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Pseudo Random Number Generators are widely used in VLSI Design as Test Pattern Generators for testing of digital circuits in a BIST system. The test pattern sequence generated also finds applications in cryptography. It is thus essential to design an efficient test pattern generator which utilizes least hardware, dissipates lowest power and generates most random sequence. This paper attempts to compare a few recent proposals where Linear Feedback Shift Register (LFSR) has been suitably modified to obtain an efficient architecture of a test pattern generator.

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bin Rosly, Hasrul Nisham, Mamun bin Ibne Reaz, Noorfazila Kamal, and Fazida Hanim Hashim. "Design and Analysis of CMOS Linear Feedback Shift Registers for Low Power Application." Applied Mechanics and Materials 833 (April 2016): 111–18. http://dx.doi.org/10.4028/www.scientific.net/amm.833.111.

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Chip manufacturing technologies have been a key to the growth in all electronics devices over the past decade, bringing added convenience and accessibility through advantages in cost, size, and power consumption. Using recent CMOS technology, LFSR is implemented until layout level which develops low power application. One of the most frequent uses of a LFSR inside a FPGA is as a counter. Using a LFSR instead of a binary counter can increase the clock rate considerably due to the low routing resource required to produce the next state logic. This paper explores the LFSR using different architecture in a 0.18μm CMOS technology. There are 3 type architecture implemented into LFSR which is NAND gates, pass transistor and transmission gates. Those LFSR are compare in term of CMOS layout, hardware implementation and power consumption using Mentor Graphics tools. Thus, it provides analysis of LFSR for low power application in CMOS VLSI.

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Journal, Baghdad Science. "Stochastic Non-Linear Pseudo-Random Sequence Generator." Baghdad Science Journal 7, no. 2 (2010): 1042–46. http://dx.doi.org/10.21123/bsj.7.2.1042-1046.

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Many of the key stream generators which are used in practice are LFSR-based in the sense that they produce the key stream according to a rule y = C(L(x)), where L(x) denotes an internal linear bit stream, produced by small number of parallel linear feedback shift registers (LFSRs), and C denotes some nonlinear compression function. In this paper we combine between the output sequences from the linear feedback shift registers with the sequences out from non linear key generator to get the final very strong key sequence

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Shamran, Mahmood A. "Stochastic Non-Linear Pseudo-Random Sequence Generator." Baghdad Science Journal 7, no. 2 (2010): 1042–46. http://dx.doi.org/10.21123/bsj.2010.7.2.1042-1046.

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MPR Murthy. "Double Encrypted Symmetric Cryptosystem Using adjacency matrix and Linear Feedback Shift Register (LFSR)." Communications on Applied Nonlinear Analysis 31, no. 6s (2024): 269–78. http://dx.doi.org/10.52783/cana.v31.1262.

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Owing to an extensive and indiscriminate usage of social communicating networks nowadays, transfer of sensitive data genuine people has become hardship and Herculean task. Message encryption is the only tool to safeguard the original information that helps to protect the data from cyber-attacks in its journey via public channel. Graph theory is one of the important techniques used in the encryption process especially in block ciphers. Abundant research has been done in the field of cryptography using several graph theory concepts. This article explains a symmetric block cipher employing the concept of an adjacency matrix in an undirected graph. Here each block is encrypted at two different stages and three rounds at each stage. The first stage of encryption is done with an adjacency matrix and second stage using simple logical XOR operation in a special pattern. In this technique the adjacency matrix is public, the sender and receiver derive new matrices for encryption/decryption from the adjacency matrix using Linear Feedback Shift Register LFSR. LFSR polynomial acts as a secret key which is the agreement between the communicating parties.

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Shyi-Tsong Wu, Shyi-Tsong Wu. "Hybrid FCSR Based Stream Cipher for Secure Communications in IoT." 網際網路技術學刊 24, no. 6 (2023): 1273–86. http://dx.doi.org/10.53106/160792642023112406010.

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Linear Feedback Shift Register (LFSR) is the basic hardware of stream cipher, and Feedback with Carry Shift Register (FCSR) is the nonlinear analogues of LFSR. FCSR is a feedback architecture to generate long pseudorandom sequence. In this paper, we study the characteristics of FCSRs combined with nonlinear circuits such as Dawson&rsquo;s Summation Generator (DSG), lp-Geffe generator and etc. Then we proposed a hybrid FCSR applying DSG and lp-Geffe generator as nonlinear combining elements to increase the period and the linear complexity of the output sequence. In addition, we further investigate the period, linear complexity, randomness, and use known attacks to verify the security strength of the proposed keystream generator. The pass rates of the proposed scheme are 100% for FIPS PUB 140-1 random tests, and at least 98% for SP800-22 random test, respectively. &nbsp;

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Kannadhasan, Suriyan, Ramalingam Nagarajan, Venusamy Kanagaraj, Sivaraman Sathish, Balasubramaniyan Kiruthiga, and Alagarsamy Manjunathan. "Power analyzer of linear feedback shift register techniques using built in self test." Bulletin of Electrical Engineering and Informatics 11, no. 2 (2022): 713–21. https://doi.org/10.11591/eei.v11i2.3331.

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Wasteful patterns that don't lead to fault dropping squander a tone of energy in the linear-feedback shift register and circuit under examination in a random research region. Random switching actions in the CUT and scan pathways between applications with two consecutive vectors are another significant cause of energy loss. This study proposes a unique built-in selftest (BIST) technique for scan-based circuits that might help save energy. Only the available vectors are produced in a fixed series thanks to a mapping logic that alters the LFSR's state transitions. As a consequence, and without reducing fault coverage, the time it takes to execute trials has decreased. Experiments on circuits demonstrated that during random testing, the linear feedback shift register saves a significant amount of power.

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Awaid, Falih. "Breaking Modified Bruer Generator by Solving the System of Linear Equations of the Generated Sequence." Journal of Al-Rafidain University College For Sciences ( Print ISSN: 1681-6870 ,Online ISSN: 2790-2293 ), no. 2 (October 19, 2021): 48–67. http://dx.doi.org/10.55562/jrucs.v30i2.365.

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Linear Feedback Shift Register (LFSR) systems are used widely in stream cipher systems field. Golomb used the recurrence relation to find the next state values of single LFSR depending on initial values, s.t. he can be considered the first who can construct a linear equations system of a single LFSR. Attacking of key generator means attempt to find the initial values of the combined LFSR's.In this paper, a Golomb's method introduced to construct a linear equations system of a single LFSR. This method developed to construct a linear equations system of key generator (a LFSR system) where the effect of combining function of LFSR is obvious. Finally, before solving the linear equations system, the uniqueness of the solution must be tested, then solving the linear equations system using one of the classical methods like Gauss Elimination. Find the solution of linear equations system means find the initial values of the generator. One of the known generators; Modified Bruer generator, treated as a practical example of this work.

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Chen, Chien-In Henry, and Yingjie Zhou. "Configurable 2-D Linear Feedback Shift Registers for VLSI Built-in Self-test Designs." VLSI Design 11, no. 2 (2000): 149–59. http://dx.doi.org/10.1155/2000/60904.

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Recently a multiple-sequence test generator was presented based on two-dimensional linear feedback shift registers (2-D LFSR). This generator can generate a set of precomputed test vectors obtained by an ATPG tool for detecting random-pattern-resistant faults and particular hard-to-detect faults. In addition, it can generate better random patterns than a conventional LFSR. In this paper we describe an optimized BIST scheme which has a configurable 2-D LFSR structure. Starting from a set of stuck-at faults and a corresponding set of test vectors detecting these faults, the corresponding test pattern generator is determined automatically. A synthesis procedure of designing this test generator is presented. Experimental results show that the hardware overhead is considerably reduced compared with 2-D LFSR generators.

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Gandhi, Srushti, and Ravi Gor. "DIGITAL IMAGE ENCRYPTION USING RSA AND LFSR." International Journal of Engineering Science Technologies 6, no. 4 (2022): 36–52. http://dx.doi.org/10.29121/ijoest.v6.i4.2022.351.

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In this world of hasty evolution of exchanging digital data, data protection is essential to keep the data safe from the unauthorized parities. With the broad use of digital images of various fields, it is important to preserve the confidentiality for the data of an image from any unauthorized access. In this paper, the keys are generated using a random number generator which is based on Linear Feedback Shift Register (LFSR). The encryption/decryption is based on Rivest–Shamir–Adleman (RSA) with the random key generator.

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Singh, Balwinder, and Birinderjit Singh Kalyan. "Performance Analysis of Quantum Dot Cellular Automata (QCA) based Linear Feedback Shift Register (LFSR)." International Journal of Computing and Digital Systems 9, no. 3 (2020): 545–51. http://dx.doi.org/10.12785/ijcds/090318.

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Gandhi, Srushti, and Ravi Gor. "DIGITAL IMAGE ENCRYPTION USING LAPLACE TRANSFORM AND LFSR." International Journal of Engineering Science Technologies 6, no. 5 (2022): 1–22. http://dx.doi.org/10.29121/ijoest.v6.i5.2022.390.

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In the world of rapid evolution of exchanging digital data, data security is essential to protect data from the unauthorized parities. With the broad use of digital images of various fields, it is important to preserve the confidentiality of image’s data from any unauthorized access. Cryptography is a technique that assists in the development of such algorithms for security purpose. In this paper, key is generated using a random number generator based on Linear Feedback Shift Register (LFSR) and Laplace Transformation.

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Pallangan, Jorghie Theodore Kenzo, and Alz Danny Wowor. "Identifikasi Nilai Keacakan Berdasarkan Reposisi Fungsi XOR Pada Blok Kedua LFSR A5/1." Journal of Information System Research (JOSH) 6, no. 1 (2024): 679–87. https://doi.org/10.47065/josh.v6i1.6112.

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This research plans a random number generation method using the Linear Feedback Shift Register (LFSR) method with the A5/1 scheme which involves three feedback functions. XOR is used to determine the new output bit value in the next iteration in the feedback mechanism. The test material produces random output for an input using Run Test, Mono Bit, and Block bit. Tests using three feedback functions were carried out to compare with previous research which generated random numbers. Testing of plaintext and ciphertext encryption shows a very small level of correlation with an average value close to 0. The use of LFSR with the A5/1 scheme which involves three XOR functions, creates random output and can be used against Stream Chipers.

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Ali Khalil Salih. "Using permutation function and the Bank of LFSR's in pseudo random generator keys." Tikrit Journal of Pure Science 22, no. 11 (2023): 102–5. http://dx.doi.org/10.25130/tjps.v22i11.923.

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In this paper a Bank of Linear Feedback Shift Registers (LFSR) is used to design and build a system for cryptography. This algorithm consists of 16 Linear Feedback Shift Registers. When we choose eight Shift Registers for each operation of this system, we get one byte constantly this operation. The external unit consists of three Linear Feedback Shift Registers use for filling the main system to generate the stream cipher of bits (0&1) as a Pseudo Random generator, in which we use the permutation system and this sequence of bits passed the statistical tests.

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Kim, Hyun-Il, and Jun-Cheol Jeon. "Quantum LFSR Structure for Random Number Generation Using QCA Multilayered Shift Register for Cryptographic Purposes." Sensors 22, no. 9 (2022): 3541. http://dx.doi.org/10.3390/s22093541.

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A random number generator (RNG), a cryptographic technology that plays an important role in security and sensor networks, can be designed using a linear feedback shift register (LFSR). This cryptographic transformation is currently done through CMOS. It has been developed by reducing the size of the gate and increasing the degree of integration, but it has reached the limit of integration due to the quantum tunneling phenomenon. Quantum-dot cellular automata (QCA), one of the quantum circuit design technologies to replace this, has superior performance compared to CMOS in most performance areas, such as space, speed, and power. Most of the LFSRs in QCA are designed as shift registers (SR), and most of the SR circuits proposed based on the existing QCA have a planar structure, so the cell area is large and the signal is unstable when a plane intersection is implemented. Therefore, in this paper, we propose a multilayered 2-to-1 QCA multiplexer and a D-latch, and we make blocks based on D-latch and connect these blocks to make SR. In addition, the LFSR structure is designed by adding an XOR operation to it, and we additionally propose an LFSR capable of dual-edge triggering. The proposed structures were completed with a very meticulous design technique to minimize area and latency using cell interaction, and they achieve high performance compared to many existing circuits. For the proposed structures, the cost and energy dissipation are calculated through simulation using QCADesigner and QCADesigner-E, and their efficiency is verified.

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Espinosa García, Javier, Guillermo Cotrina, Alberto Peinado, and Andrés Ortiz. "Security and Efficiency of Linear Feedback Shift Registers in GF(2n) Using n-Bit Grouped Operations." Mathematics 10, no. 6 (2022): 996. http://dx.doi.org/10.3390/math10060996.

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Many stream ciphers employ linear feedback shift registers (LFSRs) to generate pseudorandom sequences. Many recent LFSRs are defined in GF(2n) to take advantage of the n-bit processors, instead of using the classic binary field. In this way, the bit generation rate increases at the expense of a higher complexity in computations. For this reason, only certain primitive polynomials in GF(2n) are used as feedback polynomials in real ciphers. In this article, we present an efficient implementation of the LFSRs defined in GF(2n). The efficiency is achieved by using equivalent binary LFSRs in combination with binary n-bit grouped operations, n being the processor word’s length. This improvement affects the general considerations about the security of cryptographic systems that uses LFSR. The model also allows the development of a faster method to test the primitiveness of polynomials in GF(2n).

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Sabbaghi-Nadooshan, Reza, Zahra Shahosseini, and Davood Rezaeipour. "Design of New QCA LFSR and NLFSR for Grain-128 Stream Cipher." Journal of Circuits, Systems and Computers 25, no. 02 (2015): 1650005. http://dx.doi.org/10.1142/s0218126616500055.

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The use of quantum-dot cellular automata (QCA) technology for the design of logic circuits has shown to increase data transfer rates up to 2 THz. In QCA technology, circuits are designed to have an ultra-small feature size as well as ultra-low power consumption. Grain-128 is one of the best stream ciphers in the final list of the eSTREAM project. In this paper, we have designed and simulated the main blocks of this algorithm including XOR gate, linear-feedback shift register (LFSR) and nonlinear-feedback shift register (NLFSR) using QCA technology. The designs of these blocks using the QCA Designer simulator are given and the main factors such as area, complexity and delay are estimated. Furthermore, ModelSim software is used to simulate HDLQ model of the QCA Grain-128 stream cipher algorithm. The results indicate that the main parameters of the proposed Grain-128, such as area and throughput, are improved as well.

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Yan, Shaohui, Jianjian Wang, and Lin Li. "A color image encryption scheme based on cellular neural networks and linear feedback shift registers." Physica Scripta 99, no. 3 (2024): 035212. http://dx.doi.org/10.1088/1402-4896/ad224b.

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Abstract In this paper, a cellular neural network (CNN) chaotic system is constructed and the multiple stability of the system and its rich chaotic properties are confirmed by studying the effect of parameters on the system, coexisting attractors, and offset boosting behavior. As linear feedback shift registers (LFSR) can be applied to cryptography, this paper applies LFSR to generate encrypted key matrices to enhance the randomness of encryption algorithms. Based on CNN and LFSR, a new color image encryption algorithm is designed by combining DNA coding and bit-plane decomposition with high bit-plane Zigzag dislocation changes. Experimental results and security tests show that the algorithm is highly secure and resistant to a variety of common attacks, such as differential attacks, cropping attacks, and noise attacks.

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Gupta, Sanchit. "LFSR Next Bit Prediction through Deep Learning." Journal of Informatics Electrical and Electronics Engineering (JIEEE) 2, no. 2 (2021): 1–9. http://dx.doi.org/10.54060/jieee/002.02.022.

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Pseudorandom bit sequences are generated using deterministic algorithms to simulate truly random sequences. Many cryptographic algorithms use pseudorandom sequences, and the randomness of these sequences greatly impacts the robustness of these algorithms. Important crypto primitive Linear Feedback Shift Register (LFSR) and its combinations have long been used in stream ciphers for the generation of pseudorandom bit sequences. The sequences generated by LFSR can be predicted using the traditional Berlekamp Massey Algorithm, which solves LFSR in 2×n number of bits, where n is the degree of LFSR. Many different techniques based on ML classifiers have been successful at predicting the next bit of the sequences generated by LFSR. However, the main limitation in the existing approaches is that they require a large number (as compared to the degree of LFSR) of bits to solve the LFSR. In this paper, we have proposed a novel Pattern Duplication technique that exponentially reduces the input bits requirement for training the ML Model. This Pattern Duplication technique generates new samples from the available data using two properties of the XOR function used in LFSRs. We have used the Deep Neural Networks (DNN) as the next bit predictor of the sequences generated by LFSR along with the Pattern Duplication technique. Due to the Pattern Duplication technique, we need a very small number of input patterns for DNN. Moreover, in some cases, the DNN model managed to predict LFSRs in less than 2n bits as compared to the Berlekamp Massey Algorithm. However, this technique was not successful in cases where LFSRs have primitive polynomials with a higher number of tap points.

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Feng, Yelai, Huaixi Wang, Chao Chang, Hongyi Lu, Fang Yang, and Chenyang Wang. "A Novel Nonlinear Pseudorandom Sequence Generator for the Fractal Function." Fractal and Fractional 6, no. 10 (2022): 589. http://dx.doi.org/10.3390/fractalfract6100589.

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A pseudorandom sequence is a repeatable sequence with random statistical properties that is widely used in communication encryption, authentication and channel coding. The pseudorandom sequence generator based on the linear feedback shift register has the problem of a fixed sequence, which is easily tracked. Existing methods use the secret linear feedback shift register (LFSR) and built-in multiple LFSRs and is difficult to prevent cracking based on the hardware analysis. Since the plaintext depends on a specific language to be generated, using pseudo-random sequence encryption, it faces the problem that the encryptor cannot hide the characteristics of the plaintext data. Fractal functions have the following properties: chaotic, unpredictable and random. We propose a novel pseudorandom sequence generator based on the nonlinear chaotic systems, which is constructed by the fractal function. Furthermore, we design a data processing matrix to hide the data characteristics of the sequence and enhance the randomness. In the experiment, the pseudo-random sequences generator passed 16 rigorous test items from the National Institute of Standards and Technology (NIST), which means that the nonlinear pseudorandom sequence generator for the fractal function is effective and efficient.

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Hong, Zhou, and Ling Xieting. "Generating Chaotic Secure Sequences with Desired Statistical Properties and High Security." International Journal of Bifurcation and Chaos 07, no. 01 (1997): 205–13. http://dx.doi.org/10.1142/s0218127497000145.

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This work proposes a class of one-dimensional analogue chaotic signals which have perfect statistical properties. A non-invertible transformation is introduced to generate a class of binary (symbolic) chaotic sequences with desired distribution function and correlation function. These binary chaotic secure sequences are proven to have near-ideal linear complexity and infinite large discrete correlation dimension, thus they cannot be reconstructed by linear-feedback shift-register (LFSR) techniques or nonlinear dynamics (NLD) forecasting in finite order.

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Kim, Minsu, Jiwoon Park, Gwanghee Jo, and Hoyoung Yoo. "Area-Efficient Universal Code Generator for Multi-GNSS Receivers." Electronics 10, no. 20 (2021): 2485. http://dx.doi.org/10.3390/electronics10202485.

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Although conventional global navigation satellite systems (GNSS) receivers were originally designed for single signals, studies on multi-signal receiver design have recently been actively conducted to achieve high accuracy, precision, and reliability. However, in order for a multi-signal receiver to support various codes, the receiver should support the generation of individual codes. Therefore, the resulting problem of increased complexity must be solved. This paper proposes a hardware structure for an area-efficient linear feedback shift register (LFSR)-based multi-frequency universal code generator. Whereas the existing universal code generators were configured so that feedback polynomials, output registers, and initial values can be selected by placing read-only memories (ROMs), multiplexers (MUXs), and exclusive ORs (XORs) by register bit, in the case of the proposed universal code generator; the circuit was implemented by applying the hardwiring technique to those register bits that have fixed values. According to the results of field programmable gate array (FPGA) implementation, the proposed LFSR-based universal code generator can improve look up table (LUT) by up to 37% and register by up to 78% when compared to conventional code generators, and LUT by up to 36% when compared to the previous universal code generator. Therefore, the proposed universal code generator is a good candidate for implementing multi-frequency receivers to achieve high precision and high reliability.

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Mirella, Amelia Mioc. "BRAIN Journal - A Synoptic of Software Implementation for Shift Registers Based on 16th Degree Primitive Polynomials." BRAIN - Broad Research in Artificial Intelligence and Neuroscience 7, no. 3 (2016): 31–42. https://doi.org/10.5281/zenodo.1044978.

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ABSTRACT Almost all of the major applications in the specific Fields of Communication used a wellknown device called Linear Feedback Shift Register. Usually LFSR functions in a Galois Field GF(2n ), meaning that all the operations are done with arithmetic modulo n degree Irreducible and especially Primitive Polynomials. Storing data in Galois Fields allows effective and manageable manipulation, mainly in computer cryptographic applications. The analysis of functioning for Primitive Polynomials of 16th degree shows that almost all the obtained results are in the same time distribution.

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K, Sivakami, Vijayalakshmi P, and Jaya J. "VLSI USAGE OF A PRODUCTIVE MBIST ARCHITECTURE UTILIZING RLFSR." ICTACT Journal on Microelectronics 7, no. 2 (2021): 1134–40. https://doi.org/10.21917/ijme.2021.0197.

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This article introduces a power efficient application of FPGA created through a Memory Built in Self Test (MBIST). It has 2-bit Linear Feedback Shift Register (LFSR) array, which changes the direction of the previous process and creates high MBIST structures. This unwanted change affects all MBIST’s power consumption. The proposed MBIST with LFSR ring reduces the power consumption problem. The 2-bit 2N bit model generator is connected to the 2-bit (N-2) and 2-bit 4-bit (N-2) LFSR model generator, which are separately controlled using two separate clocks with two different frequencies, creating each location address high memory test. The proposed architecture has been implemented on Vertex4 FPGA technology in Xilinx software. The results enhance proposed design’s performance when compared it with the existing design.

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Xiao, Haoyuan. "High-performance LFSR circuit design based on XOR gates." Journal of Physics: Conference Series 2649, no. 1 (2023): 012042. http://dx.doi.org/10.1088/1742-6596/2649/1/012042.

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Abstract The research discussed in this article is focused on analysing the effects of XOR gates based on different logic families, namely MOS Current Mode Logic (MCML), dynamic current logic, and PTL, on the performance of linear feedback shift register (LFSR) circuits. The aim of the study is to evaluate the power dissipation and critical path latency of the circuits while comparing the results with earlier works in the field. To achieve this, the researchers implemented the 3, 4, and 5-bit LFSR circuits using Verilog HDL code and synthesized them on the Cadence tool using 90nm CMOS technology. The study concludes that LFSR circuits based on XOR gates outperform previous LFSR circuits in terms of power dissipation. The research also offers a comparative analysis of the different types of XOR gates used in the LFSR circuits, highlighting the advantages and disadvantages of each type. The results of the study can be useful for researchers working in the field of circuit design, as well as for practitioners who are interested in developing low-power and efficient LFSR circuits.

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Ndaw, Babacar, Djiby Sow, and Mamadou Sanghare. "Construction of Maximum Period Linear Feedback Shift Registers (LFSR) (Primitive Polynomials and Linear Recurring Relations)." British Journal of Mathematics & Computer Science 11, no. 4 (2015): 1–24. http://dx.doi.org/10.9734/bjmcs/2015/19442.

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Nishitani, Yoshi, Chie Hosokawa, Yuko Mizuno-Matsumoto, Tomomitsu Miyoshi, Hajime Sawai, and Shinichi Tamura. "Detection of M-Sequences from Spike Sequence in Neuronal Networks." Computational Intelligence and Neuroscience 2012 (2012): 1–9. http://dx.doi.org/10.1155/2012/862579.

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In circuit theory, it is well known that a linear feedback shift register (LFSR) circuit generates pseudorandom bit sequences (PRBS), including an M-sequence with the maximum period of length. In this study, we tried to detect M-sequences known as a pseudorandom sequence generated by the LFSR circuit from time series patterns of stimulated action potentials. Stimulated action potentials were recorded from dissociated cultures of hippocampal neurons grown on a multielectrode array. We could find several M-sequences from a 3-stage LFSR circuit (M3). These results show the possibility of assembling LFSR circuits or its equivalent ones in a neuronal network. However, since the M3 pattern was composed of only four spike intervals, the possibility of an accidental detection was not zero. Then, we detected M-sequences from random spike sequences which were not generated from an LFSR circuit and compare the result with the number of M-sequences from the originally observed raster data. As a result, a significant difference was confirmed: a greater number of “0–1” reversed the 3-stage M-sequences occurred than would have accidentally be detected. This result suggests that some LFSR equivalent circuits are assembled in neuronal networks.

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Y, G. Praveen Kumar, S. Kariyappa B, and Z. Kurian M. "Design, Implementation and Performance Analysis of Test Pattern Generator for Built-In Self-Test using m-GDI Technology." Indian Journal of Science and Technology 15, no. 5 (2022): 221–26. https://doi.org/10.17485/IJST/v15i5.1846.

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ABSTRACT Background: A Linear Feedback Shift Register (LFSR) is typically used for generating the test patterns in built-in self-test (BIST) as it produces pseudorandom patterns at every clock cycle. These pseudo-random patterns are used as test vectors for testing the VLSI circuits. Objective: The pseudorandom patterns generated by the LFSR exhibit low-correlation among the patterns, this increases the switching activity and power dissipation while testing the VLSI circuit. Thus, to reduce the testing power, modified gate diffusion input (m-GDI) logic based LFSR in 45nm technology is proposed in this paper. Methods: The circuits are developed on m-GDI technology using the Cadence virtuoso tool and a spectre simulator is used to carry out the simulation. Findings: Comparative analysis revealed that the delay and power are reduced significantly, for the proposed design when compared to the existing LFSRs in conventional CMOS, GDI and reversible logic. Novelty and applications: In conventional LFSR, an external source is necessary to load the seed value and it dissipates more power. But in the proposed design, the seed value is generated by the circuit itself. This reduces the power and critical path delay. Further a complete zero patterns is not possible in conventional LFSR design. But in proposed design, all zero pattern is plausible. The design obtained from this study can be applied in low-power, high-speed BIST circuits. Keywords: LFSR; Seed Value; Test Patterns; Built-In-Self-Test; m-GDI

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Varaprasad, B. K. S. V. L., L. M. Patnaik, H. S. Jamadagni, and V. K. Agrawal. "An Efficient Test Pattern Generation Scheme for an On Chip BIST." VLSI Design 12, no. 4 (2001): 551–62. http://dx.doi.org/10.1155/2001/45324.

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Testing and power consumption are becoming two critical issues in VLSI design due to the growing complexity of VLSI circuits and remarkable success and growth of low power applications (viz. portable consumer electronics and space applications). On chip Built In Self Test (BIST) is a cost-effective test methodology for highly complex VLSI devices like Systems On Chip. This paper deals with cost-effective Test Pattern Generation (TPG) schemes in BIST. We present a novel methodology based on the use of a suitable Linear Feedback Shift Register (LFSR) which cycles through the required sequences (test vectors) aiming at a desired fault coverage causing minimum circuit toggling and hence low power consumption while testing. The proposed technique uses circuit simulation data for modeling. We show how to identify the LFSR using graph theory techniques and compute its feedback coefficients (i.e., its characteristic polynomial) for realization of a Test Pattern Generator.

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Babu T, Narendra, Fazal Noorbasha, and Leenendra Chowdary Gunnam. "Implementation of High Security Cryptographic System with Improved Error Correction and Detection Rate using FPGA." International Journal of Electrical and Computer Engineering (IJECE) 6, no. 2 (2016): 602. http://dx.doi.org/10.11591/ijece.v6i2.9267.

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In this article, an encryption algorithm with an error detection technique is presented for highly secured reliable data transmission over unreliable communication channels. In this algorithm, an input data is mapped into orthogonal code first. After that the code is encrypted with the help of Linear Feedback Shift Register (LFSR). The technique has been successfully verified and synthesized using Xilinx by Spartan-3E FPGA. The results show that the error detection rate has been increased to 100% by proposed encryption scheme is effective and improves bandwidth efficiency.

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Novak, Ondrej, Jiri Jenicek, and Martin Rozkovec. "Sequential Test Decompressors with Fast Tester Bits Wide-Spreading." Journal of Circuits, Systems and Computers 26, no. 08 (2017): 1740001. http://dx.doi.org/10.1142/s0218126617400011.

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Usually, test pattern decompressors with dynamic reseeding are reset before starting a new test pattern decoding. The first few scan chain slices are then filled with test vectors that have lower decoding ability as the number of free variables is limited by the test access mechanism bandwidth. We have found that even within this limitation, it is possible to improve the decodability by creating fast and wide-spreading as many as possible independent linear combinations of the tester bits and using them for the scan chain loading. We evaluated features influencing the decompression quality and the hardware overhead for different decompressor principles. According to the evaluation results, we proposed a decompressor combining a XOR network and a linear feedback shift register (LFSR)-like automaton; we place the XOR network on the LFSR inputs. We demonstrate that due to this arrangement, the combined decompressor can be used without any phase shifter or state skipping ability of the LFSR. We have experimentally verified that adopting the proposed decompressor structure improves test coverage, saves the hardware resources and shortens the test application time.

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Swaraja, K., K. Meenakshi, Padmavathi Kora, Mamatha Samson, G. Karuna, and A. Ushasree. "A Secure Architecture of Design for Testability Structures." International Journal of Recent Technology and Engineering (IJRTE) 8, no. 2 (2019): 2816–20. http://dx.doi.org/10.35940/ijrte.b18840.078219.

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The structures of Scan-based Design for Testability are extremely susceptible towards unapproved access of the signals present inside the chip. This paper suggests a protected output based plan which averts the unapproved access without any compromise in the testability. A unique key for each test vector is provided in the proposed secure architecture. These inimitable keys are produced by a multi-polynomial linear feedback shift register (LFSR) in addition they are utilized as test vectors. The dimensions of the multi polynomial LFSR bit is saved bigger than the dimension of key so as to augment the level of security to the key. As the keys are concealed within the test vectors, there is reduction in area overhead. The amount of security is improved predominantly by changing the key for all test vectors, along with the location of the bit in the test vector by choosing a valid combination out of available test vector generated by multi polynomial LFSR.

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