Relevant bibliographies by topics / Merged-PiN-Schottky (MPS) diode

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  1. Journal articles
  2. Dissertations / Theses

Academic literature on the topic 'Merged-PiN-Schottky (MPS) diode'

Author: Grafiati
Published: 4 June 2021
Last updated: 18 February 2022

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Journal articles on the topic "Merged-PiN-Schottky (MPS) diode"

1

TANTRAVIWAT, Doldet, Wittawat YAMWONG, Udom TECHAKIJKAJORN, Kazuo IMAI, and Burapat INCEESUNGVORN. "Schottky Barrier Height Engineering of Ti/n-Type Silicon Diode by Means of Ion Implantation." Walailak Journal of Science and Technology (WJST) 15, no. 11 (2018): 803–9. http://dx.doi.org/10.48048/wjst.2018.5968.

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Herein, boron implantation technique was employed to engineer the Schottky barrier height (SBH) of Ti/n-type silicon junction (Ti/n-Si). The Ti/n-Si Schottky diodes with boron doses of 4, 5.4 and 6.6´1012 cm-2 at the energy of 25 keV were fabricated with improved rectification and their effective SBHs increased from 0.49 to 0.95. The tuning of the effective SBH is mainly attributed to the presence of shallow p-layer, which modifies the energy band at Ti/n-Si interface. This work clearly shows that the ability to precisely control the SBH, regardless of the metal work function, would facilitate the implementation of Schottky diode into various semiconductor structures, such as MPS (Merged PiN Schottky) diode, in order to improve performance without major modification on the existing metal line process.
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Wu, Jiupeng, Na Ren, Qing Guo, and Kuang Sheng. "A Comparative Study of Silicon Carbide Merged PiN Schottky Diodes with Electrical-Thermal Coupled Considerations." Materials 13, no. 11 (2020): 2669. http://dx.doi.org/10.3390/ma13112669.

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A comparative study of surge current reliability of 1200 V/5 A 4H-SiC (silicon carbide) MPS (Merged PiN Schottky) diodes with different technologies is presented. The influences of device designs in terms of electrical and thermal aspects on the forward conduction performance and surge current capability were studied. Device forward characteristics were simulated and measured. Standard single-pulse surge current tests and thermal impedance measurements were carried to show their surge capability and thermal design differences. An advanced thermal RC (thermal resistance-capacitance) model, with the consideration of current distribution non-uniformity effects, is proposed to accurately calculate the device junction temperature during surge events. It was found that a thinner substrate and a hexagonal layout design are beneficial to the improvement of the bipolar conduction performance in high current mode, as well as the surge current capability. The thinner substrate design also has advantages on thermal aspects, as it presents the lowest thermal resistance. The calculated failure temperature during the surge tests is consistent with the aluminum melting phenomenon, which is regarded as the failure mechanism. It was demonstrated that, for a SiC MPS diode, higher bipolar conduction performance is conducive to restraining the joule heat, and a lower thermal resistance design is able to accelerate the heat dissipation and limit the junction temperature during surge events. In this way, the MPS diode using a thinner substrate and advanced layout design technology is able to achieve 60% higher surge current density capability compared to the other technologies.
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Xu, Hongyi, Na Ren, Jiupeng Wu, Zhengyun Zhu, Qing Guo, and Kuang Sheng. "The Impact of Process Conditions on Surge Current Capability of 1.2 kV SiC JBS and MPS Diodes." Materials 14, no. 3 (2021): 663. http://dx.doi.org/10.3390/ma14030663.

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This paper demonstrated the impact of process conditions on the surge current capability of 1.2 kV SiC junction barrier Schottky diode (JBS) and merged PiN Schottky diode (MPS). The influence of ohmic contact and defect density produced by implantation was studied in the simulation. The device fabricated with high temperature implantation had less defect density in the implant region compared with room temperature implantation, which contributed to higher hole injection in surge current mode and 20% surge capability improvement. In addition, with lower P+ ohmic contact resistance, the device had higher surge capability. When compared to device fabrication with a single Schottky metal layer in the device active area, adding additional P+ ohmic contact on top of the P+ regions in the device active area resulted in the pn junctions sharing a greater portion of surge current, and improved the devices’ surge capability by ~10%.
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Heidorn, Christian, Romain Esteve, Tobias Höchbauer, and Roland Rupp. "Investigation on the Effect of Ge Co-Doped Epitaxy on 4H-SiC Based MPS Diodes and Trench MOSFETs." Materials Science Forum 924 (June 2018): 419–22. http://dx.doi.org/10.4028/www.scientific.net/msf.924.419.

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The incorporation of Germanium (Ge) in 4H-SiC has recently being reported as enabling an increase of the electron mobility in n-type doped layers. The present work aims at evaluating the impact of the Ge doping on two types of SiC devices: Merged PiN-Schottky (MPS) diodes and Trench MOSFETs.
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Du, Qiwen, and Xuehui Tao. "The On-Resistance Model of Silicon Carbide Merged PiN Schottky (MPS) Diodes." IOP Conference Series: Materials Science and Engineering 677 (December 10, 2019): 052100. http://dx.doi.org/10.1088/1757-899x/677/5/052100.

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6

Napieralski, Andrzej, Cezary Maj, Michal Szermer, et al. "Recent research in VLSI, MEMS and power devices with practical application to the ITER and dream projects." Facta universitatis - series: Electronics and Energetics 27, no. 4 (2014): 561–88. http://dx.doi.org/10.2298/fuee1404561n.

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Several MEMS (Micro Electro-Mechanical Systems) devices have been analysed and simulated. The new proposed model of SiC MPS (Merged PIN-Schottky) diodes is in full agreement with the real MPS devices. The real size DLL (Dynamic Lattice Liquid) simulator as well as the research on modelling and simulation of modern VLSI devices with practical applications have been presented. Based on experience in the field of ATCA (Advanced Telecommunications Computing Architecture) based systems a proof-of-concept DAQ (data acquisition) system for ITER (International Thermonuclear Experimental Reactor) have been proposed.
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7

Caldwell, Joshua David, Robert E. Stahlbush, Eugene A. Imhoff, et al. "Influence of Shockley Stacking Fault Expansion and Contraction on the Electrical Behavior of 4H-SiC DMOSFETs and MPS diodes." MRS Proceedings 1069 (2008). http://dx.doi.org/10.1557/proc-1069-d10-04.

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ABSTRACTThe forward voltage drop (Vf) increase observed in 4H-SiC bipolar devices such as pin diodes due to recombination-induced Shockley stacking fault (SSF) creation and expansion has been widely discussed in the literature. It was long believed that the deleterious affect of these defects was limited to bipolar devices. However, it was recently reported that forward biasing of the body diode of a 10kV 4H-SiC DMOSFET led to similar Vf increases in the body diode I-V curve as well as a corresponding degradation in the majority carrier conduction characteristics as well and this degradation was believed to be due to the creation and expansion of SSFs during the body diode forward biasing. Here we report measurements comparing the influence of similar stressing, along with annealing and current-induced recovery experiments in DMOSFETs and merged pin-Schottky diodes with the previously reported results of these experiments in 4H-SiC pin diodes. The results of these experiments provide sufficient support that the observed degradation in the majority carrier conduction characteristics is the result of SSF expansion.
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Ryu, Sei-Hyung, Qingchun Zhang, Husna Fatima, Sarah Haney, Robert Stahlbush, and Anant Agarwal. "Degradation of Majority Carrier Conductions and Blocking Capabilities in 4H-SiC High Voltage Devices due to Basal Plane Dislocations." MRS Proceedings 1069 (2008). http://dx.doi.org/10.1557/proc-1069-d07-17.

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ABSTRACTThis paper presents the effect of recombination-induced stacking faults on the drift based forward conduction and leakage currents of high voltage 4H-SiC power devices. To show the effects, 10 kV 4H-SiC MPS (Merged PiN Schottky) diodes have been fabricated on a standard wafer and a low BPD (Basal Plane Dislocation) wafer, and their IV characteristics were evaluated before and after a forward bias stress, which resulted in minority carrier recombination and conductivity modulation in the drift epilayer of the diodes. After the stressing, the diode fabricated on standard wafer showed a significant increase in forward voltage drop, as well as a marked increase in leakage current, which were due to induction of stacking faults. The diode on the low BPD wafer showed very little change after the stress because the induction of stacking faults was minimized. Similar results were also observed on a 10 kV 4H-SiC DMOSFET. The results suggest that recombination-induced stacking faults are detrimental to all device types, and injection of minority carriers in majority carrier devices should be avoided at all times.
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Dissertations / Theses on the topic "Merged-PiN-Schottky (MPS) diode"

1

Niwa, Hiroki. "Breakdown Characteristics in SiC and Improvement of PiN Diodes toward Ultrahigh-Voltage Applications." 京都大学 (Kyoto University), 2016. http://hdl.handle.net/2433/215548.

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2

Chevalier, Florian. "Conception, fabrication et caractérisation de transistors à effet de champ haute tension en carbure de silicium et de leur diode associée." Phd thesis, INSA de Lyon, 2012. http://tel.archives-ouvertes.fr/tel-01016687.

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Dans le contexte des transports plus électriques, les parties mécaniques tendent à être remplacées par leurs équivalents électriques plus petits. Ainsi, le composant lui-même doit supporter un environnement plus sévère et de lourdes contraintes (haute tension, haute température). Les composants silicium deviennent alors inappropriés. Depuis la commercialisation des premières diodes Schottky en 2001, le carbure de silicium est le matériau reconnu mondialement pour la fabrication de dispositifs haute tension avec une forte intégration. Sa large bande d'énergie interdite et son fort champ électrique critique permettent la conception de transistors à effet de champ avec jonction (JFET) pour les hautes tensions ainsi que les diodes associées. Les structures étudiées dépendent de nombreux paramètres, et doivent ainsi être optimisées. L'influence d'un paramètre ne pouvant être isolée, des méthodes mathématiques ont été appelées pour trouver la valeur optimale. Ceci a conduit à la mise en place d'un critère d'optimisation. Ainsi, les deux grands types de structures de JFET verticaux ont pu être analysés finement. D'une part, la recherche d'une structure atteignant les tensions les plus élevées possible a conduit à l'élaboration d'un procédé de fabrication complexe. D'autre part, un souci de simplification et de stabilisation des procédés de fabrication a permis le développement d'un composant plus simple, mais avec une limite en tension un peu plus modeste.
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3

Berthou, Maxime. "Implementation of high voltage Silicon Carbide rectifiers and switches." Phd thesis, INSA de Lyon, 2012. http://tel.archives-ouvertes.fr/tel-00770661.

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In this document, we present ou study about the conception and realization of VMOS and Schottky and JBS Diodes on Silicon Carbide. This work allowed us optimize and fabricate diodes using Tungsten as Schottky barrier on both Schottky and JBS diodes of different blocking capability between 1.2kV and 9kV. Moreover, our study of the VMOS, by considering the overall fabrication process, has permitted to identify the totality of the problems we are facing. Thusly we could ameliorate the devices and try new designs as the VIEMOS or the monolithic integration of temperature and current sensors.
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