Academic literature on the topic 'Metal oxide semiconductors, complementary Algorithms'

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Journal articles on the topic "Metal oxide semiconductors, complementary Algorithms"

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Saggese, Gerardo, Mattia Tambaro, Elia A. Vallicelli, et al. "Comparison of Sneo-Based Neural Spike Detection Algorithms for Implantable Multi-Transistor Array Biosensors." Electronics 10, no. 4 (2021): 410. http://dx.doi.org/10.3390/electronics10040410.

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Real-time neural spike detection is an important step in understanding neurological activities and developing brain-silicon interfaces. Recent approaches exploit minimally invasive sensing techniques based on implanted complementary metal-oxide semiconductors (CMOS) multi transistors arrays (MTAs) that limit the damage of the neural tissue and provide high spatial resolution. Unfortunately, MTAs result in low signal-to-noise ratios due to the weak capacitive coupling between the nearby neurons and the sensor and the high noise power coming from the analog front-end. In this paper we investigate the performance achievable by using spike detection algorithms for MTAs, based on some variants of the smoothed non-linear energy operator (SNEO). We show that detection performance benefits from the correlation of the signals detected by the MTA pixels, but degrades when a high firing rate of neurons occurs. We present and compare different approaches and noise estimation techniques for the SNEO, aimed at increasing the detection accuracy at low SNR and making it less dependent on neurons firing rates. The algorithms are tested by using synthetic neural signals obtained with a modified version of NEUROCUBE generator. The proposed approaches outperform the SNEO, showing a more than 20% increase on averaged sensitivity at 0 dB and reduced dependence on the neuronal firing rate.
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Moses, C. John, D. Selvathi, and V. M. Anne Sophia. "VLSI Architectures for Image Interpolation: A Survey." VLSI Design 2014 (May 19, 2014): 1–10. http://dx.doi.org/10.1155/2014/872501.

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Image interpolation is a method of estimating the values at unknown points using the known data points. This procedure is used in expanding and contrasting digital images. In this survey, different types of interpolation algorithm and their hardware architecture have been analyzed and compared. They are bilinear, winscale, bi-cubic, linear convolution, extended linear, piecewise linear, adaptive bilinear, first order polynomial, and edge enhanced interpolation architectures. The algorithms are implemented for different types of field programmable gate array (FPGA) and/or by different types of complementary metal oxide semiconductor (CMOS) technologies like TSMC 0.18 and TSMC 0.13. These interpolation algorithms are compared based on different types of optimization such as gate count, frequency, power, and memory buffer. The goal of this work is to analyze the different very large scale integration (VLSI) parameters like area, speed, and power of various implementations for image interpolation. From the survey followed by analysis, it is observed that the performance of hardware architecture of image interpolation can be improved by minimising number of line buffer memory and removing superfluous arithmetic elements on generating weighting coefficient.
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Dendouga, Abdelghani, Slimane Oussalah, Damien Thienpont, and Abdenour Lounis. "Multiobjective Genetic Algorithms Program for the Optimization of an OTA for Front-End Electronics." Advances in Electrical Engineering 2014 (August 13, 2014): 1–5. http://dx.doi.org/10.1155/2014/374741.

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The design of an interface to a specific sensor induces costs and design time mainly related to the analog part. So to reduce these costs, it should have been standardized like digital electronics. The aim of the present work is the elaboration of a method based on multiobjectives genetic algorithms (MOGAs) to allow automated synthesis of analog and mixed systems. This proposed methodology is used to find the optimal dimensional transistor parameters (length and width) in order to obtain operational amplifier performances for analog and mixed CMOS-(complementary metal oxide semiconductor-) based circuit applications. Six performances are considered in this study, direct current (DC) gain, unity-gain bandwidth (GBW), phase margin (PM), power consumption (P), area (A), and slew rate (SR). We used the Matlab optimization toolbox to implement the program. Also, by using variables obtained from genetic algorithms, the operational transconductance amplifier (OTA) is simulated by using Cadence Virtuoso Spectre circuit simulator in standard TSMC (Taiwan Semiconductor Manufacturing Company) RF 0.18 μm CMOS technology. A good agreement is observed between the program optimization and electric simulation.
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Lyu, Hong-Kun, Chi-Ho Park, Dong-Hee Han, Seong Kwak, and Byeongdae Choi. "Orchard Free Space and Center Line Estimation Using Naive Bayesian Classifier for Unmanned Ground Self-Driving Vehicle." Symmetry 10, no. 9 (2018): 355. http://dx.doi.org/10.3390/sym10090355.

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In the case of autonomous orchard navigation, researchers have developed algorithms that utilize features, such as trunks, canopies, and sky in orchards, but there are still various difficulties in recognizing free space for autonomous navigation in a changing agricultural environment. In this study, we applied the Naive Bayesian classification to detect the boundary between the trunk and the ground and propose an algorithm to determine the center line of free space. The naïve Bayesian classification requires a small number of samples for training and a simple training process. In addition, it was able to effectively classify tree trunk’s points and noise points of the orchard, which are problematic in vision-based processing, and noise caused by small branches, soil, weeds, and tree shadows on the ground. The performance of the proposed algorithm was investigated using 229 sample images obtained from an image acquisition system with a Complementary Metal Oxide Semiconductor (CMOS) Image Sensor (CIS) camera. The center line detected by the unaided-eye manual decision and the results extracted by the proposed algorithm were compared and analyzed for several parameters. In all compared parameters, extracted center line was more stable than the manual center line results.
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Gao, Zhenyi, Bin Zhou, Xiang Li, Lei Yang, Qi Wei, and Rong Zhang. "A Digital-Analog Hybrid System-on-Chip for Capacitive Sensor Measurement and Control." Sensors 21, no. 2 (2021): 431. http://dx.doi.org/10.3390/s21020431.

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Sensors based on capacitance detection are common in the field of inertial measurement and have the potential for miniaturization and low power consumption. In order to control and process such sensors, a novel digital-analog hybrid system-on-chip (SoC) is designed and implemented. The system includes a capacitor to voltage (C/V) conversion circuit and a band-pass sigma-delta modulator (BPSDM) as the analog-to-digital converter (ADC). The digital signal is processed by the dedicated circuit module based on the least mean square error demodulation (LMSD) algorithm on the chip. The low-power Cortex-M3 processor supports software implementation of control algorithms and circuit parameter configuration. The control signal is output through a digital BPSDM. The chip was taped out under SMIC 180 nm Complementary Metal Oxide Semiconductor (CMOS) technology and tested for performance. The result shows that the maximum operating frequency of the chip is 105 MHz. The total area is 77.43 mm2. When the system clock is set to 51.2 MHz, the static power consumption and dynamic power consumption of the digital system are 18 mW and 54 mW respectively.
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6

Zhang, Shaohui, Guocheng Zhou, Ying Wang, Yao Hu, and Qun Hao. "A Simply Equipped Fourier Ptychography Platform Based on an Industrial Camera and Telecentric Objective." Sensors 19, no. 22 (2019): 4913. http://dx.doi.org/10.3390/s19224913.

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Fourier ptychography microscopy (FPM) is a recently emerged computational imaging method, which combines the advantages of synthetic aperture and phase retrieval to achieve super-resolution microscopic imaging. FPM can bypass the diffraction limit of the numerical aperture (NA) system and achieve complex images with wide field of view and high resolution (HR) on the basis of the existing microscopic platform, which has low resolution and wide field of view. Conventional FPM platforms are constructed based on basic microscopic platform and a scientific complementary metal–oxide–semiconductor (sCMOS) camera, which has ultrahigh dynamic range. However, sCMOS, or even the microscopic platform, is too expensive to afford for some researchers. Furthermore, the fixed microscopic platform limits the space for function expansion and system modification. In this work, we present a simply equipped FPM platform based on an industrial camera and telecentric objective, which is much cheaper than sCMOS camera and microscopic platform and has accurate optical calibration. A corresponding algorithm was embedded into a conventional FP framework to overcome the low dynamic range of industrial cameras. Simulation and experimental results showed the feasibility and good performance of the designed FPM platform and algorithms.
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Gao, Zhenyi, Bin Zhou, Xiang Li, Lei Yang, Qi Wei, and Rong Zhang. "A Digital-Analog Hybrid System-on-Chip for Capacitive Sensor Measurement and Control." Sensors 21, no. 2 (2021): 431. http://dx.doi.org/10.3390/s21020431.

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Sensors based on capacitance detection are common in the field of inertial measurement and have the potential for miniaturization and low power consumption. In order to control and process such sensors, a novel digital-analog hybrid system-on-chip (SoC) is designed and implemented. The system includes a capacitor to voltage (C/V) conversion circuit and a band-pass sigma-delta modulator (BPSDM) as the analog-to-digital converter (ADC). The digital signal is processed by the dedicated circuit module based on the least mean square error demodulation (LMSD) algorithm on the chip. The low-power Cortex-M3 processor supports software implementation of control algorithms and circuit parameter configuration. The control signal is output through a digital BPSDM. The chip was taped out under SMIC 180 nm Complementary Metal Oxide Semiconductor (CMOS) technology and tested for performance. The result shows that the maximum operating frequency of the chip is 105 MHz. The total area is 77.43 mm2. When the system clock is set to 51.2 MHz, the static power consumption and dynamic power consumption of the digital system are 18 mW and 54 mW respectively.
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8

Zhang, Yu, Guangyi Wang, and Jiangtao Xu. "Parameter Estimation of Signal-Dependent Random Noise in CMOS/CCD Image Sensor Based on Numerical Characteristic of Mixed Poisson Noise Samples." Sensors 18, no. 7 (2018): 2276. http://dx.doi.org/10.3390/s18072276.

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Parameter estimation of Poisson-Gaussian signal-dependent random noise in the complementary metal-oxide semiconductor/charge-coupled device image sensor is a significant step in eliminating noise. The existing estimation algorithms, which are based on finding homogeneous regions, acquire the pair of the variances of noise and the intensities of every homogeneous region to fit the linear or piecewise linear curve and ascertain the noise parameters accordingly. In contrast to the existing algorithms, in this study, the Poisson noise samples of all homogeneous regions in every block image are pieced together to constitute a larger sample following the mixed Poisson noise distribution; then, the mean and variance of the mixed Poisson noise sample are deduced. Next, the mapping function among the noise parameters to be estimated—variance of Poisson-Gaussian noise and that of Gaussian noise corresponding to the stitched region in every block image—is constructed. Finally, the unbiased estimations of noise parameters are calculated from the mapping functions of all the image blocks. The experimental results confirm that the proposed method can obtain lower mean absolute error values of estimated noise parameters than the conventional ones.
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Ou, Qiao-Feng, Bang-Shu Xiong, Lei Yu, Jing Wen, Lei Wang, and Yi Tong. "In-Memory Logic Operations and Neuromorphic Computing in Non-Volatile Random Access Memory." Materials 13, no. 16 (2020): 3532. http://dx.doi.org/10.3390/ma13163532.

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Recent progress in the development of artificial intelligence technologies, aided by deep learning algorithms, has led to an unprecedented revolution in neuromorphic circuits, bringing us ever closer to brain-like computers. However, the vast majority of advanced algorithms still have to run on conventional computers. Thus, their capacities are limited by what is known as the von-Neumann bottleneck, where the central processing unit for data computation and the main memory for data storage are separated. Emerging forms of non-volatile random access memory, such as ferroelectric random access memory, phase-change random access memory, magnetic random access memory, and resistive random access memory, are widely considered to offer the best prospect of circumventing the von-Neumann bottleneck. This is due to their ability to merge storage and computational operations, such as Boolean logic. This paper reviews the most common kinds of non-volatile random access memory and their physical principles, together with their relative pros and cons when compared with conventional CMOS-based circuits (Complementary Metal Oxide Semiconductor). Their potential application to Boolean logic computation is then considered in terms of their working mechanism, circuit design and performance metrics. The paper concludes by envisaging the prospects offered by non-volatile devices for future brain-inspired and neuromorphic computation.
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10

Li, Qingyang, Ruofei Zhong, and Ya Wang. "A Method for the Destriping of an Orbita Hyperspectral Image with Adaptive Moment Matching and Unidirectional Total Variation." Remote Sensing 11, no. 18 (2019): 2098. http://dx.doi.org/10.3390/rs11182098.

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The Orbita hyperspectral satellite (OHS) is the first hyperspectral satellite with surface coating technology for sensors in the world. It includes 32 bands from visible to near-infrared wavelengths. However, technology such as the fabricating process of complementary metal–oxide–semiconductor (CMOS) sensors makes the image contain a lot of random and unsystematic stripe noise, which is so bad that it seriously affects visual interpretation, object recognition and the application of the OHS data. Although a large number of stripe removal algorithms have been proposed, very few of them take into account the characteristics of OHS sensors and analyze the causes of OHS data noise. In this paper, we propose a destriping algorithm for OHS data. Firstly, we use both the adaptive moment matching method and multi-level unidirectional total variation method to remove stripes. Then a model based on piecewise linear least squares fitting is proposed to restore the vertical details lost in the first step. Moreover, we further utilize the spectral information of the OHS image, and extend our 2-D destriping method to the 3-D case. Results demonstrate that the proposed method provides the optimal destriping result on both qualitative and quantitative assessments. Moreover, the experimental results show that our method is superior to the existing single-band and multispectral destriping methods. Also, we further use the algorithm to the stripe noise removal of other real remote sensing images, and excellent image quality is obtained, which proves the universality of the algorithm.
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Dissertations / Theses on the topic "Metal oxide semiconductors, complementary Algorithms"

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Shum, Roger Chi Fai Carleton University Dissertation Engineering Electrical. "A timing macro model for performance optimization of CMOS logic circuits." Ottawa, 1992.

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Bachelu, Carol R. Carleton University Dissertation Engineering Electrical. "A Topological single-layer routing algorithm and its application to leaf cell synthesis." Ottawa, 1992.

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Ramirez, Ortiz Rolando Carleton University Dissertation Engineering Electrical. "Technology mapping algorithms for CMOS dynamic logic circuits." Ottawa, 1992.

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Wang, Yan. "Predictive boundary point adaptation and vector quantization compression algorithms for CMOS image sensors /." View abstract or full-text, 2007. http://library.ust.hk/cgi/db/thesis.pl?ECED%202007%20WANGY.

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Lee, Jungwon. "Efficient image compression system using a CMOS transform imager." Diss., Atlanta, Ga. : Georgia Institute of Technology, 2009. http://hdl.handle.net/1853/31825.

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Thesis (Ph.D)--Electrical and Computer Engineering, Georgia Institute of Technology, 2010.<br>Committee Chair: Anderson, David; Committee Member: Dorsey, John; Committee Member: Hasler, Paul; Committee Member: Kang, Sung Ha; Committee Member: Romberg, Justin. Part of the SMARTech Electronic Thesis and Dissertation Collection.
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Ashouei, Maryam. "Algorithms and Methodology for Post-Manufacture Adaptation to Process Variations and Induced Noise in Deeply Scaled CMOS Technologies." Diss., Georgia Institute of Technology, 2007. http://hdl.handle.net/1853/19859.

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In the last two decades, VLSI technology scaling has spurred a rapid growth in the semiconductor industry. With CMOS device dimensions falling below 100 nm, achieving higher performance and packing more complex functionalities into digital integrated circuits have become easier. However, the scaling trend poses new challenges to design and process engineers. First, larger process parameter variations in the current technologies cause larger spread in the delay and power distribution of circuits and result in the parametric yield loss. In addition, ensuring the reliability of deep sub-micron (DSM) technologies under soft/transient errors is a significant challenge. These errors occur because of the combined effects of the atmospheric radiations and the significantly reduced noise margins of scaled technologies. This thesis focuses on addressing the issues related to the process variations and reliability in deeply scaled CMOS technologies. The objective of this research has been to develop circuit-level techniques to address process variations, transient errors, and the reliability concern. The proposed techniques can be divided into two parts. The first part addresses the process variation concern and proposes techniques to reduce the variation effects on power and performance distribution. The second part deals with the transient errors and techniques to reduce the effect of transient errors with minimum hardware or computational overhead.
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Nehl, Albert Henry. "Investigation of techniques for high speed CMOS arbitrary waveform generation." PDXScholar, 1990. https://pdxscholar.library.pdx.edu/open_access_etds/4109.

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Today a growing number of applications in design engineering, production and environmental testing, and system service require specific analog waveforms and digital patterns. Such requirements are neither satisfactorily nor easily met by the use of standard function or single purpose, custom generators. Traditional methods of waveform generation suffer from undesirable complexity or mediocre performance and are otherwise limited. For the majority of arbitrary waveform generation applications, including medical engineering, modal analysis and electronic engineering, direct digital synthesis techniques are satisfactory. Direct digital synthesis, based generally on periodic retrieval of predetermined amplitude values, may be used to 2 generate such waveforms. Within the limits imposed by the system's maximum sample rate and the Nyquist criteria, any waveform may be produced using these techniques. The objective of this inquiry, within a particular set of constraints, is to extend the cost/performance envelope of direct digital synthesis techniques for the generation of arbitrary waveforms. Performance is enhanced, particularly in the areas of output bandwidth and signal purity.
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Nisar, Muhammad Mudassar. "Robust low-power signal processing and communication algorithms." Diss., Georgia Institute of Technology, 2010. http://hdl.handle.net/1853/33872.

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This thesis presents circuit-level techniques for soft error mitigation, low-power design with performance trade-off, and variation-tolerant low-power design. The proposed techniques are divided into two broad categories. First, error compensation techniques, which are used for soft error mitigation and also for low-power operation of linear and non-linear filters. Second, a framework for variation tolerant low-power operation of wireless devices is presented. This framework analyzes the effects of circuit "tuning knobs" such as voltage, frequency, wordlength precision, etc. on system performance, and power efficiency. Process variations are considered as well, and the best operating tuning knob levels are determined, which results in maximum system wide power savings while keeping the system performance within acceptable limits. Different methods are presented for variation-tolerant and power-efficient wireless communication. Techniques are also proposed for application driven low-power operation of the OFDM baseband receiver.
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Al-Ahmadi, Ahmad Aziz. "Complementary orthogonal stacked metal oxide semiconductor a novel nanoscale complementary metal oxide semiconductor architecture /." Ohio : Ohio University, 2006. http://www.ohiolink.edu/etd/view.cgi?ohiou1147134449.

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Gurcan, Zeki B. "0.18 [mu]m high performance CMOS process optimization for manufacturability /." Online version of thesis, 2005. http://hdl.handle.net/1850/5197.

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Books on the topic "Metal oxide semiconductors, complementary Algorithms"

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Zhao, Yi. Wafer level reliability of advanced CMOS devices and processes. Nova Science Publishers, 2008.

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Lancaster, Don. CMOS cookbook. 2nd ed. H.W. Sams, 1988.

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M, Berlin Howard, ed. CMOS cookbook. 2nd ed. Newnes, 1997.

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F, Hawkins Charles, ed. CMOS electronics: How it works, how it fails. IEEE Press, 2004.

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Helms, Harry L. High-speed (HC/HCT) CMOS guide. Prentice Hall, 1989.

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Kwon, Min-jun. CMOS technology. Nova Science Publishers, 2010.

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Shoji, Masakazu. CMOS digital circuit technology. Prentice Hall, 1988.

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Pfaffli, Paul. Characterisation of degradation and failure phenomena in MOS devices. Hartung-Gorre, 1999.

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Shriram, Ramanathan, Symposium J, "Materials and Devices for Beyond CMOS Scaling" (2010 : San Francisco, Calif.), and Materials Research Society, eds. Materials and devices for end-of-roadmap and beyond CMOS scaling: Symposium held April 5-9, 2010, San Francisco, California. Materials Research Society, 2010.

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J, Branning D., ed. Experiments in CMOS technology. Tab Books, 1988.

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Book chapters on the topic "Metal oxide semiconductors, complementary Algorithms"

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Munteanu, Daniela, and Jean-Luc Autran. "Interactions between Terrestrial Cosmic-Ray Neutrons and III–V Compound Semiconductors." In Modeling and Simulation in Engineering - Selected Problems. IntechOpen, 2020. http://dx.doi.org/10.5772/intechopen.92774.

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This work explores by numerical simulation the impact of high-energy atmospheric neutrons and their interactions with III–V binary compound semiconductors. The efforts have focused on eight III–V semiconductors: GaAs, AlAs, InP, InAs, GaSb, InSb, GaN, and GaP. For each material, extensive Geant4 numerical simulations have been performed considering a bulk target exposed to a neutron source emulating the atmospheric neutron spectrum at terrestrial level. Results emphasize in detail the reaction rates per type of reaction (elastic, inelastic, nonelastic) and offer a classification of all the neutron-induced secondary products as a function of their atomic number, kinetic energy, initial stopping power, and range. Implications for single-event effects (SEEs) are analyzed and discussed, notably in terms of energy and charge deposited in the bulk material and in the first nanometers of particle range with respect to the critical charge for modern complementary metal oxide semiconductor (CMOS) technologies.
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Conference papers on the topic "Metal oxide semiconductors, complementary Algorithms"

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Osseily, Hassan Amine, and Ali Massoud Haidar. "Octal to binary conversion using multi-input floating gate complementary metal oxide semiconductors." In 2011 10th International Symposium on Signals, Circuits and Systems (ISSCS). IEEE, 2011. http://dx.doi.org/10.1109/isscs.2011.5978644.

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Osseily, Hassan Amine, and Ali Massoud Haidar. "Hexadecimal to binary conversion using multi-input floating gate complementary metal oxide semiconductors." In 2015 International Conference on Applied Research in Computer Science and Engineering (ICAR). IEEE, 2015. http://dx.doi.org/10.1109/arcse.2015.7338134.

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Gillet, Jean-Numa, Yann Chalopin, and Sebastian Volz. "Atomic-Scale Three-Dimensional Phononic Crystals With a Lower Thermal Conductivity Than the Einstein Limit of Bulk Silicon." In ASME 2008 Heat Transfer Summer Conference collocated with the Fluids Engineering, Energy Sustainability, and 3rd Energy Nanotechnology Conferences. ASMEDC, 2008. http://dx.doi.org/10.1115/ht2008-56403.

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Extensive research about superlattices with a very low thermal conductivity was performed to design thermoelectric materials. Indeed, the thermoelectric figure of merit ZT varies with the inverse of the thermal conductivity but is directly proportional to the power factor. Unfortunately, as nanowires, superlattices reduce heat transfer in only one main direction. Moreover, they often show dislocations owing to lattice mismatches. Therefore, fabrication of nanomaterials with a ZT larger than the alloy limit usually fails with the superlattices. Self-assembly is a major epitaxial technology to fabricate ultradense arrays of germaniums quantum dots (QD) in a silicon matrix for many promising electronic and photonic applications as quantum computing. We theoretically demonstrate that high-density three-dimensional (3-D) periodic arrays of small self-assembled Ge nanoparticles (i.e. the QDs), with a size of some nanometers, in Si can show a very low thermal conductivity in the three spatial directions. This property can be considered to design thermoelectric devices, which are compatible with the complementary metal-oxide-semiconductor (CMOS) technologies. To obtain a computationally manageable model of these nanomaterials, we simulate their thermal behavior with atomic-scale 3-D phononic crystals. A phononic-crystal period (supercell) consists of diamond-like Si cells. At each supercell center, we substitute Si atoms by Ge atoms in a given number of cells to form a box-like Ge nanoparticle. The phononic-crystal dispersion curves, which are computed by classical lattice dynamics, are flat compared to those of bulk Si. In an example phononic crystal, the thermal conductivity can be reduced below the value of only 0.95 W/mK or by a factor of at least 165 compared to bulk silicon at 300 K. Close to the melting point of silicon, we obtain a larger decrease of the thermal conductivity below the value of 0.5 W/mK, which is twice smaller than the classical Einstein Limit of single crystalline Si. In this paper, we use an incoherent-scattering approach for the nanoparticles. Therefore, we expect an even larger decrease of the phononic-crystal thermal conductivity when multiple-scattering effects, as multiple reflections and diffusions of the phonons between the Ge nanoparticles, will be considered in a more realistic model. As a consequence of our simulations, a large ZT could be achieved in 3-D ultradense self-assembled Ge nanoparticle arrays in Si. Indeed, these nanomaterials with a very small thermal conductivity are crystalline semiconductors with a power factor that can be optimized by doping using CMOS-compatible technologies, which is not possible with other recently-proposed nanomaterials.
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