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Journal articles on the topic 'Modified Carry Select Adder (MCSLA)'

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Published: 2 June 2025

Last updated: 31 July 2025

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1

Pallavi, Saxena, Purohit Urvashi, and Joshi Priyanka. "Analysis of Low Power, Area- Efficient and High Speed Fast Adder." International Journal of Advanced Research in Computer and Communication Engineering 2, no. 9 (2013): 3705–10. https://doi.org/10.5281/zenodo.32567.

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In electronics, adder is a digital circuit that performs addition of numbers. To perform fast arithmetic operations, carry select adder (CSLA) is one of the fastest adders used in many data- processing processors. The structure of CSLA is such that there is further scope of reducing the area, delay and power consumption. Simple and efficient gate – level modification is used in order to reduce the area, delay and power of CSLA. Based on the modifications, 8-bit, 16-bit, 32-bit and 64-bit architectures of CSLA are designed and compared. In this paper, conventional CSLA is compared with Mo

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2

J.Ponmalar, T.R.Sureshkumar, and T.Kowsalya. "Low Power, Area- Efficient and High Speed Fast Adder for Processing Element." International Journal of Innovative Research in Science, Engineering and Technology 4, no. 6 (2015): 946–54. https://doi.org/10.5281/zenodo.33096.

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In electronics, adder is a digital circuit that performs addition of numbers. To perform fast arithmetic operations, carry select adder (CSLA) is one of the fastest adders used in many data- processing processors. The structure of CSLA is such that there is further scope of reducing the area, delay and power consumption. Simple and efficient gate – level modification is used in order to reduce the area, delay and power of CSLA. Based on the modifications, 8-bit, 16-bit, 32-bit and 64-bit architectures of CSLA are designed and compared. In this paper, conventional CSLA is compared with Mo

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3

Pallavi, Saxena, Purohit Urvashi, and Joshi Priyanka. "Design of Low Power, Area-Efficient Carry Select Adder." International Journal of Engineering Research & Technology 2, no. 10 (2013): 3582–86. https://doi.org/10.5281/zenodo.32569.

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Design of low power and area-efficient logic systems forms an integral part and largest areas of research in the field of VLSI Design. Addition is the most fundamental arithmetic operation. In this paper, a low power, area-efficient carry select adder is proposed. CSA is one of the fastest adders used in dataprocessing systems to perform fast arithmetic operation. Secondly, structure of carry select adder is such that there is scope of reducing the area and power consumption. Thirdly, there is scope to reduce the area by using some add-one scheme. So, a Modified Carry Select Adder(MCSA) is des

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4

Pallavi, Saxena, Purohit Urvashi, and Joshi Priyanka. "Design of Low Power, Area-Efficient Carry Select Adder." International Journal of Engineering Research & Technology 2, no. 10 (2013): 3582–86. https://doi.org/10.5281/zenodo.33081.

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Design of low power and area-efficient logic systems forms an integral part and largest areas of research in the field of VLSI Design. Addition is the most fundamental arithmetic operation. In this paper, a low power, area-efficient carry select adder is proposed. CSA is one of the fastest adders used in dataprocessing systems to perform fast arithmetic operation. Secondly, structure of carry select adder is such that there is scope of reducing the area and power consumption. Thirdly, there is scope to reduce the area by using some add-one scheme. So, a Modified Carry Select Adder(MCSA) is des

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5

Agnes, Shiny Rachel, and Rajakumar.G. "Design and Implementation of 256 Bit Modified Square Root Carry Select Adder for Area and Delay Reduction." International Journal of Engineering and Advanced Technology (IJEAT) 9, no. 3 (2019): 407–10. https://doi.org/10.35940/ijeat.B3271.129219.

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This paper models the behaviour of modified Square Root Carry Select Adder and goes deep to investigate on its scope of reducing area and delay. This helps to overcome the drawback of conventional RCA by performing operations simultaneously for both Cin = 0 and Cin = 1, and the output is multiplexed to obtain the desired response. The work explores opportunities to reduce the area with introduction of BEC logic instead of second block RCA. The implementation of a 4 bit MCSLA and its capability of extending its word size to 8, 16, 32, 64, 128 and 256 bits are presented. The experimental result

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6

K., Periyarselvam, Saravanakumar G., and Anand M. "A Novel Architecture of Radix-3 Singlepath Delay Feedback (R3SDF) FFT Using MCSLA." Indonesian Journal of Electrical Engineering and Computer Science 10, no. 1 (2018): 37–42. https://doi.org/10.11591/ijeecs.v10.i1.pp37-42.

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Fast Fourier transform (FFT) is widely used in digital signal processing and telecommunications, particularly in orthogonal frequency division multiplexing systems, to overcome the problems associated with orthogonal subcarriers. A new algorithm of radix-3 FFT has been introduced in this work. The DFT of length N can be realized from three DFT sequences; each of length N/3.Radix-3 algorithm reduces the number of multiplications required for realizing DFT.A novel design of Radix-3pipelined Single path Delay Feedback (R3SDF) FFT using MCSLA has been proposed in this paper. First, the pipelined r

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K, Periyarselvam, Saravanakumar G, and Anand M. "A Novel Architecture of Radix-3 Singlepath Delay Feedback (R3SDF) FFT Using MCSLA." Indonesian Journal of Electrical Engineering and Computer Science 10, no. 1 (2018): 37. http://dx.doi.org/10.11591/ijeecs.v10.i1.pp37-42.

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Fast Fourier transform (FFT) is widely used in digital signal processing and telecommunications, particularly in orthogonal frequency division multiplexing systems, to overcome the problems associated with orthogonal subcarriers. A new algorithm of radix-3 FFT has been introduced in this work. The DFT of length N can be realized from three DFT sequences; each of length N/3.Radix-3 algorithm reduces the number of multiplications required for realizing DFT.A novel design of Radix-3pipelined Single path Delay Feedback (R3SDF) FFT using MCSLA has been proposed in this paper. First, the pipelined r

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8

Nalina, R., S. S. Ashwini, and M. Z. Kurian Dr. "Implementation of Unsigned Multiplier Using Area-Delay-Power Efficient Adder." International Journal for Research in Applied Science & Engineering Technology 3, no. 7 (2015): 429–32. https://doi.org/10.5281/zenodo.33100.

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Multiplication and addition are most widely and oftenly used arithmetic computations performed in all digital signal processing applications. Multiplication is the basic arithmetic operation which is present in many part of the digital computer especially in signal processing systems such as graphics and computation system. It requires substantially more hardware resources and processing time than addition and subtraction. In fact, 8.72% of all the instruction in typical processing units is multiplication. This paper deals with the basic multiplier that is shift and add multiplier. Accurate op

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9

K, P. Heena. "A Comparative Study on Ripple Carry Adder and Modified Square Root Carry Select Adder in Radix-4 8*8 Booth Multiplier." International Journal of Innovative Science and Research Technology (IJISRT) 9, no. 2 (2024): 4. https://doi.org/10.5281/zenodo.10784386.

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In digital circuits multiplication is a fundamental operation, extensively utilized in various computational tasks. The efficiency and performance of the multiplier circuit significantly impact the overall system performances, especially in applications demanding high-speed computation with minimal power consumption. This study presents a comparative analysis between two distinct implementations of Radix-4 8*8 Booth multiplier employing different adder architectures: Ripple carry adder and Modified Square Root Carry select adder. Multiplier with modified square root carry select adder reduced

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10

Ms. Mayuri Ingole. "Modified Low Power Binary to Excess Code Converter." International Journal of New Practices in Management and Engineering 4, no. 03 (2015): 06–10. http://dx.doi.org/10.17762/ijnpme.v4i03.38.

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Utilization of power is a major aspect in the design of integrated circuits. Since, adders are mostly employed in these circuits, we should design them effectively. Here, we propose an easy and effective method in decreasing the maximum consumption of power. Carry Select Adder is the one which is dependent on the design of two adders. We present a high performance low-power adder that is implemented. Also, here in Carry Select Adder, Binary Excess Code-1is replaced by Ripple Carry Adder. After analyzing the results, we can come to a conclusion that the architecture which is proposed will have

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11

S., Nithin, and Ramesh K.B. "Design of High Speed Carry Select Adder Using Kogge-Stone and Carry-Lookahead Adders." Recent Trends in Analog Design and Digital Devices 7, no. 3 (2024): 23–33. https://doi.org/10.5281/zenodo.13709580.

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<em>The adder is acknowledged as the fundamental component in various arithmetic and logical operations. In efforts to enhance operational efficiency, the Carry Select Adder (CSLA) has been devised. By integrating multiple high-speed adder logics within a conventional CSLA framework, operational speed is further enhanced. This study presents the design of a hybrid CSLA that amalgamates the advantages of both Kogge Stone Adder and Look Ahead Adder (CLA) methodologies to achieve superior performance. Kogge Stone Adder, distinguished for its rapid carry generation, is incorporated to bolster spee

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12

Anand, B., and V. V. Teresa. "Improved Modified Area Efficient Carry Select Adder (MAE-CSLA) Without Multiplexer." Journal of Computational and Theoretical Nanoscience 14, no. 1 (2017): 269–76. http://dx.doi.org/10.1166/jctn.2017.6316.

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The Carry Select Adder (CSLA) is the fastest adders that perform arithmetic operations in many processors. There are lot of modifications that are proposed to reduce the area of CSLA one such efficient technique is presented in this paper. Here the area is reduced by eliminating the multiplexer that selects the carry in of regular CSLA by using a simple XOR gate. Here the XOR gate is used to generate the first sum output of the ripple carry adders in the second stage of the CSLA adder. Then the XOR gate is implemented with AOI. This AOI implementation will further reduce the area consumption o

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13

Dhandapani, Vaithiyanathan. "An efficient architecture for carry select adder." World Journal of Engineering 14, no. 3 (2017): 249–54. http://dx.doi.org/10.1108/wje-08-2016-0043.

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Purpose Adders play a vital role in almost all digital designs, as all four arithmetic operations can be confined within addition. Hence, area and power optimization of the adders will result in overall circuit optimization. Being the fastest adder, the carry select adder (CSLA) gains higher importance among the different adder styles. However, it suffers from the drawback of increased power and area. The implementation of CSLA in digital circuits requires lots of study for optimization. Hence, to overcome this problem, various improvements were made to the CSLA structure to reduce area and, c

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14

A., Mounika, and Srinivasa Reddy K. "Designing and Performance Evaluation of Carry Select Adder." International Journal of VLSI System Design and Communication systems 3, no. 5 (2015): 0754–57. https://doi.org/10.5281/zenodo.48670.

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In electronics, adder is a digital circuit that performs addition of numbers. To perform fast arithmetic operations, carry select adder (CSA) is one of the fastest adder in processor architectures. This paper presents a modified carry select adder(CSA) that operates at low power and proves more area and delay efficient. Validation of the logic is done through extensive simulations for measuring the power and delay. Simple and efficient gate level modification is used in order to reduce the area, delay and power of CSA.The result analysis shows that the proposed structure(CSA CBL) is better tha

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15

PinnikaVenkateswarlu and Kalpana Ragutla. "An Efficient SQRT Architecture of Carry Select Adder Design by HA and Common Boolean Logic." SSRG International Journal of Electronics and Communication Engineering 1, no. 8 (2014): 36–41. https://doi.org/10.5281/zenodo.33082.

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As we are aware that carry select adder is the fastest one amongdata processing element, on the other hand due to having pairs of ripple carry adder structure traditional carry select adder consumes more area. So proposed scheme is to developa low power and low area half adder based (CSLA) using simple using common Boolean logic (CBL), where it employs one half adders to perform the summation operation for the common Boolean logic (CBL) and carry zero respectively. Half adder and CBL have to be designed where half adder requires one XOR gate, one AND gate where CBL requires only one NOT as wel

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16

Ramani, P., G. Priya, Murala Chandana, T. Sharmila, Seeram Tejaswi, and M. Manjushri. "Low Power 256-bit Modified Carry Select Adder." Research Journal of Applied Sciences, Engineering and Technology 8, no. 10 (2014): 1212–16. http://dx.doi.org/10.19026/rjaset.8.1086.

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17

Sasipriya, S., and R. Arun Sekar. "Vedic Multiplier Design Using Modified Carry Select Adder with Parallel Prefix Adder." Journal of Computational and Theoretical Nanoscience 16, no. 5 (2019): 1927–37. http://dx.doi.org/10.1166/jctn.2019.7826.

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18

Hebbar, Abhishek R., Piyush Srivastava, and Vinod Kumar Joshi. "Design of High Speed Carry Select Adder using Modified Parallel Prefix Adder." Procedia Computer Science 143 (2018): 317–24. http://dx.doi.org/10.1016/j.procs.2018.10.402.

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19

A., Nithya, G. Priyanka A., Ajitha B., Gracia Nirmala Rani D., and Rajaram S. "FPGA Implementation of Low Power and Area Efficient Carry Select Adder." International Journal of Enhanced Research in Science Technology & Engineering 3, no. 7 (2014): 321–27. https://doi.org/10.5281/zenodo.33237.

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In this paper, we have proposed a modified carry select adder which is known as fastest adders that can perform arithmetic operations in Digital signal processors. Modification in the gate level of the Square root Carry Select Adder (SQRT CSLA) structure results in the reduction of area and power of the CSLA structure which offers a simple and efficient function. Depending upon the Regular SQRT CSLA, we have modified the structure of the adders. The proposed design for 128-bit modified CSLA has reduced area and power as compared with the regular SQRT CSLA with only a slight increase in the del

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20

Hossain, Muhammad Saddam, and Farhadur Arifin. "Design and Evaluation of a 32-bit Carry Select Adder using 4-bit Hybrid CLA Adder." AIUB Journal of Science and Engineering (AJSE) 20, no. 2 (2021): 1–7. http://dx.doi.org/10.53799/ajse.v20i2.119.

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Adder circuits play a remarkable role in modern microprocessor. Adders are widely used in critical paths of arithmetic operation such as multiplication and subtraction. A Carry Select Adder (CSA) design methodology using a modified 4-bit Carry Look-Ahead (CLA) Adder has been proposed in this research. The proposed 4-bit CLA used hybrid logic style based logic circuits for Carry Generate (Gi) and Carry Propagate (Pi) functions in order to improve performance and reduce the number of transistor used. The modified 4-bit CLA is used as the basic unit for implementation of 32-bit CSA. The proposed

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21

M.Bommi, R., and Dr S.SelvakumarRaja. "A novel design of low-power reversible carry selects adder employing MPFA." International Journal of Engineering & Technology 7, no. 4 (2019): 4780–84. http://dx.doi.org/10.14419/ijet.v7i4.23138.

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In VLSI technology, power dissipation is of major concern next to speed. Due to development in technology, the necessity of fast an efficient high performance processing units has become inevitable. The circuitry of Carry Select Adder (CSLA) promises rapid dispensation in ALU and furthermore optimization can be accomplished. The proposed work encompasses the makeup of reversible design of Carry Select Adder using Modified Peres Full Adder (MPFA) and Fredkin Gate (FG). It is observed that the proposed CSLA is area efficient and attained 70% low power dissipation. The reversible CSLA is synthesi

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22

Yogayata, Shrivastava, Verma Tarun, and Jain Rita. "Design and Implementation of Low Power High Speed 32-Bit HCSA." International Journal of VLSI and Embedded Systems 5 (April 17, 2014): 893–98. https://doi.org/10.5281/zenodo.33236.

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In the design of carry select adder, the requirement of area, speed and power consumption is of prime importance. Power dissipation is one of the most important design objectives in integrated circuits, after speed. Carry select adder (CSLA) is one of the fast adder used to perform fast arithmetic operations as we select the carry beforehand and calculate the sum output for both the carry conditions i.e. for Cin=1 or Cin=0. The most fundamental arithmetic operations in any ALU is addition. It has been ranked the most extensively used operation among a set of real-time digital signal processing

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23

Priya, Meshram, Mahendra Mithilesh, and Jawarkar Parag. "Designed Implementation of Modified Area Efficient Enhanced Square Root Carry Select Adder." International Journal for Research in Emerging Science and Technology 2, no. 5 (2015): 96–99. https://doi.org/10.5281/zenodo.33092.

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In the design of Integrated Circuits, area occupancy plays a vital role because of increasing the necessity of portable systems. Carry Select Adder (CSLA) is one of the fastest adders used in many data-processing processors to perform fast arithmetic functions. In this paper, an area-efficient carry select adder by sharing the common Boolean logic term (CBL) with BEC is proposed. After logic simplification and sharing partial circuit, only one XOR gate and one inverter gate in each summation operation as well as one AND gate and one inverter gate in each carry-out operation are needed. Based o

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Gurusamy, L., Muhammad Kashif, and Norhuzaimin Julai. "Design and Implementation of an Efficient Hybrid Parallel-Prefix Ling Adder Using 0.18micron CMOS Technology in Standard Cell Library." Applied Mechanics and Materials 833 (April 2016): 149–56. http://dx.doi.org/10.4028/www.scientific.net/amm.833.149.

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This This paper addresses a novel technique in implementing hybrid parallel-prefix adder (HPA) incorporating prefix-tree structure with Carry Select Adder (CSEA). Ling’s algorithm is used to optimise the pre-processing blocks (white nodes) and intermediate Generate-Propagate blocks (Black nodes) of the prefix tree to minimise the congestion of wires which contributes to reduction in chip size and to improve performance. The resulting prefix-tree arrangement is then merged into a sequence of modified CSEA. Experimental results show that HPA has speed improvement of 62% and 13% power reduction i

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Priya, Meshram, and Sarode Prof.Mamta. "Designing of Modified Area Efficient Square Root Carry Select Adder(SQRT CSLA)." Journal of Emerging Technologies and Innovative Research 2, no. 3 (2015): 530–33. https://doi.org/10.5281/zenodo.33087.

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In the design of Integrated Circuits, The necessity of portable systems is increasing an area occupancy plays a vital role. Square Root Carry Select Adder (SQRT CSLA) is one of the fastest adders which is used in this data-processing processor to perform fast arithmetic functions. In this paper, an area-efficient square root carry select adder(SQRT CSLA design) by sharing Common Boolean logic term (CBL) is proposed The modified architecture has been developed using Binary to Excess-1 converter (BEC). Based on this modification 8-, 16-, 32-, and 64-b square-root CSLA (SQRT CSLA) architecture ha

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26

Priya, Meshram, and Sarode Prof.Mamta. "Design of Modified Area Efficient Square Root Carry Select Adder (SQRT CSLA)." International Journal of Industrial Electronics and Electrical Engineering, no. 4 (June 17, 2015): 216–19. https://doi.org/10.5281/zenodo.33098.

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In the design of Integrated Circuits, The necessity of portable systems is increasing an area occupancy plays a vital role. Square Root Carry Select Adder (SQRT CSLA) is one of the fastest adders which is used in this data-processing processor to perform fast arithmetic functions. In this paper, an area-efficient square root carry select adder(SQRT CSLA design) by sharing Common Boolean logic term (CBL) is proposed The modified architecture has been developed using Binary to Excess-1 converter (BEC). Based on this modification 8-, 16-, 32-, and 64-b square-root CSLA (SQRT CSLA) architecture ha

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27

M, Syed Mustafaa, Sathish M, Nivedha S, Magribatul Noora A K, and Safrin Sifana T. "Design of Carry Select Adder using BEC and Common Boolean Logic." Indian Journal of VLSI Design 1, no. 3 (2022): 5–9. http://dx.doi.org/10.54105/ijvlsid.c1205.031322.

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Carry Select Adder (CSLA) is known to be the fastest adder among the conventional adder structure, which uses multiple narrow adders. CSLA has a great scope of reducing area, power consumption, speed and delay. From the structure of regular CSLA using RCA, it consumes large area and power. This proposed work uses a simple and dynamic Gate Level Implementation which reduces the area, delay, power and speed of the regular CSLA. Based on a modified CSLA using BEC the implementation of 8-b, 16-b, 32-b square root CSLA (SQRT CSLA) architecture have been developed. In order to reduce the area and po

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Syed, Mustafaa M., M. Sathish, S. Nivedha, Magribatul Noora A. K. Mohammed, and Sifana T. Safrin. "Design of Carry Select Adder using BEC and Common Boolean Logic." Indian Journal of VLSI Design (IJVLSID) 1, no. 3 (2022): 5–9. https://doi.org/10.54105/ijvlsid.C1205.031322.

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Carry Select Adder (CSLA) is known to be the fastest adder among the conventional adder structure, which uses multiple narrow adders. CSLA has a great scope of reducing area, power consumption, speed and delay. From the structure of regular CSLA using RCA, it consumes large area and power. This proposed work uses a simple and dynamic Gate Level Implementation which reduces the area, delay, power and speed of the regular CSLA. Based on a modified CSLA using BEC the implementation of 8-b, 16-b, 32-b square root CSLA (SQRT CSLA) architecture have been developed. In order to reduce the area and po

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29

B Gowda, Ranjith, and R. M Banakar. "Design of high speed low power optimized square root BK adder." International Journal of Engineering & Technology 7, no. 2.12 (2018): 240. http://dx.doi.org/10.14419/ijet.v7i2.12.11289.

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Adder is a basic building block in almost all the digital circuits used in todays digital world. Adders are used for address calculation, incrementing operation, table indices calculations and many other operations in digital processors. These operations require fast adders with reasonable design cost. Ripple carry adder (RCA) is the cheapest and most straight forward design but takes more computation time. For high speed applications Carry Look-ahead Adder (CLA) is preferred, but it has the limitation of increase in the total area of the design. Hence an adder which compromise between these t

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Singh, Gagandeep, and Chakshu Goel. "Design of Low Power and Efficient Carry Select Adder Using 3-T XOR Gate." Advances in Electronics 2014 (September 22, 2014): 1–6. http://dx.doi.org/10.1155/2014/564613.

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In digital systems, mostly adder lies in the critical path that affects the overall performance of the system. To perform fast addition operation at low cost, carry select adder (CSLA) is the most suitable among conventional adder structures. In this paper, a 3-T XOR gate is used to design an 8-bit CSLA as XOR gates are the essential blocks in designing higher bit adders. The proposed CSLA has reduced transistor count and has lesser power consumption as well as power-delay product (PDP) as compared to regular CSLA and modified CSLA.

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Anitha, M., J. Princy Joice, and Rexlin Sheeba.I. "A New-High Speed-Low Power-Carry Select Adder Using Modified GDI Technique." International Journal of Reconfigurable and Embedded Systems (IJRES) 4, no. 3 (2015): 173. http://dx.doi.org/10.11591/ijres.v4.i3.pp173-177.

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Adders are of fundamental importance in a wide variety of digital systems. This paper presents a novel bit block structure which computes propagate signals as carry strength. Power consumption is one of the most significant parameters of carry select adder.The proposed method aims on GDI(Gate Diffusion Input) Technique. Modified GDI is a novel technique for low power digital circuits design further to reduce the swing degradation problem. This techniques allows reduction in power consumption, carry propagation delay and transistor count of the carry select adder.This technique can be used to r

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32

Sharma, Neeta, and Ravi Sindal. "Modified Booth Multiplier using Wallace Structure and Efficient Carry Select Adder." International Journal of Computer Applications 68, no. 13 (2013): 39–42. http://dx.doi.org/10.5120/11643-7130.

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33

Aditya, Srinivas, and Ramesh K.B. "Design and Implementation of an Optimized ALU using a Square Root Carry Select Adder." Journal of Optoelectronics and Communication 6, no. 3 (2024): 18–26. https://doi.org/10.5281/zenodo.12720733.

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<em>Arithmetic logic units (ALUs) are strong combinational circuits in digital computers that carry out arithmetic and logical operations. The Parallel Adder embedded within the Arithmetic Logic Unit (ALU) holds significance, yet the time-consuming nature of carry propagation (CP) during addition demands consideration. To cater to the requirements of low-power and area-efficient applications, the paper suggests an ALU design that integrates a modified Square Root Carry Select Adder (SQRT CSLA). Additionally, for applications necessitating enhanced speed, an alternative ALU design is introduced

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34

Swetha, Tarigoppula, Sravan K. Vittapu, Ravichand Sankuru, Balla Hindupriya, Bairagoni Anand, and Gangadi Chandra Vardhan Reddy. "Implementation of Area Efficient Carry Select Adder using Binary to Excess1 Code." Journal of VLSI Design and Signal Processing 9, no. 3 (2023): 29–36. http://dx.doi.org/10.46610/jovdsp.2023.v09i03.004.

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Adders are widely used as essential parts in the design of digital integrated circuits. The Carry Select Adder (CSA) is unique among conventional adder topologies in that it operates quickly. There is a need for speedier arithmetic units as well as ones that use less power and take up less space as the mobile sector grows quickly. The Carry-Select method for adder design with carry propagation achieves a good trade-off between performance and cost. However, because it uses two ripple carry adders (RCA), the traditional CSA design still has a significant area overhead. A Binary to Excess-1 code

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Indiradevi, K., and R. Shanmugalakshmi. "VLSI Architecture Using a Modified SQRT Carry Select Adder in Image Compression." Research Journal of Applied Sciences, Engineering and Technology 11, no. 1 (2015): 14–18. http://dx.doi.org/10.19026/rjaset.11.1670.

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C M, Aiswarya, and Shanil Mohamed N. "Design of a Modified Carry Select Adder with Single Fault Tolerant Architecture." IJARCCE 6, no. 6 (2017): 474–79. http://dx.doi.org/10.17148/ijarcce.2017.6684.

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37

Meenaakshi Sundhari, R. P., and R. Anita. "Modified 16-b Square-root Low Power Area Efficient Carry Select Adder." Research Journal of Applied Sciences, Engineering and Technology 8, no. 21 (2014): 2220–26. http://dx.doi.org/10.19026/rjaset.8.1221.

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Singh, Kulvir, and Dilip Kumar. "Modified Booth Multiplier with Carry Select Adder using 3-stage Pipelining Technique." International Journal of Computer Applications 44, no. 14 (2012): 35–38. http://dx.doi.org/10.5120/6334-8710.

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Anitha, M., J. Princy joice, and Mrs Rexlin Sheeba.I. "A New-High Speed-Low Power-Carry Select adder Using Modified GDI Technique." International Journal of Engineering Research 4, no. 3 (2015): 127–29. http://dx.doi.org/10.17950/ijer/v4s3/309.

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John Alex, E., and M. Vijayaraj. "Energy Efficient BEC Modified Carry Select Adder Based PTMAC Architecture for Biomedical Processors." Intelligent Automation & Soft Computing 23, no. 2 (2016): 383–88. http://dx.doi.org/10.1080/10798587.2016.1231881.

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Bavithra, K. B., and R. Siva Kumar. "High throughput K best MIMO detector using modified final selector based carry select adder." Microprocessors and Microsystems 71 (November 2019): 102847. http://dx.doi.org/10.1016/j.micpro.2019.102847.

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Uthayakumar, C., and B. Justus Rabi. "Design and Implementation of High Speed and Low Power Modified Square Root Carry Select Adder (MSQRTCSLA)." Research Journal of Applied Sciences, Engineering and Technolog 12, no. 1 (2016): 43–51. http://dx.doi.org/10.19026/rjaset.12.2302.

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Goyal, Heena, and Shamim Akhter. "VHDL Implementation of Fast Multiplier based on Vedic Mathematic using Modified Square Root Carry Select Adder." International Journal of Computer Applications 127, no. 2 (2015): 24–27. http://dx.doi.org/10.5120/ijca2015906331.

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B.BHUPAL and S.K.SATYANARAYANA. "Design and Simulation of Low Power and Area Efficient SQRT Carry Select Adder with Modified Binary to Excess-1 Converter." International Journal of Scientific Engineering and Technology Research 3, no. 44 (2014): 8927–32. https://doi.org/10.5281/zenodo.33084.

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In the design of Integrated circuits, area occupancy and power consumption plays a vital role because of increasing necessity of portable systems. Carry Select Adder (CSLA) is a fast adder used in data processing processors for performing fast arithmetic functions. From the structure of the CSLA, it is clear that there is scope for reducing the area and power consumption in the CSLA. This work uses a simple and efficient transistor level modification of EX-OR gate used in BEC-1 converter to significantly reduce the area and power of the CSLA. Based on this modification 4, 8, 16-bit SQRT CSLA a

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Penchalaiah, U., and Siva Kumar VG. "Survey: Performance Analysis of FIR Filter Design Using Modified Truncation Multiplier with SQRT based Carry Select Adder." International Journal of Engineering & Technology 7, no. 2.32 (2018): 243. http://dx.doi.org/10.14419/ijet.v7i2.32.13519.

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A recent years of technology development in Signal processing application a FIR (Finite impulse response) filter design will have a highly compactable with high performance and low power in all digital signal processing application, such as audio processing, signal processing, software define radio and so on. Now a days in our environment will have more signal noises, and fluctuation due to technology development, here the Filter design is mainly configuring the priority to reduce the signal noises and fluctuation in all type of gadgets. In this project, the design contains Transpose form of h

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Murugeswari, S., and S. Kaja Mohideen. "Design of Optimized Low Power and Area Efficient Digital FIR Filter using Modified Group Structures based Square Root Carry Select Adder." Research Journal of Applied Sciences, Engineering and Technology 9, no. 2 (2015): 84–90. http://dx.doi.org/10.19026/rjaset.9.1381.

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Ramesh Babu Chukka, Sudhakar Jyothula, Vijaya Sree Ganta ,. "DESIGN OF HIGH THROUGHPUT ADD COMPARE AND SELECT UNIT FOR LOW POWER VITERBI DECODER." INFORMATION TECHNOLOGY IN INDUSTRY 9, no. 1 (2021): 954–60. http://dx.doi.org/10.17762/itii.v9i1.223.

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The main purpose of this paper is to focus on the design of Viterbi Decoder (VD) with low power, which is significant for receiver section of data communication applications such as Radar, Satellite, Telephone and Automatic speech recognition. The Viterbi decoder algorithm consists of three most important blocks – Branch Metric Unit (BMU), Add Compare and Select (ACS) Unit and Survivor Memory Unit (SMU). BMU computes the metrics between the input and output state transitions. ACS unit include the Path Metric Unit (PMU), which computes the metrics with the sequence to a next state of a path and

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"Design and Implementation of 256 Bit Modified Square Root Carry Select Adder for Area and Delay Reduction." International Journal of Engineering and Advanced Technology 9, no. 2 (2019): 407–10. http://dx.doi.org/10.35940/ijeat.b3271.129219.

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This paper models the behaviour of modified Square Root Carry Select Adder and goes deep to investigate on its scope of reducing area and delay. This helps to overcome the drawback of conventional RCA by performing operations simultaneously for both Cin = 0 and Cin = 1, and the output is multiplexed to obtain the desired response. The work explores opportunities to reduce the area with introduction of BEC logic instead of second block RCA. The implementation of a 4 bit MCSLA and its capability of extending its word size to 8, 16, 32, 64, 128 and 256 bits are presented. The experimental result

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MITRA, ARITRA. "Performance Improvement Of A Modified Carry Select Adder." International Journal of Electrical Electronics and Data Communication 3, no. 7 (2015). http://dx.doi.org/10.18479/ijeedc/2015/v3i7/48258.

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"High Throughput Efficient Modified SQRT Carry Select Adder." International Journal of Recent Technology and Engineering 8, no. 5 (2020): 5261–63. http://dx.doi.org/10.35940/ijrte.e3205.018520.

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In numerous processors math unit is fundamental structure square like DSPs and chip. Adders are key structure obstructs in ALUs. In this manner expanding adders speed, lessening their vitality utilization and zone firmly impact the speed, control utilization and region of processor. There are numerous takes a shot at the subject of advancing velocity, zone of these units. One of way to deal with improve both the territory and speed is to forfeit the calculation precision. This methodology is rough registering, might be utilized for the applications where a few blunders might be endured. In Rev

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