Academic literature on the topic 'MOS memory devices'

Amorphous carbon film with Diamond like properties is the subject of intense interest in the past one and half decade. The unusual properties of these diamond like carbon films arise from the preponderance of SP3 tetrahedral bonding of carbon in the film. Depending on the processing technique and the processing conditions used, the structure of the films can range from amorphous carbon to large grain polycrystalline diamond. These deposited amorphous carbon films, which are smooth, may find their use in optoelectronics, in dielectric films and in microelectronics. These films are found to be chemically inhomogeneous(containing SP3 hybridized carbon in a matrix of SP2 hybridized non-graphitic carbon). There is a possibility of using these films as substrates in microelectronics, provided the deposited films are structurally smooth, are chemically homogeneous and are dopable with both types of impurities. A host of other advantages of using diamond like carbon as a substrate material in microelectronics made it a topic of interest to many investigators. This prompted the author to take up investigations on diamond like carbon films from the point of examining the electrical properties of these films and on the possibility of conceiving devices based on these films. This investigation dealt with, sputter deposition of diamond like carbon films and their electrical characteristics in MCS device structures. In this, emphasis is given to the importance of processing parameters involved and the effect of each parameter on the electrical and structural properties of the film. Various substrate treatments were done prior to sputtering and found that the DLC nature of the film exists in all the films but differ from one another in electrical resistivity, in nucleation density and in their adherence to the substrate. Films deposited on substrates treated with low vapour pressure oil resulted in compressive strain in the film and lead to very poor adhesion. The nucleation density increased when the substrates are pretreated with ultrasonic agitation in hard SiC grit. The substrate temperature had a direct impact on the resistivity of the film: resistivity decreases with increase in substrate temperature. The constituents of the plasma modified the structural properties of the film, e.g. the Hydrogen content in the plasma has resulted in increasing the SP3 hybridization content of the film, by acting as SP2- SP2 network terminator. Ultra violet light focused onto the substrate, in general, enhanced the deposition rate. Inclusion of Nitrogen in the plasma substantially increased the conductivity of the material and this is used in doping of the DLC film. The carbon films deposited on silicon are used for electrical characterisation. Deposition of metal electrode on the carbon film lead to the basic (MCS) device structure. The I vs.V characteristics of the MCS structure resemble those of junction diodes. From the I vs.V characteristics at different temperatures, it has been found that the reverse current goes through a maximum, drops back to certain level and once again increases with gradual increase in temperature. This behaviour of the structure with A1 as well as Ag as top electrode materials is explained by the heterojunction formed at the C-pSi interface. The initial increase in the reverse current is dominated by the drift of minority carriers across the depletion width at the reverse biased junction. With increase in temperature, the depletion width reduces to a minimum above a certain temperature, where the diffusion of carriers controls the current across the device. From the constructed energy-band diagram of heterojunction, it is shown that the change in the transport phenomena from drift of minority carriers to diffusion of majority carriers at the junction, introduces a barrier at the critical temperature; This is responsible for the drop in current at the critical temperature. This explains the anomaly of drop in reverse current with increase in temperature. The C vs. v characteristics showed a bell shaped behaviour indicating the presence of two junctions connected back to back. This confirms the type of contact formed at the metal-carbon interface and the type of conductivity of the film, concluding that A1 makes a Schottky contact where as Ag makes an ohmic contact and the deposited film behaves like n-type material. The C vs. V behaviour with temperature is explained by the two types of contacts in the case of Al-GpSi, i.e. Schottky contact at Al-C; and heterojunction at C-pSi interface. These C vs. V and I vs.V changes with temperature are in tune with each other and the model proposed takes care of all the characteristics observed. In case of Ag-GpSi, C vs. V with temperature shows junction like behaviour at elevated temperatures and are explained by the presence of the interface at C-pSi. It has been observed that in some of the carbon films, when an electric field of the order of l06 V/cm is applied, the reflectance of the Aluminium metal dot is increased by 5 times, coupled with a 50 to 100 times increase in the associated capacitance of the MCS structure. The increase in reflectance is explained by considering the film to be inhomogeneous with a matrix of varying dielectric constants (SP3 hybridized carbon in a medium of SP2 bonded carbon). The transformed film, is homogeneous and enhances the reflectance of the Aluminium dot. This is termed as "homogeneity induced smoothness." The transformation of inhomogeneous material to homogeneous material is further confirmed by the Raman spectroscopy, in which the broad peak is converted to a sharp peak changing the FWHM from 93 cm-1 to 4 cm-1 ; denoting the structural order in the film. To the best of our knowledge, this is the first investigation reporting the crystalline nature of the DLC, with structural order and the corresponding FWHM of the Raman peak as low as 4 cm-1. The preparational conditions of the film to get this transformation and the influence of various process parameters are examined. Devices based on Metal-Carbon-Oxide- Silicon (MCOS) structure are realized by thermally grown oxide/sputter deposited oxide on silicon, prior to carbon deposition. These structures showed voltage controlled negative resistance(VCNR) characteristics. The applied voltage and its distribution across the reverse biased junction and across the oxide gives rise to a negative resistance region. With the number of V vs. I characteristics measured, it is observed that the negative resistance region also shifts. This is attributed to the trapped charges in the carbon changing the distribution of applied voltage. This is explained by modifying the energy-band diagram. A concept of the accumalated charges at the oxide barrier filling up the higher energy states in the carbon and silicon, to become hot carriers is used. As long a. more voltage is dropped across the oxide, these hot carriers can surmount the barrier at the reverse biased junction. The flow of these carriers is cut off when the additional voltage is dropped across the reverse biased junction leading to a drop in the current. A further increase in the applied voltage nominally increases the current due to increase in the leakage current. A new hybrid (electrical/optical) read only memory (ROM) element is conceived and the way in which the information can be written and read is discussed. A two terminal negative resistance device using MCOS structure is fabricated and tested for its VCNR property. An analog memory device is proposed using the MCOS structure as gate in an FET. The work reported in this thesis has been divided into nine chapters. The introductory remarks on the importance of the area of research and about the work reported in this thesis are given in chapter one. Chapter two deals with some of the basic concepts related to understand the reported work. In chapter three the research work done by other investigators covering different aspects of this work is reported and some of their investigations are reviewed. Chapter four dealt with the various preparative techniques to deposit films, their structural characterisation, and the experimental work carried out to electrically characterize these films. Chapter five presents the I vs.V & C vs. V analysis and a model to qualitatively explain them. In chapter six field induced transformation phenomena of some of these films and its impact on the reflectance of the metal dot is dealt. Chapter seven consists of the MCOS device structure, its I vs.V characteristics and a model to explain the behaviour. Chapter eight presents the application part of same of the phenomena observed in conceiving a new hybrid ROM element and a two terminal negative resistance device. The concluding ninth chapter itemizes the important results of the work and suggestions to carry forward this work which can open up new vistas in the diamond like carbon film based technology and its applications in microelectronics.

Ces dix dernières années, les technologies de stockage non-volatile Flash ont joué un rôle majeur dans le développement des appareils électroniques mobiles et multimedia (MP3, Smartphone, clés USB, ordinateurs ultraportables…). Afin d’améliorer davantage les performances, augmenter les capacités et diminuer les coûts de fabrication, de nouvelles solutions technologiques sont aujourd’hui étudiées pour pouvoir compléter ou remplacer la technologie Flash. Citées par l’ITRS, les mémoires résistives polymères présentent des caractéristiques très prometteuses : procédés de fabrication à faible coût et possibilité d’intégration haute densité au dessus des niveaux d’interconnexions CMOS ou sur substrat souple. Ce travail de thèse a été consacré au développement et à l'étude des mémoires résistifs organiques à base de polymère de poly-méthyl-méthacrylate (PMMA) et de molécules de fullerènes (C60). Trois axes de recherche ont été menés en parallèle: le développement et la caractérisation physico-chimique de matériaux composites, l’intégration du matériau organique dans des structures de test spécifiques et la caractérisation détaillée du fonctionnement électrique des dispositifs et des performances mémoires<br>Over the past decade, non-volatile Flash storage technologies have played a major role in the development of mobile electronics and multimedia (MP3, Smartphone, USB, ultraportable computers ...). To further enhance performances, increase the capacity and reduce manufacturing costs, new technological solutions are now studied to provide complementary solutions or replace Flash technology. Cited by ITRS, the polymer resistive memories present very promising characteristics: low cost processing and ability for integration at high densities above CMOS interconnections or on flexible substrate. This PhD specifically focused on the development and study of composite material made of Poly-Methyl-Methacrylate (PMMA) polymer resist doped with C60 fullerene molecules. Studies were carried out on three different axes in parallel: Composite materials development &amp; characterization, integration of the organic material in specific test structure and advanced devices and finally detailed electrical characterization of memory cells and performances analysis

Depuis 2005, la miniaturisation des composants mémoires, qui, auparavant, suivait la loi de Moore, a ralenti. Ceci a conduit les chercheurs à multiplier les approches pour continuer à améliorer les dispositifs mémoires. Parmi ces approches, la piste des composants ferroélectriques semble très prometteuse. En 2011, une équipe du NamLab, à Dresde, en Allemagne, a découvert que le HfO2 dopé Si pouvait devenir ferroélectrique, avec une couche isolante de seulement 10 nm, ce qui résout le problème de compatibilité avec l’industrie CMOS des matériaux de structure pérovskite. Depuis, d’autres dopants ont été découverts. Cependant, de nouveaux problèmes freinent désormais l’apparition sur le marché des dispositifs ferroélectriques à base de HfO2. Comprendre les mécanismes qui régissent les propriétés ferroélectriques de ces matériaux est alors devenu un enjeu industriel majeur. Dans ce manuscrit, nous étudions le (Hf,Zr)O2 (HZO), et nous employons une technique peu utilisée pour élaborer ce type de matériau : la pulvérisation cathodique magnétron. L’objectif de cette thèse est d’établir des relations entre les conditions de croissance des différents matériaux et les propriétés électriques, de comprendre les mécanismes qui les régissent, ainsi que de rendre viable les dispositifs mémoires. Lors de l’élaboration de condensateurs, nous démontrons que des propriétés cristallochimiques particulières sont indispensables pour obtenir la ferroélectricité, et de nouvelles propriétés du HZO sont découvertes. Ensuite, nous cherchons à dépasser l’état de l’art. Par pulvérisation, nous obtenons parmi les meilleurs résultats au monde. Les tests industriels d’endurance et de rétention sont poussés au-delà de ce qui avait été fait auparavant dans la littérature. En particulier, l’influence des conditions de contraintes électriques y est décrite en détail, et nous mettons en évidence la présence d’une relaxation au cours des différents tests pouvant s’avérer problématique pour l’avènement d’applications industriels. Ce problème ne semble jamais avoir été clairement identifié auparavant<br>Since 2005, the scaling of memory devices, which used to follow Moore's law, slowed down. This lead researchers to conduct multiple approaches in order to keep improving memory devices. Among these approaches, the pathway on ferroelectric components seems very promising. In 2011, a research team from the NamLab in Dresden, Germany, discovered that Si-doped HfO2 could become ferroelectric with an insulating layer of only 10 nm, which resolves the compatibility issue of perovskite-structured materials with CMOS industry. Since then, other dopants have been investigated. However, new issues are now slowing down the emergence of HfO2-based ferroelectric devices on the market. Understanding the mechanisms behind the ferroelectric properties of these materials has, therefore, become a major industrial issue. In this manuscript, we study (Hf,Zr)O2 (HZO), and we perform an under-utilized technique to elaborate this kind of material: magnetron sputtering. The goal of this thesis is to establish connections between the growth conditions of this material and the electrical properties, to understand the mechanisms behind them, as well as to make the memory devices viable. During the fabrication of the capacitors, we demonstrate that the particular cristallochemical properties are essential to obtain ferroelectricity, and that novel HZO properties are discovered. Afterwards, we seek to cross the state of the art. The results we obtain by sputtering are among the best in the world. The industrial endurance and retention tests are pushed beyond what has been done in the literature so far. Particularly, the influence of electrical stress conditions is thoroughly detailed, and we put to evidence the presence of a relaxation during the different tests that could turn out to become problematic for the emergence of industrial applications. It does not seem that this problem has been identified beforehand

博士<br>國立清華大學<br>工程與系統科學系<br>101<br>With the increasing demand on non-volatile memory and MOSFET devices, devices with high performance while maintaining good reliability properties are needed. Also, shrinkage in cell dimension for achieving higher storage and packing density is required. In order to improve the device performance, the utilization of SiGe buried channel is considered most promising for improving performance and lowering the operation voltage, according to the simulations, while stays on the track of device scaling down. Literature reviews on the growth of SiGe buried channel, high-concentration Ge channel and the growth techniques of interfacial layers on Ge substrate are provided. In this dissertation, SiGe buried channel, Si/Ge super-lattice channel and Ge channel have been employed for the application on charge-trapping type flash memory devices. Furthermore, Ge MOS and MOSFET devices with different formation processes of GeO2 interfacial layer are also investigated. With the employment of SiGe buried channel, both programming / erasing speeds of devices can be improved while maintaining the reliability characteristics as compared with Si-channel devices. Furthermore, the enhancement on device performance increases with the increasing Ge content within channel. Hence, in order to achieve high-Ge content channel structure, we proposed a novel Si/Ge super-lattice channel structure. From the material characterization of the as-deposited super-lattice, the super-lattice structure possesses extremely low surface-roughness and high crystal quality which are helpful for device fabrication. As a result, much better performances of devices with the employment of super-lattice channel are observed as compared to those with SiGe buried channel. At the meanwhile, the reliability properties for devices with employing super-lattice channel are kept which perform as well as Si-channel devices. For flash memory devices on Ge substrate, devices with different interfacial layers are investigated. The device performances are significantly improved by using Ge substrate as compared with Si-channel device and the retention characteristics can be kept simultaneously. However, the endurance property for Ge devices is slightly worse than that of Si-channel device. Based on the above experience on fabricating Ge flash memory devices, Ge MOS and MOSFET devices with different formation processes of GeO2 interfacial layer are also investigated in this work. The key challenge of having high performance Ge MOS and MOSFET devices is the formation of high quality stoichiometric GeO2 interfacial layer with ultra-thin thickness. In this work, a low EOT with an acceptable gate leakage current density Ge MOS device can be achieved by using H2O plasma grown GeO2 interfacial layer together with in-situ grown HfON gate dielectric. Furthermore, the oxidation states and thickness of the H2O plasma grown GeO2 interfacial layer are characterized by XPS spectroscopy and HR-TEM, respectively, where the oxidation state is +4 with thickness of around 0.3 nm. It is an important achievement in this work. At the meantime, Ge p-MOSFET devices with high hole mobility are obtained by using the high quality GeO2 interfacial layer grown by H2O plasma process. Furthermore, the effects of various detailed growth-conditions within the H2O plasma process on electrical characteristics of Ge MOS devices are also investigated. A high composition of stoichiometric GeO2 interfacial layer with ultra-thin thickness are achieved which result in ultra-low EOT and high reliability properties of the Ge MOS devices.

碩士<br>龍華科技大學<br>電子工程系碩士班<br>103<br>Gallium nitride compared with other materials has the advantage with wide bandgap, high breakdown electric field and high electron saturation velocity, etc. Gallium nitride is a good material for high power, high frequency and optics applications. Metal semiconductor junction high electron mobility transistor can't effectively suppress gate leakage current in high bias due to its limited barrier height properties. Therefore, we adopt metal oxide semiconductor structure high electron mobility transistors to reduce gate leakage and surface states density. In this thesis, we proposed in-situ silicon nitride as gate dielectric layer, and changed deposition conditions of silicon nitride to investigate the variety of deposition conditions of silicon nitride thin film for effect of device performance. Conventionally AlGaN/GaN HEMT device which operating mode is the depletion mode. Depletion mode of device for circuit design has high complexity and fail-safe problem in high power operation. For this reason, there are some methods to make device in enhancement mode. In this thesis, we proposed charge trapping method to confine electrons in the charge storage layer, to change space charge of device, so that threshold voltage toward positive voltage shift.

Ferroelectric non-volatile memories have gained momentous importance in the recent years. Significant research is being done on different device structures with several ferroelectric films for better data retention, lower power dissipation and higher density of integration. Metal - ferroelectric insulator – semiconductor (MIS) capacitor structures with Poly Vinylidene Fluoride(80%) - trifluoroethylene (20%) (PVDF – TrFE) copolymer are observed to demonstrate consistent dielectric properties and retainable memory action under selected operating conditions. Prior research was done on devices with MFeOS structure with an oxide buffer layer. The presence of a buffer oxide reduces the field acting on the film for memory state switching, which in effect requires the devices to be operated at higher voltages. In this work, MFeS devices with lower ferroelectric film thickness; with, and without a very thin buffer oxide have been studied. The dielectric behavior of PVDF thin film, when deposited directly on Si, is observed to exhibit reliable memory properties without significant charge injection under certain operating conditions. Electrical characteristics such as capacitance-voltage(C-V) and polarization-electric field (P-E) hysteresis with the direction of measurement and conduction properties through the junction have been comprehensively studied to establish the behavior of the MIS device for possible use in MIS FETs for high density ferroelectric memories.

碩士<br>國立中山大學<br>機械與機電工程學系研究所<br>97<br>Current requirements of nonvolatile memory (NVM) are the high density cells, low-power consumption, high-speed operation and good reliability for the scaling down devices. However, all of the charges stored in the floating gate will leak into the substrate if the tunnel oxide has a leakage path in the conventional NVMs. Therefore, the tunnel oxide thickness is difficult to scale down in terms of charge retention and endurance. The nanocrystal nonvolatile memories are one of promising substitution, because the discrete storage nodes as the charge storage media have been effectively improve data retention under endurance test for the scaling down device. Many methods have been developed recently for the formation of nanocrystals. Generally, most methods need thermal treatment with high temperature and long duration. This procedure will influence thermal budget and throughput in current manufacture technology of semiconductor industry. And supercritical carbon dioxide (SCCO2) has been researched to the passivation of dielectric and reducing the activation energy. The research estimates SCCO2 is potential to form nanocrystals for these reason. This research is to discuss the feasibility of fabricating nanocrystal NVMs device with low temperature SCCO2. The low melting point metal material Sn is used for the attempts. In order to check if Sn can be used for fabricating nanocrystal NVMs device, the research selects the conventional thermal annealing method first. It uses rapid thermal annealing to improve the crystalline of nanocrystals and reliability of the memory device. Compare to different Sn containment or chemistry and different process, analyze the electric characteristics and materials chemistry. At last, select the Sn and SiO2 co-sputtering film to try the SCCO2 process and analyze these characteristics as well. Due to the novel technology, many physical mechanism and improvement of properties will be discuss following.