Relevant bibliographies by topics / Prototype verification system (PVS)

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  1. Journal articles
  2. Dissertations / Theses
  3. Book chapters
  4. Conference papers

Academic literature on the topic 'Prototype verification system (PVS)'

Author: Grafiati
Published: 4 June 2021
Last updated: 2 February 2022

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Journal articles on the topic "Prototype verification system (PVS)"

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Yuan, Ling, and Ping Fan. "Verification of Dependable Architecture Based on Prototype Verification System." Advanced Materials Research 756-759 (September 2013): 4188–92. http://dx.doi.org/10.4028/www.scientific.net/amr.756-759.4188.

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The electronic power system can be viewed as a system composed of a set of concurrently interacting subsystems to generate, transmit, and distribute electric power. The complex interaction among sub-systems makes the design of electronic power system complicated. Furthermore, in order to guarantee the safe generation and distribution of electronic power, the fault tolerant mechanisms are incorporated in the system design to satisfy high reliability requirements. As a result, the incorporation makes the design of such system more complicated. We propose a dependable electronic power system architecture, which can provide a generic framework to guide the development of electronic power system to ease the development complexity. In order to provide common idioms and patterns to the system designers, we formally model the electronic power system architecture by using the PVS formal language. Based on the PVS model of this system architecture, we formally verify the fault tolerant properties of the system architecture by using the PVS theorem prover, which can guarantee that the system architecture can satisfy high reliability requirements.
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YANG, XIAOXIAO, ZHENHUA DUAN, and QIAN MA. "Axiomatic semantics of projection temporal logic programs." Mathematical Structures in Computer Science 20, no. 5 (2010): 865–914. http://dx.doi.org/10.1017/s0960129510000241.

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In this paper, we investigate the axiomatic semantics of the projection temporal logic programming language MSVL. To this end, we employ Propositional Projection Temporal Logic (PPTL) as an assertion language to specify the desired properties. We give a set of state axioms and state inference rules. In order to deduce a program over an interval, we also formalise a set of rules in terms of a Hoare logic-like triple. These rules enable us to deduce a program into its normal form and from the current state to the next one. They also enable us to verify properties over intervals. In this way, an axiom system for proving the correctness of MSVL programs is established. The axiom system is proved to be sound and relatively complete with respect to an operational model of MSVL, and give an example showing how the axiom system works. Finally, we employ a recently developed prototype verifier based on PVS as an example of semi-automatic verification using MSVL.
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Bihl, Trevor J., Todd J. Paciencia, Kenneth W. Bauer, and Michael A. Temple. "Cyber-Physical Security with RF Fingerprint Classification through Distance Measure Extensions of Generalized Relevance Learning Vector Quantization." Security and Communication Networks 2020 (February 24, 2020): 1–12. http://dx.doi.org/10.1155/2020/3909763.

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Radio frequency (RF) fingerprinting extracts fingerprint features from RF signals to protect against masquerade attacks by enabling reliable authentication of communication devices at the “serial number” level. Facilitating the reliable authentication of communication devices are machine learning (ML) algorithms which find meaningful statistical differences between measured data. The Generalized Relevance Learning Vector Quantization-Improved (GRLVQI) classifier is one ML algorithm which has shown efficacy for RF fingerprinting device discrimination. GRLVQI extends the Learning Vector Quantization (LVQ) family of “winner take all” classifiers that develop prototype vectors (PVs) which represent data. In LVQ algorithms, distances are computed between exemplars and PVs, and PVs are iteratively moved to accurately represent the data. GRLVQI extends LVQ with a sigmoidal cost function, relevance learning, and PV update logic improvements. However, both LVQ and GRLVQI are limited due to a reliance on squared Euclidean distance measures and a seemingly complex algorithm structure if changes are made to the underlying distance measure. Herein, the authors (1) develop GRLVQI-D (distance), an extension of GRLVQI to consider alternative distance measures and (2) present the Cosine GRLVQI classifier using this framework. To evaluate this framework, the authors consider experimentally collected Z-wave RF signals and develop RF fingerprints to identify devices. Z-wave devices are low-cost, low-power communication technologies seen increasingly in critical infrastructure. Both classification and verification, claimed identity, and performance comparisons are made with the new Cosine GRLVQI algorithm. The results show more robust performance when using the Cosine GRLVQI algorithm when compared with four algorithms in the literature. Additionally, the methodology used to create Cosine GRLVQI is generalizable to alternative measures.
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Kiełbik, Rafał, Kamil Rudnicki, Zbigniew Mudza, and Jarosław Jung. "Methodology of Firmware Development for ARUZ—An FPGA-Based HPC System." Electronics 9, no. 9 (2020): 1482. http://dx.doi.org/10.3390/electronics9091482.

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ARUZ is a large scale, massively parallel, FPGA-based reconfigurable computational system dedicated primarily to molecular analysis. This paper presents a methodology for ARUZ firmware development that simplifies the process, offers low-level optimization, and facilitates verification. According to this methodology, firstly an expanded, generic, all-in-one VHDL description of variable Processing Elements (PEs) is developed manually. GCC preprocessing is then used to extract only the desired target functionality. A dedicated software instantiates and connects PEs in form of a scalable network, divides it into subsets for chips and generates its HDL description. As a result, individual HDL-coded specification, optimized for certain analysis, is provided for the synthesis tool. Code reuse and automated generation of up to 81% of the code economizes the workload. Using well-optimized VHDL for core description rather than High Level Synthesis eliminates unnecessary overhead. The PE network can be scaled inversely proportional to PEs complexity, in order to efficiently utilize available resources. Moreover, downscaling the problem makes verification during HDL simulations and testing the prototype systems easier.
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Zhora, Victor, and Oleksandr Synetskyi. "Use of the PVS formal logic system in the method of formal proof of security in the construction of information security systems." Technology audit and production reserves 2, no. 2(58) (2021): 41–45. http://dx.doi.org/10.15587/2706-5448.2021.229539.

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The object of research is the information and telecommunication system (ITS) and ensuring the protection of information stored, processed and circulating in it. One of the most problematic areas in the creation of secure ITS is the logical inconsistency and incompleteness of the information security policy. That is, a set of laws, rules, restrictions, recommendations, etc., which regulate the procedure for processing information and are aimed at protecting information from a certain set of threats. The reason for such problems is usually the absence of pre-design modeling of the information security system as a component of the information and telecommunications system, which in the end causes the latter to be vulnerable. An important prerequisite for the creation of a secure ITS is the construction of a subject-object model of the system, which makes it possible to determine the connections between objects, their features, to model information flows and types of access to information and infrastructure resources. According to the existing clear, complete and consistent subject-object model of the ITS, it becomes possible to apply mathematical methods to modeling the processes of its functioning, including for solving the problem of formal proof of security. The paper considers the main idea of the method of formal proof of security, which can be used when building information security systems or assessing the security of the created information and telecommunications system. It is shown that for its implementation it is possible to use the methodology of automatic theorem proving. One of the ways to solve this problem, which is proposed in the work, is the use of the PVS (Prototype Verification System) formal logic system, which is widely used for writing specifications and constructing proofs. The main components of this system are considered, as well as the possibilities of its use for automatic proof of statements about the impossibility of unauthorized access under the conditions of a certain security policy. An example of the use of the PVS system for the formal proof of the security of the system in the framework of the Bella-LaPadula security policy is given.
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Gao, Ning, Huaiyu Fan, and Weimin Wu. "A Simplified Finite Control Set Model Predictive Control for T-Type Three-Level Power Conversion System Based on LCL Filter." Journal of Control Science and Engineering 2021 (May 31, 2021): 1–16. http://dx.doi.org/10.1155/2021/9919338.

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Finite control set model predictive control (FCSMPC) is a highly attractive and potential control method for grid-tied converters. However, there are several challenges when employing FCSMPC in an LCL filter-based T-type three-level power conversion system (PCS) for battery energy storage applications. These challenges mainly include the increasing complexity of control algorithm and excessive cost of additional sensors, which deteriorate the performance of PCS and limit the application of FCSMPC. In order to overcome these issues, this paper proposes a simplified FCSMPC algorithm to reduce the computation complexity. Furthermore, full-dimensional state observers are adopted and implemented to estimate the instantaneous values of grid-side current and capacitor voltage for purpose of removing unnecessary electrical sensors. The implementation of proposed FCSMPC algorithm is described step by step in detail. Simulation results are provided as a verification for the correctness of theoretical analysis. Finally, a three-phase T-type three-level PCS prototype rated at 2.30 kVA/110 V is built up. Experimental results extracted from the prototype can verify the effectiveness of the proposed control strategy.
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ZHANG, HUAN, and DEWEN HU. "A SCANNER BASED PALMPRINT VERIFICATION SYSTEM FOR CIVIL APPLICATION." International Journal of Information Acquisition 07, no. 03 (2010): 259–68. http://dx.doi.org/10.1142/s021987891000218x.

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The concept of capturing a palmprint using a scanner is not new, but the current palmprint capture devices based on a scanner have the limitations of low speed and large weight. A new palmprint capture device based on a scanner has been developed, which can overcome these limitations. A scanner based palmprint verification system (PVS) has also been designed using the proposed palmprint capture device. A commercially available mobile internet device (MID) was used to execute the whole program and to store the collected palmprint images. A small palmprint database was built using the developed palmprint capture device and the experimental results on this palmprint database showed that the designed system achieved an acceptable level of performance. The proposed PVS has a stable performance, small size and low price, and can meet the practical needs of civil palmprint applications.
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Chkliaev, D. A., and V. A. Nepomniaschy. "Deductive Verification of the Sliding Window Protocol." Modeling and Analysis of Information Systems 19, no. 6 (2015): 57–68. http://dx.doi.org/10.18255/1818-1015-2012-6-57-68.

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We consider the well-known Sliding Window Protocol which provides reliable and efficient transmission of data over unreliable channels. A formal proof of correctness for this protocol faces substantial difficulties caused by a high degree of parallelism which creates a significant potential for errors. Here we consider a version of the protocol that is based on selective repeat of frames. The specification of the protocol by a state machine and its safety property are represented in the language of the verification system PVS. Using the PVS system, we give an interactive proof of this property of the Sliding Window Protocol.
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Pedro, Luis, Levi Lucio, and Didier Buchs. "System Prototype and Verification Using Metamodel-Based Transformations." IEEE Distributed Systems Online 8, no. 4 (2007): 1. http://dx.doi.org/10.1109/mdso.2007.22.

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Frieder, O. "A parallel database-driven protocol verification system prototype." Software: Practice and Experience 22, no. 3 (1992): 245–64. http://dx.doi.org/10.1002/spe.4380220304.

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Dissertations / Theses on the topic "Prototype verification system (PVS)"

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Gilbert, Frédéric. "Extending higher-order logic with predicate subtyping : application to PVS." Thesis, Sorbonne Paris Cité, 2018. http://www.theses.fr/2018USPCC009/document.

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Le système de types de la logique d'ordre supérieur permet d'exclure certaines expressions indésirables telles que l'application d'un prédicat à lui-même. Cependant, il ne suffit pas pour vérifier des critères plus complexes comme l'absence de divisions par zéro. Cette thèse est consacrée à l’étude d’une extension de la logique d’ordre supérieur appelée sous-typage par prédicats (predicate subtyping), dont l'objet est de rendre l'attribution de types aussi expressive que l'attribution de prédicats. A partir d'un type A et d'un prédicat P(x) de domaine A, le sous-typage par prédicats permet de construire un sous-type de A, noté {x : A | P(x)}, dont les éléments sont les termes t de type A tels que P(t) est démontrable. Le sous-typage par prédicats est au coeur du système PVS.Ce travail présente la formalisation d'un système minimal incluant le sous-typage par prédicats, appelé PVS-Core, ainsi qu'un système de certificats vérifiables pour PVS-Core. Ce deuxième système, appelé PVS-Cert, repose sur l'introduction de termes de preuves et de coercions explicites. PVS-Core et PVS-Cert sont munis d'une notion de conversion correspondant respectivement à l'égalité modulo beta et à l'égalité modulo beta et effacement des coercions, choisi pour établir une correspondance simple entre les deux systèmes.La construction de PVS-Cert est semblable à celle des PTS (Pure Type Systems) avec paires dépendantes et PVS-Cert peut être muni de la notion de beta-sigma-réduction utilisée au coeur de ces systèmes. L'un des principaux théorèmes démontré dans ce travail est la normalisation forte de la réduction sous-jacente à la conversion et de la beta-sigma-réduction. Ce théorème permet d'une part de construire un algorithme de vérification du typage (et des preuves) pour PVS-Cert et d'autre part de démontrer un résultat d'élimination des coupures, utilisé à son tour pour prouver plusieurs propriétés importantes des deux systèmes étudiés. Par ailleurs, il est également démontré que PVS-Cert est une extension conservative du PTS lambda-HOL, et qu'en conséquence PVS-Core est une extension conservative de la logique d'ordre supérieur.Une deuxième partie présente le prototype d'une instrumentation de PVS pour produire des certificats de preuve. Une troisième et dernière partie est consacrée à l'étude de liens entre logique classique et constructive avec la définition d'une traduction par double négation minimale ainsi que la présentation d'un algorithme de constructivisation automatique des preuves<br>The type system of higher-order logic allows to exclude some unexpected expressions such as the application of a predicate to itself. However, it is not sufficient to verify more complex criteria such as the absence of divisions by zero. This thesis is dedicated to the study of an extension of higher-order logic, named predicate subtyping, whose purpose is to make the assignment of types as expressive as the assignment of predicates. Starting from a type A and a predicate P(x) of domain A, predicate subtyping allows to build a subtype of A, denoted {x : A | P(x)}, whose elements are the terms t of type A such that P(t) is provable. Predicate subtyping is at the heart of the proof system PVS.This work presents the formalization of a minimal system expressing predicate subtyping, named PVS-Core, as well as a system of verifiable certificates for PVS-Core. This second system, named PVS-Cert, is based on the introduction of proof terms and explicit coercions. PVS-Core and PVS-Cert are equipped with a notion of conversion corresponding respectively to equality modulo beta and to equality modulo beta and the erasure of coercions, chosen to establish a simple correspondence between the two systems.The construction of PVS-Cert is similar to that of PTSs (Pure Type Systems) with dependent pairs and PVS-Cert can be equipped with the notion of beta-sigma-reduction used at the core of these systems. One of the main theorems proved in this work is the strong normalization of both the reduction underlying the conversion and beta-sigma-reduction. This theorem allows, on the one hand, to build a type-checking (and proof-checking) algorithm for PVS-Cert and, on the other hand, to prove a cut elimination result, used in turn to prove important properties of the two studied systems. Furthermore, it is also proved that PVS-Cert is a conservative extension of the PTS lambda-HOL and that, as a consequence, PVS-Core is a conservative extension of higher-order logic.A second part presents the prototype of an instrumentation of PVS to generate proof certificates. A third and final part is dedicated to the study of links between classical and constructive logic, with the definition of a minimal double-negation translation as well as the presentation of an automated proof constructivization algorithm
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Kong, Cindy. "Formal Methods Applied to the Specification of an Active Network Node." University of Cincinnati / OhioLINK, 2001. http://rave.ohiolink.edu/etdc/view?acc_num=ucin982104729.

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Li, Qiong. "Developing Modeling and Simulation Methodology for Virtual Prototype Power Supply System." Diss., Virginia Tech, 1999. http://hdl.handle.net/10919/27462.

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This dissertation develops a modeling and simulation methodology for design, verification, and testing (DVT) power supply system using a virtual prototype. The virtual prototype is implemented before the hardware prototyping to detect most of the design errors and circuit deficiencies that occur in the later stage of a standard hardware design verification and testing procedure. The design iterations and product cost are reduced significantly by using this approach. The proposed modeling and simulation methodology consists of four major parts: system partitioning, multi-level modeling of device/function block, hierarchical test sequence, and multi-level simulation. By applying the proposed methodology, the designer can use the virtual prototype effectively by keeping a short simulation CPU time as well as catching most of the design problems. The proposed virtual prototype DVT procedure is demonstrated by simulating a 5 V power supply system with a main power supply, a bias power supply, and other protection, monitoring circuitry. The total CPU time is about 8 hours for 780 tests that include the basic function test, steady stage analysis, small-signal stability analysis, large-signal transient analysis, subsystem interaction test, and system interaction test. By comparing the simulation results with the measurements, it shows that the virtual prototype can represent the important behavior of the power supply system accurately. Since the proposed virtual prototype DVT procedure verifies the circuit design with different types of the tests over different line and load conditions, many circuit problems that are not obvious in the original circuit design can be detected by the simulation. The developed virtual prototype DVT procedure is not only capable of detecting most of the design errors, but also plays an important role in design modifications. This dissertation also demonstrates how to analyze the anomalies of the forward converter with active-clamp reset circuit extensively and facilitate the design and improve the circuit performances by utilizing the virtual prototype. With the help of the virtual prototype, it is the first time that the designer is able to analyze the dynamic behavior of the active-clamp forward converter during large-signal transient and optimize the design correspondingly.<br>Ph. D.
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Huang, Cheng-Hao, and 黃政豪. "Study on Adaptive Assessment Mechanism and Its Prototype System Verification." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/54155091287935545527.

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碩士<br>國立臺南大學<br>資訊工程學系碩士班<br>102<br>Due to the rapid development of artificial intelligence techniques, machine learning theory has become a popular research topic, and widely applied to data mining, feature recognition, fuzzy logic system, and so on. This thesis applies an adaptive assessment mechanism to the computer Go program, the developed adaptive assessment prototype’s verification, and the Program of Learning Diagnosis and Progress Assessment for Primary and Secondary Students of Kaohsiung technology-based testing (POLDPA-tbt) system load. For computer Go application, we use fuzzy C-Means clustering algorithm and fuzzy markup language (FML) to assess the rank of the invited Go players. Meanwhile, we also feedback the estimated rank to the Go players to increase the fun of playing with computer Go program. For the adaptive assessment prototype’s verification, this thesis uses an item response theory (IRT) to select an item whose difficulty fits with this examinee’s ability for his/her next time according to his/her current response. For the POLDPA-tbt system load, this thesis first uses FML to establish the knowledge base and rule base of POLDPA-tbt’s system load. Then, we use some strict test plans and test scripts to do many load tests and verification & validation (V&V) for this system. Next, we infer the number of students who are able to successfully finish the adaptive testing according to the collected data and the established knowledge base and rule base. Finally, we adopt a genetic algorithm to optimize the defuzzied results. The experimental results show that the after-learning knowledge base and rule base outperform the before-learning ones. In the future, we will try to introduce type-2 fuzzy set (T2 FS) to much accurately infer the system’s load.
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Chang, Ya-Chun, and 張雅鈞. "Applying BIM on Prototype of Drawing Verification in Firefighting License System." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/34627568992378362249.

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碩士<br>中華大學<br>營建管理學系碩士班<br>103<br>In general, most of the function and using of building is for single purpose. However, current buildings combine several functions that causes a lot of problems not only on firefighting but also on environment engineering. Because of hard integration on different fields that causes a lot of conflicts. That wastes cost and time. That also threaten the safety of firefighting. This search focus on the drawing verification and field inspection on firefighting. These two items all stay on paper work. To complete the current work need to bring a lot of drawing papers in the field. By BIM, integrated data can be extracted. It makes the drawing verification and field inspection easier and increases the efficiency. That is the main point of this research. The building function and style is getting more complicated today. The building is used for multiple functions now. A lot of construction problem come from the clash of interfaces. Because of the official verification term is too long, the cost and completion term of construction is out of control. Through the building information modeling, the 3D model could be completed before the construction and exclude the problem by clash detect. This thesis will build a prototype by applying the BIM on the firefighting verification. This research defines the conditions of verification process. In the future after the completion this system, the verification system will compare the condition of the firefighting design with the code automatically. That will reduce the labor cost. More on that, the applier won’t have to bring heavy drawings but a notebook and complete the verification work.
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Book chapters on the topic "Prototype verification system (PVS)"

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Owre, S., J. M. Rushby, and N. Shankar. "PVS: A prototype verification system." In Automated Deduction—CADE-11. Springer Berlin Heidelberg, 1992. http://dx.doi.org/10.1007/3-540-55602-8_217.

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Buth, Bettina. "PAMELA+PVS Verification of Sequential Programs." In Tool Support for System Specification, Development and Verification. Springer Vienna, 1999. http://dx.doi.org/10.1007/978-3-7091-6355-9_5.

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Pnueli, Amir, and Tamarah Arons. "tlpvs: A pvs-Based ltl Verification System." In Lecture Notes in Computer Science. Springer Berlin Heidelberg, 2003. http://dx.doi.org/10.1007/978-3-540-39910-0_26.

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Vitt, Jan, and Jozef Hooman. "Assertional specification and verification using PVS of the steam boiler control system." In Formal Methods for Industrial Applications. Springer Berlin Heidelberg, 1996. http://dx.doi.org/10.1007/bfb0027249.

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Gebreyohannes, Solomon, Ali Karimoddini, Abdollah Homaifar, and Albert Esterline. "Formal Verification of a Fuzzy Rule-Based Classifier Using the Prototype Verification System." In Communications in Computer and Information Science. Springer International Publishing, 2018. http://dx.doi.org/10.1007/978-3-319-95312-0_1.

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Toman, John, Ren Siqi, Kohei Suenaga, Atsushi Igarashi, and Naoki Kobayashi. "ConSORT: Context- and Flow-Sensitive Ownership Refinement Types for Imperative Programs." In Programming Languages and Systems. Springer International Publishing, 2020. http://dx.doi.org/10.1007/978-3-030-44914-8_25.

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AbstractWe present ConSORT, a type system for safety verification in the presence of mutability and aliasing. Mutability requires strong updates to model changing invariants during program execution, but aliasing between pointers makes it difficult to determine which invariants must be updated in response to mutation. Our type system addresses this difficulty with a novel combination of refinement types and fractional ownership types. Fractional ownership types provide flow-sensitive and precise aliasing information for reference variables. ConSORT interprets this ownership information to soundly handle strong updates of potentially aliased references. We have proved ConSORT sound and implemented a prototype, fully automated inference tool. We evaluated our tool and found it verifies non-trivial programs including data structure implementations.
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Weissnegger, Ralph, Martin Schachner, Markus Pistauer, Christian Kreiner, Kay Römer, and Christian Steger. "Generation and Verification of a Safety-Aware Virtual Prototype in the Automotive Domain." In Advances in Systems Analysis, Software Engineering, and High Performance Computing. IGI Global, 2018. http://dx.doi.org/10.4018/978-1-5225-2845-6.ch008.

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The electrification of today's vehicles and the high number of new assistance features imply more and more complex systems. New challenges are arising through heterogeneous and distributed systems which interact with each other and have an impact on the physical world, so-called cyber-physical systems. The sensing and controlling of these systems is the work of the highly distributed electronic control units and it is no surprise that more than 100 of these microcontrollers are currently integrated in a modern (electric) car. Technological, organizational and design gaps in today's development flows are not covered by current methods and tools. Therefore, new approaches are essential to support the development process and to reduce costs and time-to-market, especially when systems are safety-critical and demand reliability. Through applying reliability analysis and simulation-based verification methods on the proposed model-based design flow, we are able to reduce the number of tools involved and achieve correctness, completeness and consistency of the entire system.
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Mosbahi, Olfa, and Mohamed Khalgui. "Formal Methods for Verifications of Reactive Systems." In Reconfigurable Embedded Control Systems. IGI Global, 2011. http://dx.doi.org/10.4018/978-1-60960-086-0.ch014.

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This chapter deals with the use of two verification approaches: theorem proving and model checking. The authors focus on the Event-B method by using its associated theorem proving tool (Click_n_Prove), and on the language TLA+ by using its model checker TLC. By considering the limitation of the Event-B method to invariance properties, the authors propose to apply the language TLA+ to verify liveness properties on a software behavior. The authors extend first the expressivity and the semantics of a B model (called temporal B model) to deal with the specification of fairness and eventuality properties. Second, they give transformation rules from a temporal B model into a TLA+ module. The authors present in particular, their prototype system called B2TLA+, that they have developed to support this transformation; then they can verify these properties thanks to the model checker TLC on finite state systems. For the verification of infinite-state systems, they propose the use of the predicate diagrams. The authors illustrate their approach on a case study of a parcel sorting system.
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"Transaction Level Model Automation for Multicore Systems." In Behavioral Modeling for Embedded Systems and Technologies. IGI Global, 2010. http://dx.doi.org/10.4018/978-1-60566-750-8.ch011.

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Model based verification has been the bedrock of electronic design automation. Over the past several years, system modeling has evolved to keep up with improvements in process technology fueled by Moore’s law. Modeling has evolved to keep up with the complexity of applications resulting in various levels of abstractions. The design automation industry has evolved from transistor level modeling to gate level and eventually to register transfer level (RTL). These models have been used for simulation based verification, formal verification and semiformal verification. With the advent of multicore systems, RTL modeling and verification are no longer feasible. Furthermore, the software content in most modern designs is growing rapidly. The increasing software content, along with the size, complexity and heterogeneity of multicore systems, makes RTL simulation extremely slow for any reasonably sized system. This has made system verification the most serious obstacle to time to market. The root of the problem is the signal-based communication modeling in RTL. In any large design there are hundreds of signals that change their values frequently during the execution of the RTL model. Every signal toggle causes the simulator to stop and reevaluate the state of the system. Therefore, RTL simulation becomes painfully slow. To overcome this problem, designers are increasingly resorting to modeling such complex systems at higher levels of abstraction than RTL. Transaction level models (TLMs) have emerged as the next level of abstraction for system design. However, well defined TLM semantics are needed for design automation at the transaction level. In this chapter, we present transaction level model automation for multicore systems based on well defined TLM semantics. TLMs replace the traditional signal toggling model of system communication with function calls, thereby increasing simulation speed. TLMs are already being used for executable specification of multicore designs, for analysis, fast simulation, and debugging. They play an important role in early application development and debugging before the final prototype has been implemented. We discuss essential issues in TLM automation and also provide an understanding of the basic building blocks of TLMs.
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Lo, W. Amber, and Joobin Choobineh. "Knowledge-Based Systems as Database Design Tools." In Intelligent Support Systems. IGI Global, 2002. http://dx.doi.org/10.4018/978-1-931777-00-1.ch004.

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Database design process is a knowledge intensive task that requires expertise, practical experience, and judgment. It is not surprising, therefore, that over the last few years many research prototype database design expert systems have been reported in the literature. This paper is a survey of such tools. These tools are compared with respect to four major aspects: database design support, tool flexibility, expert system features, and implementation characteristics. This study reveals that, in general, there is lack of 1) support for all the phases of the design, 2) support for group database design, 3) graphic support, 4) empirical verification of effectiveness of the tools, 5) long-term maintenance of the tool and database schemata, and 6) specialized knowledge representation schemes, inference, and learning techniques.
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Conference papers on the topic "Prototype verification system (PVS)"

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Nawaz, M. Saqib, M. IkramUllah Lali, and M. A. Pasha. "Formal verification of crossover operator in Genetic Algorithms using Prototype Verification System (PVS)." In 2013 International Conference on Emerging Technologies (ICET). IEEE, 2013. http://dx.doi.org/10.1109/icet.2013.6743532.

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Niu, Jingang, and Shenghui Su. "Design Verification of BJUT Library Management System with PVS." In 2010 International Conference on Computational Intelligence and Security (CIS). IEEE, 2010. http://dx.doi.org/10.1109/cis.2010.142.

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Yuan, Ling, and Ping Fan. "Verification of Dependable Architecture based on Prototype Verification System." In 2nd International Conference on Computer and Information Applications (ICCIA 2012). Atlantis Press, 2012. http://dx.doi.org/10.2991/iccia.2012.223.

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Vrcek, Gorazd, and Peter Peer. "Iris-Based Human Verification System: A Research Prototype." In 2009 16th International Conference on Systems, Signals and Image Processing. IEEE, 2009. http://dx.doi.org/10.1109/iwssip.2009.5367801.

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Rodrigues, Brinzel, Anita Chaudhari, Pratap Sakhare, and Dimpy Modi. "Prototype for signature verification system using euclidean distance." In 2015 International Conference on Green Computing and Internet of Things (ICGCIoT). IEEE, 2015. http://dx.doi.org/10.1109/icgciot.2015.7380727.

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Malone, Robert M., Jeremy J. Bundgaard, Jesus J. Castaneda, Morris I. Kaufman, and Kevin D. McGillivray. "Adapting a prototype zoom lens to work outside its zoom range." In Optical System Alignment, Tolerancing, and Verification XIII, edited by José Sasián and Richard N. Youngworth. SPIE, 2020. http://dx.doi.org/10.1117/12.2570296.

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Adams, Colin, Ruben Alfaro, Giovanni Ambrosi, et al. "Verification of the optical system of the 9.7-m prototype Schwarzschild-Couder Telescope." In Optical System Alignment, Tolerancing, and Verification XIII, edited by José Sasián and Richard N. Youngworth. SPIE, 2020. http://dx.doi.org/10.1117/12.2568134.

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Guozhang Wang, Qiaolin Shi, Zhiguo Yu, and Zongguang Yu. "The study of HW/SW co-verification on ARM-prototype system." In 2008 9th International Conference on Solid-State and Integrated-Circuit Technology (ICSICT). IEEE, 2008. http://dx.doi.org/10.1109/icsict.2008.4734917.

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Zhang, Xiangkun, Wenshuai Zhai, and Yunhua Zhang. "A prototype for stepped-frequency SAR dechirp imaging system and experimental verification." In 2009 Asia Pacific Microwave Conference - (APMC 2009). IEEE, 2009. http://dx.doi.org/10.1109/apmc.2009.5384425.

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Hall, Peter J., Pieter Benthem, and Adrian T. Sutinjo. "Aperture array verification system 1: Overview of a square kilometre array prototype." In 2016 International Conference on Electromagnetics in Advanced Applications (ICEAA). IEEE, 2016. http://dx.doi.org/10.1109/iceaa.2016.7731394.

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