Journal articles: 'Reconfigurable Multi-Core architecture'

1

Yan, Like, Binbin Wu, Yuan Wen, Shaobin Zhang, and Tianzhou Chen. "A reconfigurable processor architecture combining multi-core and reconfigurable processing units." Telecommunication Systems 55, no. 3 (August 10, 2013): 333–44. http://dx.doi.org/10.1007/s11235-013-9791-1.

Full text

APA, Harvard, Vancouver, ISO, and other styles

2

Saeed, Ahmed, Ali Ahmadinia, and Mike Just. "Secure On-Chip Communication Architecture for Reconfigurable Multi-Core Systems." Journal of Circuits, Systems and Computers 25, no. 08 (May 17, 2016): 1650089. http://dx.doi.org/10.1142/s0218126616500894.

Full text

Abstract:

Security is becoming the primary concern in today’s embedded systems. Network-on-chip (NoC)-based communication architectures have emerged as an alternative to shared bus mechanism in multi-core system-on-chip (SoC) devices and the increasing number and functionality of processing cores have made such systems vulnerable to security attacks. In this paper, a secure communication architecture has been presented by designing an identity and address verification (IAV) security module, which is embedded in each router at the communication level. IAV module verifies the identity and address range to be accessed by incoming and outgoing data packets in an NoC-based multi-core shared memory architecture. Our IAV module is implemented on an FPGA device for functional verification and evaluated in terms of its area and power consumption overhead. For FPGA-based systems, the IAV module can be reconfigured at run-time through partial reconfiguration. In addition, a cycle-accurate simulation is carried out to analyze the performance and total network energy consumption overhead for different network configurations. The proposed IAV module has presented reduced area and power consumption overhead when compared with similar existing solutions.

APA, Harvard, Vancouver, ISO, and other styles

3

Dudhane, Tanaji M., and T. Ravi. "Design and Implementation of Extended 16 Bit Co-Operative Arithmetic and Logic Unit (CALU) for 16 Bit Instructions." Journal of Low Power Electronics 15, no. 3 (September 1, 2019): 309–14. http://dx.doi.org/10.1166/jolpe.2019.1613.

Full text

Abstract:

CPU architecture has experienced great innovation in its architecture, from 8 bit to 64 bit, CISC to RISC, Single core to multi-core and single pipelined logic to deep multi-pipelined system. Today in an era of 64 bit architectures, 8 bits are still very relevant and has not lost its position and being used in many applications. Hence this research work deals with 8 bit CPU architecture and its features enhancement to make the 8 bit case very relevant in an era of 64 bit. The co-operative ALU, as name suggests, works in tandem with existing ALU and performs 16 bits operations. The specially designed instructions shares knowledge and efficiently handles existing ALU and Co-operative ALU to perform 8 bits and 16 bits operations. The Co-operative ALU is integrated with the 2 stage pipelined 8-bit RISC architecture ensuring that existing architecture is kept intact by way of applying new functionality in the form of an extension. The reconfigurable platform software tools are used for functionality verification and final deployment is done using reconfigurable platform hardware tools.

APA, Harvard, Vancouver, ISO, and other styles

4

Sakthivel, Erulappan, Veluchamy Malathi, and Muruganantham Arunraja. "A New Simulator Based on Multi Core Processor with Improved Sense Amplifier." Journal of Circuits, Systems and Computers 24, no. 09 (August 27, 2015): 1550141. http://dx.doi.org/10.1142/s0218126615501418.

Full text

Abstract:

In recent days, network-on-chip (NoC) researchers focus mainly on the area reduction and low power consumption both in architectural and algorithmic approach. To achieve low power and high performance in NoC architecture, sense amplifiers (SAs) introduced which can consume less power under various traffic conditions. In order to analyze the performance of architectural NoC design before fabrication level, the new simulator is developed based on multi core processor with improved sense amplifier (MCPSA) in this work. The MCPSA simulator provides user, the flexibility of incorporating various traffic configurations and routing algorithm with user reconfigurable option. In addition, the different SA model can be put into the simulation in plug and play manner for evaluation. The NoC case studies are presented to demonstrate the NoC architecture with double tail sense amplifier (DTSA) and modified-DTSA (M-DTSA) design. The performance metric such as delay, data rate and power consumption is evaluated. The main idea of this new simulator is to interface multisim environment (MSE) into a NoC environment for validating any DTSA.

APA, Harvard, Vancouver, ISO, and other styles

5

Brandalero, Marcelo, Thiago Dadalt Souto, Luigi Carro, and Antonio Carlos Schneider Beck. "Predicting performance in multi-core systems with shared reconfigurable accelerators." Journal of Systems Architecture 98 (September 2019): 201–13. http://dx.doi.org/10.1016/j.sysarc.2019.07.010.

Full text

APA, Harvard, Vancouver, ISO, and other styles

6

Kim, Yoonjin, Hyejin Joo, and Sohyun Yoon. "Inter‐coarse‐grained reconfigurable architecture reconfiguration technique for efficient pipelining of kernel‐stream on coarse‐grained reconfigurable architecture‐based multi‐core architecture." IET Circuits, Devices & Systems 10, no. 4 (July 2016): 251–65. http://dx.doi.org/10.1049/iet-cds.2015.0047.

Full text

APA, Harvard, Vancouver, ISO, and other styles

7

Venkatavara Prasad, D., and Maddineni Deepthi. "Reconfigurable Architecture for Minimizing the Network Delays in the Multi-core Systems." Research Journal of Applied Sciences, Engineering and Technology 9, no. 8 (March 15, 2015): 637–44. http://dx.doi.org/10.19026/rjaset.9.1448.

Full text

APA, Harvard, Vancouver, ISO, and other styles

8

Garzia, Fabio, Roberto Airoldi, and Jari Nurmi. "Implementation of FFT on General-Purpose Architectures for FPGA." International Journal of Embedded and Real-Time Communication Systems 1, no. 3 (July 2010): 24–43. http://dx.doi.org/10.4018/jertcs.2010070102.

Full text

Abstract:

This paper describes two general-purpose architectures targeted to Field Programmable Gate Array (FPGA) implementation. The first architecture is based on the coupling of a coarse-grain reconfigurable array with a general-purpose processor core. The second architecture is a homogeneous multi-processor system-on-chip (MP-SoC). Both architectures have been mapped onto two different Altera FPGA devices, a StratixII and a StratixIV. Although mapping onto the StratixIV results in higher operating frequencies, the capabilities of the device are not fully exploited. The implementation of a FFT on the two platforms shows a considerable speed-up in comparison with a single-processor reference architecture. The speed-up is higher in the reconfigurable solution but the MP-SoC provides an easier programming interface that is completely based on C language. The authors’ approach proves that implementing a programmable architecture on FPGA and then programming it using a high-level software language is a viable alternative to designing a dedicated hardware block with a hardware description language (HDL) and mapping it on FPGA.

APA, Harvard, Vancouver, ISO, and other styles

9

Lu, Chun Hsien, Chih Sheng Lin, Hung Lin Chao, Jih g. Shen, and Pao Ann Hsiung. "Reconfigurable multi-core architecture - a plausible solution to the von Neumann performance bottleneck." International Journal of Adaptive and Innovative Systems 2, no. 3 (2015): 217. http://dx.doi.org/10.1504/ijais.2015.074399.

Full text

APA, Harvard, Vancouver, ISO, and other styles

10

R, Maheswari, Pattabiraman V, and Sharmila P. "RECONFIGURABLE FPGA BASED SOFT-CORE PROCESSOR FOR SIMD APPLICATIONS." Asian Journal of Pharmaceutical and Clinical Research 10, no. 13 (April 1, 2017): 180. http://dx.doi.org/10.22159/ajpcr.2017.v10s1.19632.

Full text

Abstract:

Objective: The prospective need of SIMD (Single Instruction and Multiple Data) applications like video and image processing in single system requires greater flexibility in computation to deliver high quality real time data. This paper performs an analysis of FPGA (Field Programmable Gate Array) based high performance Reconfigurable OpenRISC1200 (ROR) soft-core processor for SIMD.Methods: The ROR1200 ensures performance improvement by data level parallelism executing SIMD instruction simultaneously in HPRC (High Performance Reconfigurable Computing) at reduced resource utilization through RRF (Reconfigurable Register File) with multiple core functionalities. This work aims at analyzing the functionality of the reconfigurable architecture, by illustrating the implementation of two different image processing operations such as image convolution and image quality improvement. The MAC (Multiply-Accumulate) unit of ROR1200 used to perform image convolution and execution unit with HPRC is used for image quality improvement.Result: With parallel execution in multi-core, the proposed processor improves image quality by doubling the frame rate up-to 60 fps (frames per second) with peak power consumption of 400mWatt. Thus the processor gives a significant computational cost of 12ms with a refresh rate of 60Hz and 1.29ns of MAC critical path delay.Conclusion:This FPGA based processor becomes a feasible solution for portable embedded SIMD based applications which need high performance at reduced power consumptions

APA, Harvard, Vancouver, ISO, and other styles

11

Jung, Yong-Kyu. "Hardware/Software Co-reconfigurable Instruction Decoder for Adaptive Multi-core DSP Architectures." Journal of Signal Processing Systems 62, no. 3 (March 17, 2010): 273–85. http://dx.doi.org/10.1007/s11265-010-0461-1.

Full text

APA, Harvard, Vancouver, ISO, and other styles

12

Dousti, Mohammad J., Alireza Shafaei, and Massoud Pedram. "Squash 2: a hierarchical scalable quantum mapper considering ancilla sharing." Quantum Information and Computation 16, no. 3&4 (March 2016): 332–56. http://dx.doi.org/10.26421/qic16.3-4-8.

Full text

Abstract:

We present a multi-core reconfigurable quantum processor architecture, called Requp, which supports a hierarchical approach to mapping a quantum algorithm while sharing physical and logical ancilla qubits. Each core is capable of performing any quantum instruction. Moreover, we introduce a scalable quantum mapper, called Squash 2, which divides a given quantum circuit into a number of quantum modules—each module is divided into k parts such that each part will run on one of k available cores. Experimental results demonstrate that Squash 2 can handle large-scale quantum algorithms while providing an effective mechanism for sharing ancilla qubits.

APA, Harvard, Vancouver, ISO, and other styles

13

Kritikos, William V., Andrew G. Schmidt, Ron Sass, Erik K. Anderson, and Matthew French. "Redsharc: A Programming Model and On-Chip Network for Multi-Core Systems on a Programmable Chip." International Journal of Reconfigurable Computing 2012 (2012): 1–11. http://dx.doi.org/10.1155/2012/872610.

Full text

Abstract:

The reconfigurable data-stream hardware software architecture (Redsharc) is a programming model and network-on-a-chip solution designed to scale to meet the performance needs of multi-core Systems on a programmable chip (MCSoPC). Redsharc uses an abstract API that allows programmers to develop systems of simultaneously executing kernels, in software and/or hardware, that communicate over a seamless interface. Redsharc incorporates two on-chip networks that directly implement the API to support high-performance systems with numerous hardware kernels. This paper documents the API, describes the common infrastructure, and quantifies the performance of a complete implementation. Furthermore, the overhead, in terms of resource utilization, is reported along with the ability to integrate hard and soft processor cores with purely hardware kernels being demonstrated.

APA, Harvard, Vancouver, ISO, and other styles

14

Gnanaolivu, Rani, Theodore S. Norvell, and Ramachandran Venkatesan. "Analysis of Inner-Loop Mapping onto Coarse-Grained Reconfigurable Architectures Using Hybrid Particle Swarm Optimization." International Journal of Organizational and Collective Intelligence 2, no. 2 (April 2011): 17–35. http://dx.doi.org/10.4018/joci.2011040102.

Full text

Abstract:

Coarse-Grained Reconfigurable Architectures (CGRAs) have gained currency in recent years due to their abundant parallelism and flexibility. To utilize the parallelism found in CGRAs, this paper proposes a fast and efficient Modulo-Constrained Hybrid Particle Swarm Optimization (MCHPSO) scheduling algorithm to exploit loop-level parallelism in applications. This paper shows that Particle Swarm Optimization (PSO) is capable of software pipelining loops by overlapping placement, scheduling and routing of successive loop iterations and executing them in parallel. The proposed algorithm has been experimentally validated on various DSP benchmarks under two different architecture configurations. These experiments indicate that the proposed MCHPSO algorithm can find schedules with small initiation intervals within a reasonable amount of time. The MCHPSO scheduling algorithm was analyzed with different topologies and Functional Unit (FU) configurations. The authors have tested the parallelizability of the algorithm and found that it exhibits a nearly linear speedup on a multi-core CPU.

APA, Harvard, Vancouver, ISO, and other styles

15

Pan, Shing-Tai, Ching-Fa Chen, and Wen-Sin Tseng. "Efficient robust speech recognition with empirical mode decomposition using an FPGA chip with dual core." International Journal of Reconfigurable and Embedded Systems (IJRES) 9, no. 2 (July 1, 2020): 109. http://dx.doi.org/10.11591/ijres.v9.i2.pp109-115.

Full text

Abstract:

The purpose of this paper is to accelate the computing speed of Empirical Mode Decomposition (EMD) based on multi-core embedded systems for robust speech recognition. A reconfigurable chip, Field Programmable Gate Array (FPGA), is used for the implementation of the designed system. This paper applies EMD to discompose some noised speech signals into several Intrinsic Mode Functions (IMFs). These IMFs will be combined to recover the original speech by multiplying their corresponding weights which were trained by Genetic Algorithms (GA). After applying Empirical Mode Decomposition (EMD), we obtain a cleaner speech for recognition. Due to the complexity of the computation of the EMD, a dual-core architecture of embedded system on FPGA is proposed to accelerate the computing speed of EMD for robust speech recognition. This will enhance the efficiency of embedded speech recognition system.

APA, Harvard, Vancouver, ISO, and other styles

16

Mushtaq, Hassan, Sajid Gul Khawaja, Muhammad Usman Akram, Amanullah Yasin, Muhammad Muzammal, Shehzad Khalid, and Shoab Ahmad Khan. "A Parallel Architecture for the Partitioning Around Medoids (PAM) Algorithm for Scalable Multi-Core Processor Implementation with Applications in Healthcare." Sensors 18, no. 12 (November 25, 2018): 4129. http://dx.doi.org/10.3390/s18124129.

Full text

Abstract:

Clustering is the most common method for organizing unlabeled data into its natural groups (called clusters), based on similarity (in some sense or another) among data objects. The Partitioning Around Medoids (PAM) algorithm belongs to the partitioning-based methods of clustering widely used for objects categorization, image analysis, bioinformatics and data compression, but due to its high time complexity, the PAM algorithm cannot be used with large datasets or in any embedded or real-time application. In this work, we propose a simple and scalable parallel architecture for the PAM algorithm to reduce its running time. This architecture can easily be implemented either on a multi-core processor system to deal with big data or on a reconfigurable hardware platform, such as FPGA and MPSoCs, which makes it suitable for real-time clustering applications. Our proposed model partitions data equally among multiple processing cores. Each core executes the same sequence of tasks simultaneously on its respective data subset and shares intermediate results with other cores to produce results. Experiments show that the computational complexity of the PAM algorithm is reduced exponentially as we increase the number of cores working in parallel. It is also observed that the speedup graph of our proposed model becomes more linear with the increase in number of data points and as the clusters become more uniform. The results also demonstrate that the proposed architecture produces the same results as the actual PAM algorithm, but with reduced computational complexity.

APA, Harvard, Vancouver, ISO, and other styles

17

Wang, Jian, and Ying Li. "RDAMS: An Efficient Run-Time Approach for Memory Fault and Hardware Trojans Detection." Information 12, no. 4 (April 14, 2021): 169. http://dx.doi.org/10.3390/info12040169.

Full text

Abstract:

Ensuring the security of IoT devices and chips at runtime has become an urgent task as they have been widely used in human life. Embedded memories are vital components of SoC (System on Chip) in these devices. If they are attacked or incur faults at runtime, it will bring huge losses. In this paper, we propose a run-time detection architecture for memory security (RDAMS) to detect memory threats (fault and Hardware Trojans attack). The architecture consists of a Security Detection Core (SDC) that controls and enforces the detection procedure as a “security brain”, and a memory wrapper (MEM_wrapper) which interacts with memory to assist the detection. We also design a low latency response mechanism to solve the SoC performance degradation caused by run-time detection. A block-based multi-granularity detection approach is proposed to render the design flexible and reduce the cost in implementation using the FPGA’s dynamic partial reconfigurable (DPR) technology, which enables online detection mode reconfiguration according to the requirements. Experimental results show that RDAMS can correctly detect and identify 10 modeled memory faults and two types of Hardware Trojans (HTs) attacks without leading a great performance degradation to the system.

APA, Harvard, Vancouver, ISO, and other styles

18

Lv, Risheng, Weiping Chen, and Xiaowei Liu. "A High-Dynamic-Range Switched-Capacitor Sigma-Delta ADC for Digital Micromechanical Vibration Gyroscopes." Micromachines 9, no. 8 (July 27, 2018): 372. http://dx.doi.org/10.3390/mi9080372.

Full text

Abstract:

This paper presents a multi-stage noise shaping (MASH) switched-capacitor (SC) sigma-delta (ΣΔ) analog-to-digital converter (ADC) composed of an analog modulator with an on-chip noise cancellation logic and a reconfigurable digital decimator for MEMS digital gyroscope applications. A MASH 2-1-1 structure is employed to guarantee an absolutely stable modulation system. Based on the over-sampling and noise-shaping techniques, the core modulator architecture is a cascade of three single-loop stages containing feedback paths for systematic optimization to avoid deterioration in conversion accuracy caused by capacitor mismatch. A digital noise cancellation logic is also included to eliminate residual quantization errors in the former two stages, and those in the last stage are shaped by a fourth-order modulation. A multi-rate decimator follows the analog modulator to suit variable gyroscope bandwidth. Manufactured in a standard 0.35 μm CMOS technology, the whole chip occupies an area of 3.8 mm2. Experimental results show a maximum signal-to-noise ratio (SNR) of 100.2 dB and an overall dynamic range (DR) of 107.6 dB, with a power consumption of 3.2 mW from a 5 V supply. This corresponds to a state-of-the-art figure-of-merit (FoM) of 165.6 dB.

APA, Harvard, Vancouver, ISO, and other styles

19

Chen, Qinyu, Yuxiang Fu, Wenqing Song, Kaifeng Cheng, Zhonghai Lu, Chuan Zhang, and Li Li. "An Efficient Streaming Accelerator for Low Bit-Width Convolutional Neural Networks." Electronics 8, no. 4 (March 27, 2019): 371. http://dx.doi.org/10.3390/electronics8040371.

Full text

Abstract:

Convolutional Neural Networks (CNNs) have been widely applied in various fields, such as image recognition, speech processing, as well as in many big-data analysis tasks. However, their large size and intensive computation hinder their deployment in hardware, especially on the embedded systems with stringent latency, power, and area requirements. To address this issue, low bit-width CNNs are proposed as a highly competitive candidate. In this paper, we propose an efficient, scalable accelerator for low bit-width CNNs based on a parallel streaming architecture. With a novel coarse grain task partitioning (CGTP) strategy, the proposed accelerator with heterogeneous computing units, supporting multi-pattern dataflows, can nearly double the throughput for various CNN models on average. Besides, a hardware-friendly algorithm is proposed to simplify the activation and quantification process, which can reduce the power dissipation and area overhead. Based on the optimized algorithm, an efficient reconfigurable three-stage activation-quantification-pooling (AQP) unit with the low power staged blocking strategy is developed, which can process activation, quantification, and max-pooling operations simultaneously. Moreover, an interleaving memory scheduling scheme is proposed to well support the streaming architecture. The accelerator is implemented with TSMC 40 nm technology with a core size of 0.17 mm 2 . It can achieve 7.03 TOPS/W energy efficiency and 4.14 TOPS/mm 2 area efficiency at 100.1 mW, which makes it a promising design for the embedded devices.

APA, Harvard, Vancouver, ISO, and other styles

20

WEY, Chin-Long, Shin-Yo LIN, Pei-Yun TSAI, and Ming-Der SHIEH. "Reconfigurable Homogenous Multi-Core FFT Processor Architectures for Hybrid SISO/MIMO OFDM Wireless Communications." IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E94-A, no. 7 (2011): 1530–39. http://dx.doi.org/10.1587/transfun.e94.a.1530.

Full text

APA, Harvard, Vancouver, ISO, and other styles

21

Luong Van, Hieu, and Kien Do Trung. "OPTIMAL PROVISIONING OF OPTICAL NETWORKS WITH ASYMMETRIC NODES." Journal of Science Natural Science 65, no. 10 (October 2020): 36–48. http://dx.doi.org/10.18173/2354-1059.2020-0046.

Full text

Abstract:

Wavelength Switched Optical Networks (WSONs) have been designed to take advantage of all optical switching fabrics with a high level of automation and efficiency. Therein, the Wavelength Selective Switches (WSS) represent the core switching elements with a technology enabling multi-degree Reconfigurable Optical Add\Drop Multiplexers (ROADM) architectures with colorless and directionless switching. In this paper, we propose an optimization model to establish the best ROADM switching connectivity to maximize the grade of service, for a given number of ports. We show that the grade of service can vary significantly, up to 30%, depending on the switching connectivity. Besides, the larger the network is, the more the variance increases: from 20% to 30%, when the number of nodes varies from 14 to 24.

APA, Harvard, Vancouver, ISO, and other styles

22

Manco, Angelo, and Vittorio U. Castrillo. "An FPGA Scalable Software-Defined Radio Platform for UAS Communications Research." Journal of Communications, 2021, 42–51. http://dx.doi.org/10.12720/jcm.16.2.42-51.

Full text

Abstract:

In the framework of modern Unmanned Aerial System (UAS) ground-board communications, a data-link system should provide with the following features [1]: multiband and adaptive modulations for responding to channel conditions changes and multi-standard interoperability, interferences resilience with a secure physical layer, incorporation of an air-to-air link complementary to the classical air-to-ground links. Varying the available communication functions to provide the above features without the need to substitute on-board components is a desired target. For this purpose, a Field Programmable Gate Aray (FPGA) scalable Software Defined Radio hardware Platform (SDRP) and its control and baseband signal processing architecture have been developed. The platform is composed by means of three boards which provide respectively the power supply, an FPGA based processing core and the radio frequency front-end. The control and baseband signal processing architecture, implemented on the FPGA, is designed with an application-independent section, working as a base reference design, and a reconfigurable section that implements communication functions and algorithms. The overall platform, at the board and FPGA architecture level, has been designed considering scalability and modularity as key features. Thanks to this platform a data-link which responds to the above target can be easily implemented. As a case study a reconfigurable data-link between a UAS and a Ground Control Station (GCS), designed to establish reliable communication in all the phases of a flight (parking, taxiing, taking off, cruising and landing), is presented.

APA, Harvard, Vancouver, ISO, and other styles

Journal articles on the topic 'Reconfigurable Multi-Core architecture'

Create a spot-on reference in APA, MLA, Chicago, Harvard, and other styles