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Journal articles on the topic 'Semiconductors : Etching : Plasma etching'

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Published: 4 June 2021

Last updated: 6 February 2022

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1

PEARTON, S. J. "REACTIVE ION ETCHING OF III–V SEMICONDUCTORS." International Journal of Modern Physics B 08, no. 14 (1994): 1781–876. http://dx.doi.org/10.1142/s0217979294000762.

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Anisotropic dry etching by a number of different techniques is widely employed in III–V compound semiconductor technology for pattern transfer, device isolation, mesa formation, grating fabrication and via hole etching. In this paper we review the different dry etching techniques, the plasma chemistries employed for III–V materials and electrical and optical changes to the near-surface of the etched sample. We give examples of the use of dry etching in fabrication of heterojunction bipolar transistors, field effect transistors and various types of semiconductor lasers. Particular attention is paid to the characteristics of Electron Cyclotron Resonance discharges operating at high ion densities (≥5×1011 cm −3) and low pressure (~1 mTorr) with low ion energies (≤15 eV ) which are ideally suited for dry etching of III–V semiconductors.

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2

Zolper, J. C., and R. J. Shul. "Implantation and Dry Etching of Group-III-Nitride Semiconductors." MRS Bulletin 22, no. 2 (1997): 36–43. http://dx.doi.org/10.1557/s0883769400032553.

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The recent advances in the material quality of the group-III-nitride semiconductors (GaN, A1N, and InN) have led to the demonstration of high-brightness light-emitting diodes, blue laser diodes, and high-frequency transistors, much of which is documented in this issue of MRS Bulletin. While further improvements in the material properties can be expected to enhance device operation, further device advances will also require improved processing technology. In this article, we review developments in two critical processing technologies for photonic and electronic devices: ion implantation and plasma etching. Ion implantation is a technology whereby impurity atoms are introduced into the semiconductor with precise control of concentration and profile. It is widely used in mature semiconductor materials systems such as silicon or gallium arsenide for selective area doping or isolation. Plasma etching is employed to define device features in the semiconductor material with controlled profiles and etch depths. Plasma etching is particularly necessary in the III-nitride materials systems due to the lack of suitable wet-etch chemistries, as will be discussed later.Figure 1 shows a laser-diode structure (after Nakamura) where plasma etching is required to form the laser facets that ideally should be vertical with smooth surfaces. The first III-nitride-based laser diode was fabricated using reactive ion etching (RIE) to form the laser facets but suffered from rough mirror facet surfaces that contributed to scattering loss and a high lasing threshold. This is a prime example of how improved material quality alone will not yield optimum device performance.

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3

Lee, J. W. "IC1 plasma etching of III–V semiconductors." Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures 15, no. 3 (1997): 652. http://dx.doi.org/10.1116/1.589308.

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4

Shul, R. J., G. B. McClellan, R. D. Briggs, et al. "High-density plasma etching of compound semiconductors." Journal of Vacuum Science & Technology A: Vacuum, Surfaces, and Films 15, no. 3 (1997): 633–37. http://dx.doi.org/10.1116/1.580696.

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5

Madziwa-Nussinov, Tsitsi G., Donald Arnush, and Francis F. Chen. "Ion orbits in plasma etching of semiconductors." Physics of Plasmas 15, no. 1 (2008): 013503. http://dx.doi.org/10.1063/1.2819681.

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6

VOSHCHENKOV, ALEXANDER M. "FUNDAMENTALS OF PLASMA ETCHING FOR SILICON TECHNOLOGY (PART 1)." International Journal of High Speed Electronics and Systems 01, no. 03n04 (1990): 303–45. http://dx.doi.org/10.1142/s0129156490000149.

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Over the past decade, as the rapid evolution of semiconductor technology has progressed towards submicron design rules, plasma (dry) etching has supplanted simple wet etching processes for the transfer of patterns. To understand the underlying need for development of plasma etching, a brief background of integrated semiconductor technology is presented. Along with a historical perspective of the evolution of plasma etching, the relationship of plasma etching to lithography needs, its basic characteristics and advantages over wet chemical processing are discussed. Following this, relevant concepts of plasma physics and chemistry, based on experience with plasma etching applications for silicon technology, which can be used as building blocks for technology development are described.

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7

Kawasaki, Ryohei, Kenta Irikura, Hitoshi Habuka, Yoshinao Takahashi, and Tomohisa Kato. "Non-Plasma Dry Etcher Design for 200 mm-Diameter Silicon Carbide Wafer." Materials Science Forum 1004 (July 2020): 167–72. http://dx.doi.org/10.4028/www.scientific.net/msf.1004.167.

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For improving the productivity of the semiconductor silicon carbide power devices, a very large diameter wafer process was studied, particularly for the non-plasma wafer etching using the chlorine trifluoride gas. Taking into account the motion of heavy gas, such as the chlorine trifluoride gas having the large molecular weight, the transport phenomena in the etching reactor were evaluated and designed using the computational fluid dynamics. The simple gas distributor design for a 200-mm-diameter wafer was evaluated in detail in order to uniformly spread the etchant gas over the wide wafer surface.

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8

L Hitchman, Michael. "Plasma etching in semiconductor fabrication." Vacuum 36, no. 5 (1986): 293. http://dx.doi.org/10.1016/0042-207x(86)90610-x.

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9

Pearton, Stephen J., Erica A. Douglas, Randy J. Shul, and Fan Ren. "Plasma etching of wide bandgap and ultrawide bandgap semiconductors." Journal of Vacuum Science & Technology A 38, no. 2 (2020): 020802. http://dx.doi.org/10.1116/1.5131343.

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10

Reksten, Grace M., W. Holber, and R. M. Osgood. "Wavelength dependence of laser enhanced plasma etching of semiconductors." Applied Physics Letters 48, no. 8 (1986): 551–53. http://dx.doi.org/10.1063/1.96504.

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11

Saito, Suguru, Yoshiya Hagimoto, Hayato Iwamoto, and Yusuke Muraki. "Mechanism of Plasma-Less Gaseous Etching Process for Damaged Oxides from the Ion Implantation Process." Solid State Phenomena 145-146 (January 2009): 227–30. http://dx.doi.org/10.4028/www.scientific.net/ssp.145-146.227.

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Recently, plasma-less gaseous etching processes have attracted attention for their interesting etching properties. Previously, we reported on the etching properties of theses processes for various kinds of oxides and revealed that they reduce the etch rate of the chemical-vapor-deposited (CVD) oxides more than the conventional wet etching process does [1]. Our results also revealed that depressions called divots in the CVD oxide of the shallow trench isolation (STI) became smaller in size by substituting a plasma-less gaseous etching process for the conventional wet etching process. In semiconductor manufacturing, many processes are used to remove oxides damaged during ion implantation or reactive ion etching on the device surface. Therefore, it is very important to understand the etching properties of plasma-less gaseous etching processes for damaged oxides as well as those for other kinds of oxides. In this report, we evaluate the etching properties of one particular plasma-less gaseous etching process for oxide films damaged during the ion implantation process under various conditions and discuss the mechanism of interesting etching properties for the damaged oxides.

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12

Economou, Demetre J. "Pulsed plasma etching for semiconductor manufacturing." Journal of Physics D: Applied Physics 47, no. 30 (2014): 303001. http://dx.doi.org/10.1088/0022-3727/47/30/303001.

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13

Xu, Qing, Yu-Xing Li, Xiao-Ning Li, et al. "Simulation of SiO2 etching in an inductively coupled CF4 plasma." Modern Physics Letters B 31, no. 06 (2017): 1750042. http://dx.doi.org/10.1142/s0217984917500427.

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Plasma etching technology is an indispensable processing method in the manufacturing process of semiconductor devices. Because of the high fluorine/carbon ratio of CF4, the CF4 gas is often used for etching SiO2. A commercial software ESI-CFD is used to simulate the process of plasma etching with an inductively coupled plasma model. For the simulation part, CFD-ACE is used to simulate the chamber, and CFD-TOPO is used to simulate the surface of the sample. The effects of chamber pressure, bias voltage and ICP power on the reactant particles were investigated, and the etching profiles of SiO2 were obtained. Simulation can be used to predict the effects of reaction conditions on the density, energy and angular distributions of reactant particles, which can play a good role in guiding the etching process.

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14

Adesida, I., C. Youtsey, A. T. Ping, F. Khan, L. T. Romano, and G. Bulman*. "Dry and Wet Etching for Group III – Nitrides." MRS Internet Journal of Nitride Semiconductor Research 4, S1 (1999): 38–48. http://dx.doi.org/10.1557/s1092578300002222.

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The group-III nitrides have become versatile semiconductors for short wavelength emitters, high temperature microwave transistors, photodetectors, and field emission tips. The processing of these materials is significant due to the unusually high bond energies that they possess. The dry and wet etching methods developed for these materials over the last few years are reviewed. High etch rates and highly anisotropic profiles obtained by inductively-coupled-plasma reactive ion etching are presented. Photoenhanced wet etching provides an alternative path to obtaining high etch rates without ion-induced damage. This method is shown to be suitable for device fabrication as well as for the estimation of dislocation densities in n-GaN. This has the potential of developing into a method for rapid evaluation of materials.

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15

Schwarzl, Th, W. Heiß, G. Kocher-Oberlehner, and G. Springholz. "plasma etching of IV-VI semiconductor nanostructures." Semiconductor Science and Technology 14, no. 2 (1999): L11—L14. http://dx.doi.org/10.1088/0268-1242/14/2/003.

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16

Armacost, M., P. D. Hoh, R. Wise, et al. "Plasma-etching processes for ULSI semiconductor circuits." IBM Journal of Research and Development 43, no. 1.2 (1999): 39–72. http://dx.doi.org/10.1147/rd.431.0039.

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17

Li, Jie, Yongjae Kim, Seunghun Han, and Heeyeop Chae. "Ion-Enhanced Etching Characteristics of sp2-Rich Hydrogenated Amorphous Carbons in CF4 Plasmas and O2 Plasmas." Materials 14, no. 11 (2021): 2941. http://dx.doi.org/10.3390/ma14112941.

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The sp2-rich hydrogenated amorphous carbon (a-C:H) is widely adopted as hard masks in semiconductor-device fabrication processes. The ion-enhanced etch characteristics of sp2-rich a-C:H films on ion density and ion energy were investigated in CF4 plasmas and O2 plasmas in this work. The etch rate of sp2-rich a-C:H films in O2 plasmas increased linearly with ion density when no bias power was applied, while the fluorocarbon deposition was observed in CF4 plasmas instead of etching without bias power. The etch rate was found to be dependent on the half-order curve of ion energy in both CF4 plasmas and O2 plasmas when bias power was applied. An ion-enhanced etching model was suggested to fit the etch rates of a-C:H in CF4 plasmas and O2 plasmas. Then, the etch yield and the threshold energy for etching were determined based on this model from experimental etch rates in CF4 plasma and O2 plasma. The etch yield of 3.45 was observed in CF4 plasmas, while 12.3 was obtained in O2 plasmas, owing to the high reactivity of O radicals with carbon atoms. The threshold energy of 12 eV for a-C:H etching was obtained in O2 plasmas, while the high threshold energy of 156 eV was observed in CF4 plasmas. This high threshold energy is attributed to the formation of a fluorocarbon layer that protects the a-C:H films from ion-enhanced etching.

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18

CHOI, S. S., M. Y. JUNG, J. W. KIM, J. H. BOO, and J. S. YANG. "FABRICATION OF NEARFIELD OPTICAL PROBE ARRAY USING VARIOUS NANOFABRICATION PROCEDURES." International Journal of Nanoscience 02, no. 04n05 (2003): 283–91. http://dx.doi.org/10.1142/s0219581x03001309.

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The nanosize silicon oxide aperture on the cantilever array has been successfully fabricated as nearfield optical probe. The various semiconductor processes were utilized for subwavelength size aperture fabrication. The anisotropic etching of the Si substrate by alkaline solutions followed by anisotropic crystal orientation dependent oxidation, anisotropic plasma etching, isotropic oxide etching was carried out. The 3 and 4 micron size dot array were patterned on the Si(100) wafer. After fabrication of the V-groove shape by anisotropic TMAH etching, the oxide growth at 1000° C was performed to have an oxide etch-mask. The oxide layer on the Si(111) plane have been utilized as an etch mask for plasma dry etching and water-diluted HF wet etching for nanosize aperture fabrication. The Au thin layer was deposited on the fabricated oxide nanosize aperture on the cantilever array. The 160 nm metal apertures on (5×1) cantilever array were successfully fabricated using electron beam evaporator.

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19

PEARTON, S. J. "HYDROGEN IN CRYSTALLINE SEMICONDUCTORS: PART II–III–V COMPOUNDS." International Journal of Modern Physics B 08, no. 10 (1994): 1247–342. http://dx.doi.org/10.1142/s0217979294000592.

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The properties of hydrogen in III–V semiconductors are reviewed. Atomic hydrogen is found to passivate the electrical activity of shallow donor and acceptor dopants in virtually all III–V materials, including GaAs, Alx Ga1−x As, InP, InGaAs, GaP, InAs, GaSb, InGaP, AlInAs and AlGaAsSb. The passivation is due to the formation of neutral dopant-hydrogen complexes, with hydrogen occupying a bond-centered position in p-type semiconductors and an anti-bonding site in n-type materials. The dopants are reactivated by annealing at ≤400° C. The neutral hydrogen-dopant complexes have characteristic vibrational bands, around 2000cm−1 for stretching modes and 800cm−1 for wagging modes. Deep levels such as EL2, DX and metallic impurities are also passivated by hydrogen. The diffusivity of hydrogen is high in III–V semiconductors and unintentional incorporation can occur during epitaxial growth, annealing in H2, dry etching, water boiling, wet etching or chemical vapor deposition processes, Surface passivation by (NH4)xS or NH3 plasma treatment is also effective in lowering surface recombination velocities in many III-V semiconductors.

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20

Han, Chuankun, Yiyong Yang, Weifeng Liu, Yijia Lu, and Jia Cheng. "Experimental Study of SiO2 Sputter Etching Process in 13.56 MHz rf-Biased Inductively Coupled Plasma." SPIN 08, no. 02 (2018): 1850002. http://dx.doi.org/10.1142/s2010324718500029.

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Inductively coupled plasma (ICP) has been widely used in semiconductor manufacturing, especially in nanoscale etching and deposition process. It is important to understand the relationship among the 13.56[Formula: see text]MHz rf-biased power and the etching process. In this study, the effect of dual rf power on the SiO2 sputter etching is investigated by measuring the ion energy distributions (IEDs), ion flux and sputter etching rate. The results show that the IEDs transforms from uni-modal towards bi-modal distribution when rf-biased power is applied to electrode. The influence of source power, bias power, discharge pressure and current ratio on the ion flux, IEDs are investigated in detail. The energy separations measured by RFEA are in good agreement with analytical model. The ion flux can be modulated by the 13.56[Formula: see text]MHz rf-biased power. Moreover, the coil current ratio expands the control window of the ion bombardment energy for the ICP etch equipment while. Finally, an ion-enhanced etching model is introduced to obtain the sputter etching rate and reveals the influence of discharge conditions on the etch rate.

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21

Lee, J. W., E. S. Lambers, C. R. Abernathy, et al. "Inductively coupled plasma etching of III–V semiconductors in Cl2-based chemistries." Materials Science in Semiconductor Processing 1, no. 1 (1998): 65–73. http://dx.doi.org/10.1016/s1369-8001(98)00002-x.

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22

Maeda, T., J. W. Lee, R. J. Shul, et al. "Inductively coupled plasma etching of III–V semiconductors in BCl3-based chemistries." Applied Surface Science 143, no. 1-4 (1999): 183–90. http://dx.doi.org/10.1016/s0169-4332(98)00593-5.

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23

Maeda, T., J. W. Lee, R. J. Shul, et al. "Inductively coupled plasma etching of III–V semiconductors in BCl3-based chemistries." Applied Surface Science 143, no. 1-4 (1999): 174–82. http://dx.doi.org/10.1016/s0169-4332(98)00594-7.

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24

Efremov, A. M., S. A. Pivovarenok, and V. I. Svettsov. "Plasma parameters and etching mechanisms of metals and semiconductors in hydrogen chloride." Russian Microelectronics 38, no. 3 (2009): 147–59. http://dx.doi.org/10.1134/s1063739709030019.

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25

Lim, W. T., I. K. Baek, J. W. Lee, et al. "Planar Inductively Coupled BCl[sub 3] Plasma Etching of III-V Semiconductors." Journal of The Electrochemical Society 151, no. 5 (2004): G343. http://dx.doi.org/10.1149/1.1690292.

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26

Maeda, Takeshi, Hyun Cho, Jin Hong, and S. J. Pearton. "New plasma chemistries for etching III–V compound semiconductors: Bl3 and BBr3." Journal of Electronic Materials 28, no. 2 (1999): 118–23. http://dx.doi.org/10.1007/s11664-999-0229-1.

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27

Pearton, S. J., F. Ren, T. R. Fullowan, et al. "Plasma etching of III–V semiconductor thin films." Materials Chemistry and Physics 32, no. 3 (1992): 215–34. http://dx.doi.org/10.1016/0254-0584(92)90203-k.

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28

Ikegawa, Masato, Yoshihumi Ogawa, Ryoji Fukuyama, Tatehito Usui, and Jun’ichi Tanaka. "Direct Simulation Monte Carlo Analysis of Rarefied Gas Flow Structures and Ventilation of Etching Gas in Magneto-Microwave Plasma Etching Reactors." Journal of Fluids Engineering 124, no. 2 (2002): 476–82. http://dx.doi.org/10.1115/1.1459074.

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Gas flows in plasma etching reactors for semiconductor fabrication became a chief consideration in designing second-generation reactors with higher etching rates. An axisymmetrical model based on the direct simulation Monte Carlo method has been developed for analyzing rarefied gas flows in a vacuum chamber with the conditions of downstream pressure and gas flow rate. By using this simulator, rarefied gas flows with radicals and etch-products were calculated for microwave-plasma etching reactors. The results showed that the flow patterns in the plasma chamber strongly depend on the Knudsen number and the gas-supply structure. The ventilation of the etch-products in the plasma chamber was found to be improved both for higher Knudsen numbers and for gas-supply structures of the downward-flow type, as compared with those of the radial-flow or upward-flow types.

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29

Banhart, F., F. O. Phillipp, R. Bergmann, E. Czech, M. Konuma, and E. Bauser. "Silicon layers grown over SiO2 by liquid phase epitaxy: Electron Microscopical study." Proceedings, annual meeting, Electron Microscopy Society of America 48, no. 4 (1990): 566–67. http://dx.doi.org/10.1017/s042482010017596x.

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Defect-free silicon layers grown on insulators (SOI) are an essential component for future three-dimensional integration of semiconductor devices. Liquid phase epitaxy (LPE) has proved to be a powerful technique to grow high quality SOI structures for devices and for basic physical research. Electron microscopy is indispensable for the development of the growth technique and reveals many interesting structural properties of these materials. Transmission and scanning electron microscopy can be applied to study growth mechanisms, structural defects, and the morphology of Si and SOI layers grown from metallic solutions of various compositions.The treatment of the Si substrates prior to the epitaxial growth described here is wet chemical etching and plasma etching with NF3 ions. At a sample temperature of 20°C the ion etched surface appeared rough (Fig. 1). Plasma etching at a sample temperature of −125°C, however, yields smooth and clean Si surfaces, and, in addition, high anisotropy (small side etching) and selectivity (low etch rate of SiO2) as shown in Fig. 2.

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30

Garner, C. Michael. "Lithography for enabling advances in integrated circuits and devices." Philosophical Transactions of the Royal Society A: Mathematical, Physical and Engineering Sciences 370, no. 1973 (2012): 4015–41. http://dx.doi.org/10.1098/rsta.2011.0052.

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Because the transistor was fabricated in volume, lithography has enabled the increase in density of devices and integrated circuits. With the invention of the integrated circuit, lithography enabled the integration of higher densities of field-effect transistors through evolutionary applications of optical lithography. In 1994, the semiconductor industry determined that continuing the increase in density transistors was increasingly difficult and required coordinated development of lithography and process capabilities. It established the US National Technology Roadmap for Semiconductors and this was expanded in 1999 to the International Technology Roadmap for Semiconductors to align multiple industries to provide the complex capabilities to continue increasing the density of integrated circuits to nanometre scales. Since the 1960s, lithography has become increasingly complex with the evolution from contact printers, to steppers, pattern reduction technology at i-line, 248 nm and 193 nm wavelengths, which required dramatic improvements of mask-making technology, photolithography printing and alignment capabilities and photoresist capabilities. At the same time, pattern transfer has evolved from wet etching of features, to plasma etch and more complex etching capabilities to fabricate features that are currently 32 nm in high-volume production. To continue increasing the density of devices and interconnects, new pattern transfer technologies will be needed with options for the future including extreme ultraviolet lithography, imprint technology and directed self-assembly. While complementary metal oxide semiconductors will continue to be extended for many years, these advanced pattern transfer technologies may enable development of novel memory and logic technologies based on different physical phenomena in the future to enhance and extend information processing.

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31

NAGASAKA, MICHIO. "Special issue on semiconductors - Materials and processing technologies. Single slice plasma etching system." Journal of the Japan Society of Precision Engineering 51, no. 7 (1985): 1318–21. http://dx.doi.org/10.2493/jjspe1933.51.1318.

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32

Lee, J. W. "Cl2/Ar plasma etching of binary, ternary, and quaternary In-based compound semiconductors." Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures 14, no. 4 (1996): 2567. http://dx.doi.org/10.1116/1.588769.

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33

Avtaeva, S. V., and D. K. Otorbaev. "Diagnostics of plasma parameters of RF discharges in CF3Br during etching of semiconductors." Journal of Physics D: Applied Physics 26, no. 12 (1993): 2148–53. http://dx.doi.org/10.1088/0022-3727/26/12/009.

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34

IWASE, Chikatsu, Yuya SHIRAYAMA, Shuntaro YOKOSUKA, et al. "Development of Localized Plasma Etching System for Failure Analyses in Semiconductor Devices: (4)Precise Temperature Measured during Plasma Etching." Journal of the Vacuum Society of Japan 55, no. 4 (2012): 176–79. http://dx.doi.org/10.3131/jvsj2.55.176.

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35

Tak, Hyun Woo, Jun Ki Jang, Dain Sung, Doo San Kim, Dong Woo Kim, and Geun Young Yeom. "Etch characteristics of nanoscale ultra low-k dielectric using C3H2F6." Materials Express 10, no. 6 (2020): 834–40. http://dx.doi.org/10.1166/mex.2020.1777.

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Next generation semiconductor devices require ultra low dielectric constant (ULK) materials such as porous SiCOH on the back end of line structure for lower resistance and capacitance (RC) time delay, however, these ULK materials are easily damaged by the exposure to plasmas during the etching. In this study, etch characteristics of nanoscale TiN masked porous SiCOH such as etch rate, etch profile, surface damage, etc. and plasma characteristics by using C3H2F6 based gases have been investigated with a dual-frequency capacitively coupled plasma system (DF-CCP) and the results were compared with those by using conventional C4F8 based gases used for low-k dielectric etching. The results showed that, for the similar etch rates and etch profiles of porous SiCOH, lower sidewall damage was observed for the etching with the C3H2F6 compared to the C4F8. The analysis showed that it was related to less UV (less than 400 nm) emission and less fluorine radicals in the plasma for C3 H2F6 compared to C4F8, which leads to less fluorine diffusion to the sidewall surface of the etched porous SiCOH by the fluorine scavenging by hydrogen in C3H2F6.

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36

Tice, Scott, and Chan Geun Park. "Metal Etch in Advanced Immersion Tank with Precision Uniformity Using Agitation and Wafer Rotation." Solid State Phenomena 219 (September 2014): 138–42. http://dx.doi.org/10.4028/www.scientific.net/ssp.219.138.

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In semiconductor wafer fabrication, etching refers to the process of removing unwanted material from wafer surface through a subtractive process. Metal etching is most commonly used in the patterning of metal films for interconnects by establishing specific connection and conduction paths and can be classified by dry etching, de-plating and dissolution of the layers on various substrates such as silicon, SiO2, Si3N4, GaAs, germanium, and sapphire. Dry etching is used to produce very precise etching of vertical channels or vias forming the device features or lines which make up the conductive path because it is anisotropic or etching in one direction. Dry etching is achieved by using chemical gases and plasma in a process chamber so dry etching tools are very large, complex and expensive to purchase and operate. De-plating is a process of electro-chemically removing metal material from the surface of the wafer to an anode by creating a difference in electrical potential between the surface to be etched/de-plated (typically cathode) and the “target” or anode where the material is to be collected. De-plating in single wafer tools has also replaced immersion processing due to the better uniformity it provides. However, De-plating single wafer tools are also very large and expensive to operate and have low throughput (wafers per hour). Dissolution/Immersion is the used of recirculated chemical baths to perform the etching process. In an immersion bath chemical is used to dissolve the metal layer that is unprotected by the mask. Immersion metal etch process has been on the decline because of its isotropic etching property and poor etch uniformity caused by non-uniform chemical flow around wafers in the tank. For the most of etch processes lateral etching is undesired because it occurs on the walls of the features and makes them thinner or misshapen. As a result, most of critical etching steps are performed by dry etching systems. However, if etch uniformity is precise, immersion etching can be used for less critical features in place of complex dry etching and de-plating.

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37

Kim, Bobae, Sungbin Im, and Geonwook Yoo. "Performance Evaluation of CNN-Based End-Point Detection Using In-Situ Plasma Etching Data." Electronics 10, no. 1 (2020): 49. http://dx.doi.org/10.3390/electronics10010049.

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As the technology node shrinks and shifts towards complex architectures, accurate control of automated semiconductor manufacturing processes, particularly plasma etching, is crucial in yield, cost, and semiconductor performance. However, current endpoint detection (EPD) methods relying on the experience of skilled engineers result in process variations and even errors. This paper proposes an enhanced optimal EPD in the plasma etching process based on a convolutional neural network (CNN). The proposed approach performs feature extraction on the spectral data obtained by optical emission spectroscopy (OES) and successfully predicts optimal EPD time. For the purpose of comparison, the support vector machine (SVM) classifier and the Adaboost Ensemble classifier are also investigated; the CNN-based model demonstrates better performance than the two models.

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38

Abe, Haruhiko, Masahiro Yoneda, and Nobuo Fujiwara. "Developments of Plasma Etching Technology for Fabricating Semiconductor Devices." Japanese Journal of Applied Physics 47, no. 3 (2008): 1435–55. http://dx.doi.org/10.1143/jjap.47.1435.

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39

Abraham-Shrauner, Barbara. "Analytic models for plasma-assisted etching of semiconductor trenches." Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures 12, no. 4 (1994): 2347. http://dx.doi.org/10.1116/1.587762.

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Qin, Shu, James D. Bernstein, and Chung Chan. "Hydrogen etching for semiconductor materials in plasma doping experiments." Journal of Electronic Materials 25, no. 3 (1996): 507–11. http://dx.doi.org/10.1007/bf02666628.

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Sano, Yasuhisa, Masayo Watanabe, Takehiro Kato, Kazuya Yamamura, Hidekazu Mimura, and Kazuto Yamauchi. "Temperature Dependence of Plasma Chemical Vaporization Machining of Silicon and Silicon Carbide." Materials Science Forum 600-603 (September 2008): 847–50. http://dx.doi.org/10.4028/www.scientific.net/msf.600-603.847.

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Silicon carbide (SiC) is a promising semiconductor material for power devices. However, it is extremely hard and chemically stable; thus there is no efficient method of machining it without causing damage to the machined surface. Plasma chemical vaporization machining (PCVM) is plasma etching in atmospheric-pressure plasma. PCVM has a high removal rate because the radical density in atmospheric-pressure plasma is much higher than that in conventional low-pressure plasma. Although it was found that the machining characteristic of SiC by PCVM had stronger rf power dependence than that of Si, it has not been clear whether it is radical density dependence or temperature dependence. In this paper, the temperature dependences of the PCVM of Si and SiC are examined using pipe electrode apparatus. As a result, it is found that the removal rate of SiC has a much stronger temperature dependence than that of Si and that the surface roughness of the SiC Si face becomes worse as the etching temperature increases whereas that of the C face does not increase at etching temperatures of up to 360°C.

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Huff, Michael. "Recent Advances in Reactive Ion Etching and Applications of High-Aspect-Ratio Microfabrication." Micromachines 12, no. 8 (2021): 991. http://dx.doi.org/10.3390/mi12080991.

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This paper reviews the recent advances in reaction-ion etching (RIE) for application in high-aspect-ratio microfabrication. High-aspect-ratio etching of materials used in micro- and nanofabrication has become a very important enabling technology particularly for bulk micromachining applications, but increasingly also for mainstream integrated circuit technology such as three-dimensional multi-functional systems integration. The characteristics of traditional RIE allow for high levels of anisotropy compared to competing technologies, which is important in microsystems device fabrication for a number of reasons, primarily because it allows the resultant device dimensions to be more accurately and precisely controlled. This directly leads to a reduction in development costs as well as improved production yields. Nevertheless, traditional RIE was limited to moderate etch depths (e.g., a few microns). More recent developments in newer RIE methods and equipment have enabled considerably deeper etches and higher aspect ratios compared to traditional RIE methods and have revolutionized bulk micromachining technologies. The most widely known of these technologies is called the inductively-coupled plasma (ICP) deep reactive ion etching (DRIE) and this has become a mainstay for development and production of silicon-based micro- and nano-machined devices. This paper will review deep high-aspect-ratio reactive ion etching technologies for silicon, fused silica (quartz), glass, silicon carbide, compound semiconductors and piezoelectric materials.

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Sano, Yasuhisa, Hiroaki Nishikawa, Kohei Aida, et al. "Basic Experiment on Atmospheric-Pressure Plasma Etching with Slit Aperture for High-Efficiency Dicing of SiC Wafer." Materials Science Forum 740-742 (January 2013): 813–16. http://dx.doi.org/10.4028/www.scientific.net/msf.740-742.813.

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Silicon carbide (SiC) is a promising semiconductor material for high-temperature, high-frequency, high-power, and energy-saving applications. However, because the hardness and chemical stability of SiC are high, few conventional machining methods can handle this material efficiently. We previously developed a plasma chemical vaporization machining (PCVM) technique, which is an atmospheric-pressure plasma etching process, and investigated its application to the processing of SiC substrates. In this paper, we propose a novel style of PCVM technique for dicing, using slit apertures to confine the plasma. From experiments by means of an apparatus with a one-slit aperture formed by two masks, it was found that the kerf loss was almost proportional to the slit width, and that the etching depth increased with RF power. Furthermore, from experiments on a SiC wafer, we obtained a 130-μm etching depth and 300-μm kerf loss for an 11-min processing time and 200-μm slit width.

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Chang, Chun Ming, Ming Hua Shiao, Don Yau Chiang, et al. "Submicron Patterns on Sapphire Substrate Produced by Dual Layer Photoresist Complimentary Lithography." Applied Mechanics and Materials 284-287 (January 2013): 334–41. http://dx.doi.org/10.4028/www.scientific.net/amm.284-287.334.

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In this study, the combined technologies of dual-layer photoresist complimentary lithography (DPCL), inductively coupled plasma-reactive ion etching (ICP-RIE) and laser direct-write lithography (LDL) are applied to produce the submicron patterns on sapphire substrates. The inorganic photoresist has almost no resistance for chlorine containing plasma and aqueous acid etching solution. However, the organic photoresist has high resistance for chlorine containing plasma and aqueous acid etching solution. Moreover, the inorganic photoresist is less etched by oxygen plasma etching process. The organic and inorganic photoresists deposit sequentially into a composite photoresist on a substrate. The DPCL takes advantages of the complementary chemical properties of organic and inorganic photoresists. We fabricated two structures with platform and non-platform structure. The non-platform structure featured structural openings, the top and bottom diameters and the depth are approximately 780 nm, 500 nm and 233 nm, respectively. The platform structure featured structural openings, the top and bottom diameters and the depth are approximately 487 nm, 288 nm and 203 nm, respectively. The precision submicron or nanoscale patterns of large etched area and patterns with high aspect ratio can be quickly produced by this technique. This technology features a low cost but high yield production technology. It has the potential applications in fabrication of micro-/nanostructures and devices for the optoelectronic industry, semiconductor industry and energy industry.

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Belov, A. N., S. A. Gavrilov, Yu A. Demidov, and V. I. Shevyakov. "Features of the formation of porous alumina mask for local plasma etching of semiconductors." Nanotechnologies in Russia 6, no. 11-12 (2011): 711–16. http://dx.doi.org/10.1134/s199507801106005x.

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Yoshikawa, Takashi, Shigeru Kohmoto, Yoshimasa Sugimoto, and Kiyoshi Asakawa. "Cl2-ECR plasma etching of III/V semiconductors and its application to photonic devices." Electronics and Communications in Japan (Part II: Electronics) 77, no. 8 (1994): 24–34. http://dx.doi.org/10.1002/ecjb.4420770803.

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Constantine, C. "Plasma etching of III–V semiconductors in CH4/H2/Ar electron cyclotron resonance discharges." Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures 8, no. 4 (1990): 596. http://dx.doi.org/10.1116/1.585026.

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Lim, W. T., I. K. Baek, J. W. Lee, et al. "BCl3/Ne etching of III–V semiconductors in a planar inductively coupled plasma reactor." Applied Surface Science 222, no. 1-4 (2004): 74–81. http://dx.doi.org/10.1016/j.apsusc.2003.08.009.

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Park, Seung Hyun, Kyung Eon Kim, and Sang Jeen Hong. "Surface Analysis of Chamber Coating Materials Exposed to CF4/O2 Plasma." Coatings 11, no. 1 (2021): 105. http://dx.doi.org/10.3390/coatings11010105.

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Coating the inner surfaces of high-powered plasma processing equipment has become crucial for reducing maintenance costs, process drift, and contaminants. The conventionally preferred alumina (Al2O3) coating has been replaced with yttria (Y2O3) due to the long-standing endurance achieved by fluorine-based etching; however, the continuous increase in radio frequency (RF) power necessitates the use of alternative coating materials to reduce process shift in a series of high-powered semiconductor manufacturing environments. In this study, we investigated the fluorine-based etching resistance of atmospheric pressure-sprayed alumina, yttria, yttrium aluminum garnet (YAG), and yttrium oxyfluoride (YOF). The prepared ceramic-coated samples were directly exposed to silicon oxide etching, and the surfaces of the plasma-exposed samples were characterized by scanning electron microscopy, energy-dispersive X-ray spectroscopy, and X-ray photoelectron spectroscopy. We found that an ideal coating material must demonstrate high plasma-induced structure distortion by the fluorine atom from the radical. For endurance to fluorine-based plasma exposure, the bonding structure with fluoride was shown to be more effective than oxide-based ceramics. Thus, fluoride-based ceramic materials can be promising candidates for chamber coating materials.

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Evertsen, Rogier, Nicolle Beckers, Shao Ying Wang, and Richard van der Stam. "Remote Plasma Etching of Backend Semiconductor Materials for Reliable Packaging." Solid State Phenomena 314 (February 2021): 312–17. http://dx.doi.org/10.4028/www.scientific.net/ssp.314.312.

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This paper describes a study on the remote plasma etching of silicon-based semiconductor wafers after laser separation. Several process parameters having impact on the chip reliability, expressed as changes in die material strength, have been studied and optimized. The results show the potential of fluorine-based plasma processing for cleaning dies and improving die performance and thus have a role as a process enabling advanced packaging technologies.

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