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Journal articles on the topic 'Single event latch-up (SEL)'

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Published: 4 June 2025

Last updated: 15 July 2025

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Norsuzila, Ya'acob, Fauzan Ayob Muhammad, Tajudin Noraisyah, Kassim Murizah, and Laily Yusof Azita. "Single event latch-up detection for nano-satellite external solar radiation mitigation system." Bulletin of Electrical Engineering and Informatics 10, no. 1 (2021): 39–45. https://doi.org/10.11591/eei.v10i1.2488.

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This paper presents the single event latch-up (SEL) detection for nano-satellite external solar radiation mitigation system. In this study, the SEL detection analysis was conducted using circuit test and simulation. An electrical power subsystem (EPS) is a part of all CubeSat bus subsystems and it comprises solar arrays, rechargeable batteries, and a power control and distribution unit (PCDU). In order to extract the maximum power generated by the solar arrays, a peak power tracking topology is required. This may lead to the SEL with the presence of high voltage produced by solar. To overcome the SEL problems, the circuit test and simulation must be done so that the flow of SEL will be easily detected and mitigate. The method that been used are by using microcontroller, the SEL will be created in the certain time. The programable integrated circuit (PIC) are used to mitigate SEL effect. It indicates that, the SEL occur very fast in certain time. When the simulation is conducted by using SPENVIS, the result shows, only single event upset (SEU) was affected on UiTMSAT-1.

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Wang, Bin, Jianguo Cui, Ling Lv, and Longsheng Wu. "The Impact of Single-Event Radiation on Latch-Up Effect in High-Temperature CMOS Devices and Its Mechanism." Micromachines 16, no. 7 (2025): 783. https://doi.org/10.3390/mi16070783.

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This paper investigates the latch-up effect in CMOS devices based on a 28 nm CMOS process within the temperature range of 200 K to 450 K using Sentaurus Technology Computer-Aided Design (TCAD) simulation, with a particular focus on the single-event latch-up (SEL) effect in the high-temperature range of 300 K to 450 K. The physical mechanism underlying the triggering of SEL in CMOS devices at high temperatures is revealed. The results show that when the linear energy transfer (LET) value is 75 MeV cm2/mg, the CMOS devices do not exhibit SEL effects at 300 K and 350 K. However, when the temperature rises to 400 K, a significant latch-up effect occurs, which becomes more pronounced with increasing temperature. Additionally, at a supply voltage of 1.2 V and a temperature of 450 K, the LET threshold for triggering SEL in CMOS devices decreases by 91.4% compared to 75 MeV cm2/mg at 300 K, dropping to 6 MeV cm2/mg. As the temperature increases, the latch-up trigger current of the CMOS devices decreases from 1.18 × 10−4 A/μm at 300 K to 4.65 × 10−5 A/μm at 450 K, and the hold voltage decreases from 1.48 V at 300 K to 1.07 V at 450 K.

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Yaa’cob, Norsuzila, Muhammad Fauzan Ayob, Noraisyah Tajudin, Murizah Kassim, and Azita Laily Yusof. "Single event latch-up detection for nano-satellite external solar radiation mitigation system." Bulletin of Electrical Engineering and Informatics 10, no. 1 (2021): 39–45. http://dx.doi.org/10.11591/eei.v10i1.2488.

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Xin, Jindou, Xiang Zhu, Yingqi Ma, and Jianwei Han. "Study of Single Event Latch-Up Hardness for CMOS Devices with a Resistor in Front of DC-DC Converter." Electronics 12, no. 3 (2023): 550. http://dx.doi.org/10.3390/electronics12030550.

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Bulk silicon Complementary Metal Oxide Semiconductor (CMOS) devices have distinct single event latch-up (SEL) problems in aerospace. Therefore, it is essential that CMOS devices are designed with appropriate circuit-level methods. Traditional resistor hardness satisfies the current aerospace trend of low cost, high performance, and miniaturization. Therefore conventional resistor hardness is often applied in circuit-level designs due to the reduction of latch-up current. In circuits containing a DC-DC buck converter, the resistor is connected to the back of the converter in the traditional method. However, the traditional method is unable to take devices out of the latch-up owing to the small resistance range. To solve this problem, the paper proposes an improved design for the resistor in front of the DC-DC buck converter. The proposed method enables the devices to exit the latch-up by increasing the resistance range according to the input characteristic of the DC-DC buck converter. The paper quantifies the range of the resistor through the parametric model containing the resistor and the DC-DC buck converter. Two CMOS devices are chosen for pulsed laser experiments, verifying that the proposed method increases the resistance ranges by 300% to 400% compared to the conventional method. It is also demonstrated that the proposed method exits the devices from latch-up within the resistor ranges. That is, the resistance ranges of 34 Ω~41 Ω and 51 Ω~56 Ω reduce the latch-up currents of the devices to below holding currents of 72.1 mA and 24.2 mA, respectively.

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Sterpone, L. "SEL-UP: A CAD tool for the sensitivity analysis of radiation-induced Single Event Latch-Up." Microelectronics Reliability 53, no. 9-11 (2013): 1311–14. http://dx.doi.org/10.1016/j.microrel.2013.07.104.

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Mattos, André M. P., Douglas A. Santos, Lucas M. Luza, Viyas Gupta, and Luigi Dilillo. "Investigation of Single-Event Effects for Space Applications: Instrumentation for In-Depth System Monitoring." Electronics 13, no. 10 (2024): 1822. http://dx.doi.org/10.3390/electronics13101822.

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Ionizing radiation induces the degradation of electronic systems. For memory devices, this phenomenon is often observed as the corruption of the stored data and, in some cases, the occurrence of sudden increases in current consumption during the operation. In this work, we propose enhanced experimental instrumentation to perform in-depth Single-Event Effects (SEE) monitoring and analysis of electronic systems. In particular, we focus on the Single-Event Latch-up (SEL) phenomena in memory devices, in which current monitoring and control are required for testing. To expose the features and function of the proposed instrumentation, we present results for a case study of an SRAM memory that has been used on-board PROBA-V ESA satellite. For this study, we performed experimental campaigns in two different irradiation facilities with protons and heavy ions, demonstrating the instrumentation capabilities, such as synchronization, high sampling rate, fast response time, and flexibility. Using this instrumentation, we could report the cross section for the observed SEEs and further investigate their correlation with the observed current behavior. Notably, it allowed us to identify that 95% of Single-Event Functional Interrupts (SEFIs) were triggered during SEL events.

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Buitrago-Leiva, Jeimmy Nataly, Mohamed El Khayati Ramouz, Adriano Camps, and Joan A. Ruiz-de-Azua. "Statistical Analysis of LEO and GEO Satellite Anomalies and Space Radiation." Aerospace 11, no. 11 (2024): 924. http://dx.doi.org/10.3390/aerospace11110924.

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Exposure to space radiation substantially degrades satellite systems, provoking severe partial or, in some extreme cases, total failures. Electrostatic discharges (ESD), single event latch-up (SEL), and single event upsets (SEU) are among the most frequent causes of those reported satellite anomalies. The impact of space radiation dose on satellite equipment has been studied in-depth. This study conducts a statistical analysis to explore the relationships between low-Earth orbit (LEO) and geostationary orbit (GEO) satellite anomalies and particle concentrations, solar and geomagnetic activity in the period 2010–2022. Through a monthly and daily timescale analysis, the present work explores the temporal response of space disturbances on satellite systems and the periods when satellites are vulnerable to those disturbances.

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Petrov, Andrey, Alexander Nikiforov, Anna Boruzdina, Anastasia Ulanova, and Andrey Yanenko. "Memory chips and units radiation tolerance dependence on supply voltage during irradiation and test." Facta universitatis - series: Electronics and Energetics 31, no. 1 (2018): 131–40. http://dx.doi.org/10.2298/fuee1801131p.

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In this work we investigate the influence of various memory chips supply voltage on their sensitivity to the radiation environment. The main physical mechanisms responsible for radiation-induced degradation at nominal, increased, and decreased supply voltage values are discussed. It is demonstrated that, depending on supply voltage value during irradiation and subsequent testing, device's tolerance to data corruption effects in memory circuits, single event latch-up (SEL) and hard errors induced by ionizing radiation can vary significantly. We also give some recommendations to perform radiation tests.

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Zhou, Xin Jie, Jing He Wei, and Lei Lei Li. "A SEE Hardened Read-Out Circuit of EEPROM for Space Application." Applied Mechanics and Materials 198-199 (September 2012): 1105–9. http://dx.doi.org/10.4028/www.scientific.net/amm.198-199.1105.

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As wide application of EEPROM devices in space and military field, more and more researches focus on its radiation hardened characteristics in international. To improve the single-event effect (SEE) tolerant ability of read-out circuits in the memory, a radiation hardened circuit is designed. The design kernels of radiation hardened latch-flip are given and designed to resist the single-event upset (SEU) effect. A correction circuit is proposed to resist the single-event transient (SET) effect. The performances of this design are: SEU (LET)th ≥ 27 MeV•cm2/mg, SEL(LET)th ≥ 75 MeV•cm2/mg , read out time ≤200 ns. The new design not only satisfied the needs of present work, but supplies a worthful reference for radiation hardened circuit design in future.

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Datta, Mithun, Dipayan Mazumder, Alexander C. Bodoh, and Ashiq A. Sakib. "DMR-SCL: A Design and Verification Framework for Redundancy-Based Resilient Asynchronous Sleep Convention Logic Circuits." Electronics 14, no. 5 (2025): 884. https://doi.org/10.3390/electronics14050884.

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The digital integrated circuit (IC) design industry is continuously evolving. However, the rapid advancements in technology are accompanied by major reliability concerns. Conventional clock-based synchronous designs become exceedingly susceptible to transient errors, caused by radiation rays, power jitters, electromagnetic interferences (EMIs), and/or other noise sources, primarily due to aggressive device and voltage scaling. quasi-delay-insensitive (QDI) asynchronous (clockless) circuits demonstrate inherent robustness against such transient errors, owing to their unique architecture. However, they are not completely immune. This article presents a hardened QDI Sleep Convention Logic (SCL) asynchronous architecture, which can fully recover from radiation-induced single-event effects such as single-event upset (SEU) and single-event latch-up (SEL). Multiple benchmark circuits are designed based on the proposed architecture. The simulation results indicate that the proposed designs offer substantial energy savings per operation, dissipate substantially less power during idle phases, and have lower area footprints in comparison to designs based on an existing resilient Null Convention Logic (NCL) architecture at the cost of increased latency. In addition, a formal verification framework for the proposed architecture is also presented. The performance and scalability of the proposed verification scheme are demonstrated using several multiplier benchmark circuits of varying width.

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Yin-Hong, Luo, Zhang Feng-Qi, Guo Hong-Xia, et al. "Single-Event Cluster Multibit Upsets Due to Localized Latch-Up in a 90 nm COTS SRAM Containing SEL Mitigation Design." IEEE Transactions on Nuclear Science 61, no. 4 (2014): 1918–23. http://dx.doi.org/10.1109/tns.2014.2314722.

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Mazumder, Dipayan, Mithun Datta, Alexander C. Bodoh, and Ashiq A. Sakib. "A Scalable Formal Framework for the Verification and Vulnerability Analysis of Redundancy-Based Error-Resilient Null Convention Logic Asynchronous Circuits." Journal of Low Power Electronics and Applications 14, no. 1 (2024): 5. http://dx.doi.org/10.3390/jlpea14010005.

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The increasing demand for high-speed, energy-efficient, and miniaturized electronics has led to significant challenges and compromises in the domain of conventional clock-based digital designs, most notably reduced circuit reliability, particularly in mission-critical hardware. At scaled technology nodes, devices are vulnerable to transient or soft errors, such as Single Event Upset (SEU) and Single Event Latch-up (SEL). External radiation, internal electromagnetic interference (EMI), or noise are the primary sources of these errors, which can compromise the circuit functionality. In response to these challenges, the Quasi-Delay-Insensitive (QDI) Null Convention Logic (NCL) asynchronous design paradigm has emerged as a promising alternative, offering advantages such as ultra-low power performance, reduced noise and EMI, and resilience to process, voltage, and temperature variations. Moreover, its unique architecture and insensitivity to timing variations offers a degree of resistance against transient errors; however, it is not entirely resilient. Several resiliency schemes are available to detect and mitigate soft errors in QDI circuits, with approaches based on redundancy proving to be the most effective in ensuring complete resilience across all major QDI implementation paradigms, including NCL, Pre-charge/Weak-charge Half Buffers (PCHB/WCHB), and Sleep Convention Logic (SCL). This research focuses on one such redundancy-based resiliency scheme for QDI NCL circuits, known as the dual-modular redundancy-based NCL (DMR-NCL) architecture, and addresses the absence of formal methods for the verification and analysis of such circuits. A novel methodology has been proposed for formally verifying the correctness of DMR-NCL circuits synthesized from their synchronous counterparts, covering both safety (functional correctness) and liveness (the absence of deadlock). In addition, this research introduces a formal framework for the vulnerability analysis of DMR-NCL circuits against SEU/SEL. To demonstrate the framework’s efficacy and scalability, a prototype computer-aided support tool has been developed, which verifies and analyzes multiple DMR-NCL benchmark circuits of varying sizes and complexities.

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Любімов, О. В., and М. О. Любімов. "USE OF OPEN-SOURCE COTS/MOTS HARDWARE AND SOFTWARE PLATFORMS FOR THE BUILD UP OF THE CUBESAT NANOSATELLITES." Journal of Rocket-Space Technology 31, no. 4 (2023): 138–47. http://dx.doi.org/10.15421/452318.

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Abstract. CubeSats as a sub-class of nanosatellites have become a game-changer in the industry of scientific research and exploration of the new space technologies. Their cost effectiveness, relative ease of manufacturing, and the predicted lifecycle are the main factors of success. Having such popularity in mind – many vendors, student teams and enthusiast started to build their platforms to offer reuse and faster buildup of such satellites, introducing so-called COTS/MOTS approach of the satellite’s construction. However, looking into statistics – only 2.5% of the launched satellites were able to full perform their mission, and almost 25% just failed. Partially, the key problems are in the area of using non-radiation hardened electronics as the CubeSat idea is to use commercial (or at utmost automotive) components. Authors of the article provide a holistic view on the existing hardware and software platforms that are currently available as COTS/MOTS solutions, as well as their capabilities. Part of the research was done in the area of the available software frameworks, as the modern software has rather high cyclomatic complexity and often it is exactly software components that make CubeSat mission at risk. Software related frameworks are compared via the use of newly introduced by the authors multi-factor ranking model (FMCSA). At the same time the article raises the cross-country problem of the creation and use of the Ukrainian platform for the CubeSats. Authors propose a solution for the creation of the part of the CubeSat platform as the starting point and it is an On-Board Computer (OBC). The idea is to design an OBC that can solve the big portion of the known issues of the CubeSat hardware and software with the major stress on the hardware issues related to the Single-Event Upset (SEU) and Single-Event Latch Up (SEL), without moving to the radiation tolerant semiconductors. Proposed in the article solution combines the selection of the modern central processor, that is industry recognized, availability of the software solutions for it, as well as the power-domains control principle that allows to minimize the potential harm of the SEU and SEL radiation-driven events.

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Cai, Chang, Shuai Gao, Peixiong Zhao, et al. "SEE Sensitivity Evaluation for Commercial 16 nm SRAM-FPGA." Electronics 8, no. 12 (2019): 1531. http://dx.doi.org/10.3390/electronics8121531.

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Radiation effects can induce severe and diverse soft errors in digital circuits and systems. A Xilinx commercial 16 nm FinFET static random-access memory (SRAM)-based field-programmable gate array (FPGA) was selected to evaluate the radiation sensitivity and promote the space application of FinFET ultra large-scale integrated circuits (ULSI). Picosecond pulsed laser and high energy heavy ions were employed for irradiation. Before the tests, SRAM-based configure RAMs (CRAMs) were initialized and configured. The 100% embedded block RAMs (BRAMs) were utilized based on the Vivado implementation of the compiled hardware description language. No hard error was observed in both the laser and heavy-ion test. The thresholds for laser-induced single event upset (SEU) were ~3.5 nJ, and the SEU cross-sections were correlated positively to the laser’s energy. Multi-bit upsets were measured in heavy-ion and high-energy laser irradiation. Moreover, latch-up and functional interrupt phenomena were common, especially in the heavy-ion tests. The single event effect results for the 16 nm FinFET process were significant, and some radiation tolerance strategies were required in a radiation environment.

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Budroweit, Jan, Mattis Paul Jaksch, and Maciej Sznajder. "Proton Induced Single Event Effect Characterization on a Highly Integrated RF-Transceiver." Electronics 8, no. 5 (2019): 519. http://dx.doi.org/10.3390/electronics8050519.

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Radio frequency (RF) systems in space applications are usually designed for a single task and its requirements. Flexibility is mostly limited to software-defined adaption of the signal processing in digital signal processors (DSP) or field-programmable gate arrays (FPGA). RF specifications, such as frequency band selection or RF filter bandwidth are thereby restricted to the specific application requirements. New radio frequency integrated circuit (RFIC) devices also allow the software-based reconfiguration of various RF specifications. A transfer of this RFIC technology to space systems would have a massive impact to future radio systems for space applications. The benefit of this RFIC technology allows a selection of different RF radio applications, independent of their RF parameters, to be executed on a single unit and, thus, reduces the size and weight of the whole system. Since most RF application sin space system require a high level of reliability and the RFIC is not designed for the harsh environment in space, a characterization under these special environmental conditions is mandatory. In this paper, we present the single event effect (SEE) characterization of a selected RFIC device under proton irradiation. The RFIC being tested is immune to proton induced single event latch-up and other destructive events and shows a very low response to single failure interrupts. Thus, the device is defined as a good candidate for future, highly integrated radio system in space applications.

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Gevin, O., O. Limousin, F. Lugiez, et al. "IDeF-X HD: A CMOS ASIC for the Readout of Cd(Zn)Te Detectors for Space-Borne Applications." Journal of Astronomical Instrumentation 10, no. 02 (2021): 2150009. http://dx.doi.org/10.1142/s2251171721500094.

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IDeF-X HD is a 32-channel analog front-end with self-triggering capability optimized for the readout of [Formula: see text] pixels CdTe or CdZnTe pixelated detectors to build a low power micro-gamma camera. IDeF-X HD has been designed in the standard AMS CMOS 0.35[Formula: see text][Formula: see text]m process technology. Its power consumption is 800[Formula: see text][Formula: see text]W per channel. The energy range of the ASIC can be extended to 1.1[Formula: see text]MeV thanks to the in-channel adjustable gain stage. When no detector is connected to the chip and without input current, a 33 electrons rms ENC level is achieved after shaping with 10.7[Formula: see text][Formula: see text]s peaking time. Spectroscopy measurements have been performed with CdTe Schottky detectors. We measured an energy resolution of 4.2[Formula: see text]keV FWHM at 667[Formula: see text]keV ([Formula: see text]Cs) on a single-pixel configuration. Meanwhile, we also measured 562[Formula: see text]eV and 666[Formula: see text]eV FWHM at 14[Formula: see text]keV and 60[Formula: see text]keV, respectively ([Formula: see text]Am) with a 256 small pixel array and a low detection threshold of 1.2[Formula: see text]keV. Since IDeF-X HD is intended for space-borne applications in astrophysics, we evaluated its radiation tolerance and its sensitivity to single event effects. We demonstrated that the ASIC remained fully functional without significant degradation of its performances after 200 krad and that no single event latch-up was detected putting the linear energy transfer threshold above 110[Formula: see text]MeV/(mg/cm2). Good noise performance and radiation tolerance make the chip well suited for X-rays energy discrimination and high energy resolution. The chip is space qualified and flies on board of the solar orbiter ESA mission launched in 2020.

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Pujol, Jose. "An integrated 3D velocity inversion—joint hypocentral determination relocation analysis of events in the Northridge area." Bulletin of the Seismological Society of America 86, no. 1B (1996): S138—S155. http://dx.doi.org/10.1785/bssa08601bs138.

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Abstract A subset of 3371 events recorded in the Northridge area by the Southern California Seismic Network during January to April 1994 was relocated with the joint hypocentral determination (JHD) technique. This analysis showed two unexpected results: (a) the JHD locations are shifted about 3.9 km on average in a northwest direction with respect to the locations determined using a single-event location (SEL) program, and (b) the station corrections vary between −0.55 and 1.26 sec, a rather large range. In addition, the JHD locations are less scattered than the SEL locations. For each station, the weighted average of the arrival time residuals obtained when the events are located with the SEL program (which does not apply distance or error weighting) are generally smaller than the corresponding JHD corrections. The locations determined with SEL and using the weighted average residuals as station corrections do not differ much from the SEL locations, but on average the RMS residuals become as small as those corresponding to the JHD locations. As the magnitude of the station corrections indicates the presence of large lateral velocity variations, a 3D velocity model for the area was determined using the arrival times of 1012 events recorded by at least 17 stations. The initial velocity model was that used routinely by the Southern California Earthquake Center. The first two layers (5.5- and 10.5-km thick) were subdivided into 100 blocks each (12 × 12 km). These layers show a pronounced low-velocity anomaly (24% and 16%, respectively) immediately to the northwest of the epicentral area. This low-velocity zone coincides with the west Ventura Basin. Another pronounced low-velocity zone to the southeast of the epicentral area reflects the presence of the Los Angeles Basin. The locations obtained with the 3D velocity model are consistently to the southeast of the JHD locations, 2.4 km on average. To establish the effect of these pronounced lateral velocity variations on the SEL and JHD locations, synthetic travel times were analyzed. The synthetic times were generated for event locations determined by JHD (shifted by various amounts) and the 3D velocity model and were subsequently treated as the actual data. The most important result of this analysis is that the JHD locations are affected by a quasi-systematic shift in a northwest direction (up to about 2.7 km on average, depending on the initial shift) but that the relative locations are well preserved. Therefore, both the velocity inversion of the actual data and the analysis of the synthetic data indicate that the JHD locations determined for the actual data are quasi-systematically mislocated. To account for this mislocation, an overall shift of 2.5 km to the southeast was applied to all the JHD locations. One of the most important implications of the shifted locations is the possibility that the northeasterly dipping Santa Susana fault, to the northwest of the epicentral area, was seismically active during the aftershock sequence. This feature is more diffuse in other published locations.

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Chumakov, A. I., D. V. Bobrovsky, A. A. Pechenkin, D. V. Savchenkov, and G. S. Sorokoumov. "Non-Stable Single Event Latch-up." Problems of advanced micro- and nanoelectronic systems development, no. 4 (2019): 28–31. http://dx.doi.org/10.31114/2078-7707-2019-4-28-31.

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Yılmaz, Sema, Buket Kara, Bahattin Kerem Aydin, Zeliha Esin Çelik, and Yavuz Köksal. "Childhood osteosarcoma: The experience of a single center." Chronicles of Precision Medical Researchers 4, no. 2 (2023): 126–30. https://doi.org/10.5281/zenodo.7715554.

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Aim: In this study, it was aimed to evaluate the clinical features, treatment approaches and outcomes of patients with childhood osteosarcoma. Material and Method: From 2006 to 2022, the oncology files of patients with osteosarcoma diagnosed and treated at Selçuk University hospitals between 2006 and 2022 were retrospectively reviewed. Results: In this period, 24 children with osteosarcoma were included in the study. The male/female ratio was 1/1. The patients' age ranged from 7.8 to 17.2 years (median, 13.9 years). The most common site was the femur (n: 14, 58.3%). The follow-up period of the patients ranged from 9 months to 16.2 years (median, 3.15 years). Eight patients (33.4%) died with progressive disease. Overall and event-free survival rates were 58.6% ± 11.7% and 61% ± 10.2%, respectively. A negative effect of lactate dehydrogenase enzyme elevation at the time of diagnosis was observed on the overall survival rate (p=0.021). Although the overall survival rate was low in patients with metastatic disease at the time of diagnosis, the difference was not statistically significant (p=0.059). Conclusion: Survival rates similar to those in osteosarcomas with localized disease, unfortunately, still cannot be achieved in metastatic osteosarcomas, which remains a serious problem. Therefore, new treatment approaches are needed in patients with metastatic osteosarcoma.

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Tao, Rong, Chuanxu Liu, Yan Gao, et al. "Selinexor Combined with Tislelizumab in Patients with Relapsed or Refractory Extranodal NK/T-Cell Lymphoma (R/R ENKTL): Preliminary Results of Arm C, from a Multicenter, Single-Arm, Phase I/II Study, Touch." Blood 144, Supplement 1 (2024): 4448. https://doi.org/10.1182/blood-2024-206554.

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Introduction: ENKTL is a rare subtype of mature T and NK/T cell lymphoma characterized by a highly aggressive clinical course and resistance to traditional chemotherapy. The prognosis remains extremely poor for R/R ENKTL patients (pts) who fail L-Aspariginase (L-Asp) based regimens, highlighting the need for novel approaches. Check point inhibitors (CPI) including Tislelizumab (Tis) reported preliminary clinical activity in R/R ENKTL in several clinical trials. Selinexor (Sel), a novel XPO1 inhibitor, has demonstrated preclinical synergistic effects when combined with a CPI. This report aims to update the cumulative data of Arm C from Touch study (Sel plus Tis in treating R/R ENKTL). Method: Arm C was designed to evaluate the safety, tolerability, preliminary efficacy of Sel plus Tis in R/R ENKTL. Pts who received at least one prior treatment containing L-Asp were enrolled. Sel was administered orally at dose level of 40 mg QW or 60 mg QW on Days 1, 8, and 15 of each 21-day cycle. Tis was administered at a fixed dose of 200 mg every 3 weeks on Day 1. Efficacy was evaluated per Lyric 2016 by investigators. Results: As of 18 May 2024, 17 R/R ENKTL pts were enrolled in Arm C [Sel 40mg (n=3); Sel 60mg (n=14)]. At study entry, the median age was 51 years (range 20-80); Nine males and 8 females; 10 (58.8%) had stage III/IV disease; 11 (64.7%) pts had PINK score ≥2 and 9 (52.9%) pts were circular EBV-DNA positive. The median number of prior systemic treatment lines was 2 (range 1-5); sixteen pts previously exposed to both L-Asp and CPIs including 8 pts who had received prior Tis; eleven (64.7%) pts were refractory to their last-line therapy. All pts experienced at least one treatment-emergent adverse event (TEAE). The most common TEAEs were anemia, neutropenia (82.4%, respectively), asthenia (76.5%), nausea (64.7%), vomiting (58.8%), decreased appetite, weight loss (52.9%, respectively), thrombocytopenia, lymphocytopenia (47.1%, respectively), proteinuria (41.2%), pneumonia, ALT increased, hypothyroidism (29.4%, respectively). Ten pts (58.8%) experienced Grade≥3 TEAEs. TESAEs occurred in 4 pts (23.5%) with only 1 (sepsis) considered treatment related. No pt discontinued due to TEAEs. Three pts died due to disease progression before the cut-off date. Most of toxicities were manageable by dose modification and supportive care. In intent-to-treat (ITT) population, the ORR was 70.6% (12/17), the DCR was 76.5% (13/17) and CR rate was 41.2% (7/17). One pt was considered efficacy non-evaluable due to early withdraw for personal reason. Of 16 CPIs exposed pts, the ORR achieved 75% (12/16) including 7 CRs and 5 PRs. In Sel 60mg cohort, 6 CRs and 5 PRs were observed. At a median follow-up time of 10.48 months (range 4.7-17.3), the median PFS of ITTs were 6.7 months (95% CI 2.89, NE). The median DOR and OS were not reached. The estimated 6-month response rate was 56.6% (95% CI 19.7, 81.9) and the estimated 12-month OS rate was 81.9% (95% CI 53.8, 93.8). In Sel 60mg cohort, the median PFS, DOR and OS were not reached. Conclusion: The chemo-free regimen, Sel plus Tis, demonstrated a favorable response rate and manageable safety profile in R/R ENKTL. This approach may probably reverse the drug resistance in population refractory to early lines treatment with CPIs. Long-term follow-up and larger clinical trials are still needed in the future.

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Harboe-Sorensen, R. "Test methods for single event upset/latch-up." Radiation Physics and Chemistry 43, no. 1-2 (1994): 165–74. http://dx.doi.org/10.1016/0969-806x(94)90209-7.

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Chen, Rui, Jian-Wei Han, Han-Sheng Zheng, et al. "Comparative research on “high currents” induced by single event latch-up and transient-induced latch-up." Chinese Physics B 24, no. 4 (2015): 046103. http://dx.doi.org/10.1088/1674-1056/24/4/046103.

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Karp, James, Michael J. Hart, Pierre Maillard, Geert Hellings, and Dimitri Linten. "Single-Event Latch-Up: Increased Sensitivity From Planar to FinFET." IEEE Transactions on Nuclear Science 65, no. 1 (2018): 217–22. http://dx.doi.org/10.1109/tns.2017.2779831.

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Hatefinasab, Seyedehsomayeh, Noel Rodriguez, Antonio García, and Encarnacion Castillo. "Low-Cost Soft Error Robust Hardened D-Latch for CMOS Technology Circuit." Electronics 10, no. 11 (2021): 1256. http://dx.doi.org/10.3390/electronics10111256.

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In this paper, a Soft Error Hardened D-latch with improved performance is proposed, also featuring Single Event Upset (SEU) and Single Event Transient (SET) immunity. This novel D-latch can tolerate particles as charge injection in different internal nodes, as well as the input and output nodes. The performance of the new circuit has been assessed through different key parameters, such as power consumption, delay, Power-Delay Product (PDP) at various frequencies, voltage, temperature, and process variations. A set of simulations has been set up to benchmark the new proposed D-latch in comparison to previous D-latches, such as the Static D-latch, TPDICE-based D-latch, LSEH-1 and DICE D-latches. A comparison between these simulations proves that the proposed D-latch not only has a better immunity, but also features lower power consumption, delay, PDP, and area footprint. Moreover, the impact of temperature and process variations, such as aspect ratio (W/L) and threshold voltage transistor variability, on the proposed D-latch with regard to previous D-latches is investigated. Specifically, the delay and PDP of the proposed D-latch improves by 60.3% and 3.67%, respectively, when compared to the reference Static D-latch. Furthermore, the standard deviation of the threshold voltage transistor variability impact on the delay improved by 3.2%, while its impact on the power consumption improves by 9.1%. Finally, it is shown that the standard deviation of the (W/L) transistor variability on the power consumption is improved by 56.2%.

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Jiang, Jianwei, Wenyi Zhu, Jun Xiao, and Shichang Zou. "A Novel High-Performance Low-Cost Double-Upset Tolerant Latch Design." Electronics 7, no. 10 (2018): 247. http://dx.doi.org/10.3390/electronics7100247.

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Single event double upsets (SEDUs) caused by charge sharing have been an important contributor to the soft error in integrated circuits. Most of the up-to-date double-upset (DU) tolerant latches suffer from high costs in terms of delay, power and area. In this paper, we propose a novel high-performance low-cost double-upset tolerant (HLDUT) latch. Simulation waveforms have validated the double-upset tolerance of the proposed latch. Besides, detailed comparisons demonstrate that our design saves 805.24% delay-power-area product (DPAP) on average compared with other considered up-to-date double-upset tolerant latches, which means the proposed latch is a promising candidate for future highly reliable low-cost applications.

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Mai, Ziqi, Xiang Zhu, Hongwei Li, Jianwei Han, and Tao He. "Experiment Study of Single Event Functional Interrupt in Analog-to-Digital Converters Using a Pulsed Laser." Electronics 12, no. 13 (2023): 2774. http://dx.doi.org/10.3390/electronics12132774.

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Single Event Functional Interrupt (SEFI) poses a severe threat to the normal operation of spacecraft. This paper investigates SEFI in Analog-to-Digital Converters (ADCs) with storage units using precision positioning of pulsed lasers. Based on the experiment, it was discovered that a bit flip in the configuration registers in ADCs results in changes in parameters such as digital filter frequency, operating mode, and gain, leading to an upward or downward offset of ADC output codes. Similarly, a bit flip in the calibration registers also causes ADC output codes to shift upwards or downwards, or even output a value of zero. Furthermore, it was observed that SEFI phenomena can occur due to current latch-up in ADC input pins, causing the inability to read or write data in ADC storage units. This current latch-up can be resolved through power cycling or configuring the pins into a high-impedance state. This work highlights the significance of SEFI phenomena in ADCs, emphasizing the serious threat posed by storage unit flipping-induced SEFI to the proper functioning of ADCs. Moreover, the SEFI phenomenon caused by current latch-up in input pins is difficult to detect in practice, making it highly elusive. Once it occurs, it severely impacts the functionality of ADCs.

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Pilipenko, A. S., and M. I. Tikhonov. "Application of tracing tools for analysis of microcontroller failures arising under the 14 MeV neutrons exposure." Radiotehnika i èlektronika 69, no. 2 (2024): 199–204. http://dx.doi.org/10.31857/s0033849424020117.

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The trace support tools capabilities for a microcontroller (МС) with a Cortex-M3 core are analyzed to investigation of failures arising under the 14 MeV neutrons exposure. It has been shown that in most cases, MC hang is caused by the microcontroller going into a handling an inactive exception infinite loop. The cross-section values for the single event functional interrupt and the single event latch-up are estimated.

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Li, Dongqing, Tianqi Liu, Zhenyu Wu, et al. "An investigation of FinFET single-event latch-up characteristic and mitigation method." Microelectronics Reliability 114 (November 2020): 113901. http://dx.doi.org/10.1016/j.microrel.2020.113901.

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Tomioka, Takahiro, Yuta Okumura, Hirokazu Masui, Koichi Takamiya, and Mengu Cho. "Screening of nanosatellite microprocessors using californium single-event latch-up test results." Acta Astronautica 126 (September 2016): 334–41. http://dx.doi.org/10.1016/j.actaastro.2016.05.004.

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Park, Jung-Jin, Young-Min Kang, Geon-Hak Kim, Ik-Joon Chang, and Jinsang Kim. "A Fully Polarity-Aware Double-Node-Upset-Resilient Latch Design." Electronics 11, no. 15 (2022): 2465. http://dx.doi.org/10.3390/electronics11152465.

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Due to aggressive scaling down, multiple-node-upset hardened design has become a major concern regarding radiation hardening. The proposed latch overcomes the architecture and performance limitations of state-of-the-art double-node-upset (DNU)-resilient latches. A novel stacked latch element is developed with multiple thresholds, regular architecture, increased number of single-event upset (SEU)-insensitive nodes, low power dissipation, and high robustness. The radiation-aware layout considering layout-level issues is also proposed. Compared with state-of-the-art DNU-resilient latches, simulation results show that the proposed latch exhibits up to 92% delay and 80% power reduction in data activity ratio (DAR) of 100%. The radiation simulation using the dual-double exponential current source model shows that the proposed latch has the strongest radiation-hardening capability among the other DNU-resilient latches.

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Chen Rui, 陈睿, 余永涛 Yu Yongtao, 董刚 Dong Gang, et al. "Single event latch-up effect and mitigation technique in different sized CMOS devices." High Power Laser and Particle Beams 26, no. 7 (2014): 74005. http://dx.doi.org/10.3788/hplpb20142607.74005.

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Umesh, S. B., S. R. Kulkarni, R. Sandhya, G. R. Joshi, R. Damle, and M. Ravindra. "High-energy heavy ion testing of VLSI devices for single event upsets and latch up." Bulletin of Materials Science 28, no. 5 (2005): 473–76. http://dx.doi.org/10.1007/bf02711239.

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Coronetti, Andrea, Ruben Garcia Alia, Francesco Cerutti, et al. "The Pion Single-Event Latch-Up Cross Section Enhancement: Mechanisms and Consequences for Accelerator Hardness Assurance." IEEE Transactions on Nuclear Science 68, no. 8 (2021): 1613–22. http://dx.doi.org/10.1109/tns.2021.3070216.

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LI Sai, CHEN Rui, HAN Jianwei, SHANGGUAN Shipeng, and MA Yingqi. "Single Event Latch-up Effect of 130 nm Bulk Silicon CMOS Device Irradiated by Pulsed Laser." Chinese Journal of Space Science 41, no. 4 (2021): 648. http://dx.doi.org/10.11728/cjss2021.04.648.

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Badugu, Divya Madhuri, Sunithamani S., Javid Basha Shaik, and Ramesh Kumar Vobulapuram. "Design of hardened flip-flop using Schmitt trigger-based SEM latch in CNTFET technology." Circuit World 47, no. 1 (2020): 51–59. http://dx.doi.org/10.1108/cw-10-2019-0141.

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Purpose The purpose of this paper is to design novel hardened flip-flop using carbon nanotube field effect transistors (CNTFETs). Design/methodology/approach To design the proposed flip-flop, the Schmitt trigger-based soft error masking and unhardened latches have been used. In the proposed design, the novel mechanism, i.e. hysteresis property is used to enhance the hardness of the single event upset. Findings To obtain the simulation results, all the proposed circuits are extensively simulated in Hewlett simulation program with integrated circuit emphasis software. Moreover, the results of the proposed latches are compared to the conventional latches to show performance improvements. It is noted that the proposed latch shows the performance improvements up to 25.8%, 51.2% and 17.8%, respectively, in terms of power consumption, area and power delay product compared to the conventional latches. Additionally, it is observed that the simulation result of the proposed flip-flop confirmed the correctness with its respective functions. Originality/value The novel hardened flip-flop utilizing ST based SEM latch is presented. This flip-flop is significantly improves the performance and reliability compared to the existing flip-flops.

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Li, Pengwei, Xiaoyun Fu, Lei Luo, and Qingkui Yu. "A New Analyzing Method of Single Event Latch-Up Protection Circuit Based on Current Comparing and Its Performance Verification." Journal of Modern Physics 05, no. 06 (2014): 387–93. http://dx.doi.org/10.4236/jmp.2014.56050.

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Rezzak, Nadia, and Jih-Jong Wang. "Single Event Latch-Up Hardening Using TCAD Simulations in 130 nm and 65 nm Embedded SRAM in Flash-Based FPGAs." IEEE Transactions on Nuclear Science 62, no. 4 (2015): 1599–608. http://dx.doi.org/10.1109/tns.2015.2450210.

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Wang, Chen, Yi Liu, Changqing Xu, Xinfang Liao, Dongdong Chen, and Zhenyu Wu. "Research on Temperature Dependence of Single-Event Burnout in Power MOSFETs." Micromachines 14, no. 5 (2023): 1028. http://dx.doi.org/10.3390/mi14051028.

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Power MOSFETs are found to be very vulnerable to single-event burnout (SEB) in space irradiation environments, and the military components generally require that devices could operate reliably as the temperature varies from 218 K to 423 K (−55 °C to 150 °C); thus, the temperature dependence of single-event burnout (SEB) in power MOSFETs should be investigated. Our simulation results showed that the Si power MOSFETs are more tolerant to SEB at a higher temperature at the lower LET (10 MeV∙cm2/mg) due to the decrease of the impact ionization rate, which is in good agreement with the previous research. However, the state of the parasitic BJT plays a primary role in the SEB failure mechanism when the LET value is greater than 40 MeV∙cm2/mg, which exhibits a completely different temperature dependence from that of 10 MeV∙cm2/mg. Results indicate that with the temperature increasing, the lower difficulty to turn on the parasitic BJT and the increasing current gain all make it easier to build up the regenerative feedback process responsible for SEB failure. As a result, the SEB susceptibility of power MOSFETs increases as ambient temperature increases when the LET value is greater than 40 MeV∙cm2/mg.

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Laštovička-Medin, G., G. Kramberger, M. Rebarz, et al. "New insight into gain suppression and single event Burnout effects in LGAD." Journal of Instrumentation 18, no. 02 (2023): C02059. http://dx.doi.org/10.1088/1748-0221/18/02/c02059.

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Abstract Low Gain Avalanche Detectors (LGADs) will be employed in the CMS MTD and ATLAS HGTD upgrades to mitigate the high levels of pile-up events expected in the High Luminosity phase of the LHC. Over the last several years, much attention has been focused on designing radiation-tolerant gain implants to ensure that these sensors survive the expected fluence (>1015 neq/cm2). This work reports several effects observed during our previous studies on two relevant phenomena Single Event Burnout (SEB) and carrier density-induced Gain Suppression (GS). Influence of irradiation level, pad configuration and gain layer depth on SEB are discussed. In this paper, we also extend GS study with a new insight into the spatio-temporal dynamics of charge transport in LGAD, probed with a focused ion beam.

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Yang, Guoqing, Jizuo Zhang, Jincheng Zhang, Xiangyuan Liu, and Yimin Yang. "Characterization of Single Event Effect in a Radiation Hardened Programmable Read-Only Memory in a 130 nm Bulk CMOS Technology." Journal of Nanoelectronics and Optoelectronics 18, no. 11 (2023): 1284–95. http://dx.doi.org/10.1166/jno.2023.3511.

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The concept of memory that can only be read but cannot be changed seems strange at first. In reality, it is found that it has great application potential, such as the processor with a fixed purpose, the initial set value of the microprocessor BIOS, and these data are stored in Programmable Read-Only Memory (PROM) to quickly realize system functions. The PROM storage content is fixed, greatly simplifying his design. The radiation of space particles is the main factor causing the failure of the electronic system of spacecraft. The PROM storage array of the space electronic system is the most basic guarantee for the normal operation of the electronic system. The chip adopts domestic 130 nm standard technology of Complementary Metal Oxide Semiconductor (CMOS), Muller-C digital filter is used in the peripheral subsystem of PROM storage array, and the core cell uses Dual Interlocked Cell (DICE) and ring gate and other radiation hardening technologies to design a 32Kx8bit radiation resistant asynchronous programmable PROM. Pre-silicon of devices was verified by Technology Computer Aided Design (TCAD), and post silicon radiation verification was completed through radiation experiment. The post silicon radiation experiment showed that the total ionizing Dose (TID) capacity of the PROM chip was ≥100 Krad (Si), the critical value of single event upset (SEU) was ≥37.1 MeV·cm2/mg, the critical value of single event latch up was ≥98 MeV·cm2/mg, meeting the life requirements of the initial value storage of aerospace electronic systems. These performances ensure the reliable operation of the space electronic system after restart.

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Mehmood, Maria, Sajid Saleem, and Renato Filjar. "Eyjafjallajökull Volcanic Ash 2010 Effects on GPS Positioning Performance in the Adriatic Sea Region." Atmosphere 13, no. 1 (2021): 47. http://dx.doi.org/10.3390/atmos13010047.

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The Eyjafjallajökull volcanic ash crisis in 2010 temporarily suspended European air traffic operations, as the 39-day eruption caused widely dispersed ashes to enter the lower atmosphere. In this paper, we assessed the effects of this event on the ionosphere layer and, consequently, on GPS positioning. We collected and analysed the data from four IGS stations, nearest to the volcano, for the month of April 2010. We recorded Vertical Total Electron Content (VTEC) time series, analysed their dynamics, and compared them with the GPS positioning errors of a commercial-grade, un-aided, single-frequency GPS receiver (simulating the response of a mass-market GPS receiver). The geomagnetic indices during the time period show little geomagnetic disturbance, especially during the volcanic event. Our results show an enhancement in ionosphere error by up to 15% during the volcanic ash event and an enhanced variance in GPS position components errors. This study reveals the potential impact of the charged volcanic ash on single-frequency, unaided GPS positioning accuracy in the Adriatic Sea region and establishes a foundation for studying similar events in future.

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Ferlini, Frederico, Felipe Viel, Laio Oriel Seman, Hector Pettenghi, Eduardo Augusto Bezerra, and Valderi Reis Quietinho Leithardt. "A Methodology for Accelerating FPGA Fault Injection Campaign Using ICAP." Electronics 12, no. 4 (2023): 807. http://dx.doi.org/10.3390/electronics12040807.

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The increasing complexity of System-on-Chip (SoC) and the ongoing technology miniaturization on Integrated Circuit (IC) manufacturing processes makes modern SoCs more susceptible to Single-Event Effects (SEE) caused by radiation, even at sea level. To provide realistic estimates at a low cost, efficient analysis techniques capable of replicating SEEs are required. Among these methods, fault injection through emulation using Field-Programmable Gate Array (FPGA) enables campaigns to be run on a Circuit Under Test (CUT). This paper investigates the use of an FPGA architecture to speed up the execution of fault campaigns. As a result, a new methodology for mapping the CUT occupation on the FPGA is proposed, significantly reducing the total number of faults to be injected. In addition, a fault injection technique/flow is proposed to demonstrate the benefits of cutting-edge approaches. The presented technique emulates Single-Event Transient (SET) in all combinatorial elements of the CUT using the Internal Configuration Access Port (ICAP) of Xilinx FPGAs.

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Sonesson, Göran. "Translation as culture: The example of pictorial-verbal transposition in Sahagún’s primeros memoriales and codex florentino." Semiotica 2020, no. 232 (2020): 5–39. http://dx.doi.org/10.1515/sem-2019-0044.

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AbstractMany items of culture which are conveyed from one culture to another may take verbal form, and then constitute what Jakobson called “translation proper.” If such diffusions involve a co-occurrent change of semiotic systems, they are of such a different nature, that we better reserve another term for it: transposition. Whether or not accompanied by transpositions, such as pictures, translational events may play an important part in the encounter between cultures, not only in the negative sense of deformations as postulated by the Tartu school. Particularly, when such transpositions make up a massive occurrence, as was the assimilation of the Greek-Muslim heritage in Middle Age Europe, or the more extended process by means of which Europe took on of the experience of the so-called New World several centuries later, such processes may actually enrich the homeculture. In this paper, we will study the latter process, zeroing in on a single, if protracted, event, the creation of the work ascribed to Bernardino de Sahagún, which really involved the collaboration of many scholars, many of them bearers of Aztec culture, exclusively or in combination with Western culture. This case interests us in particular, also because it involved the transposition of pictures, not, in the sense, of Western pictures being substitued for single pre-Hispanic picture, but rather as a kind of semiotic means contributing in different ways to the process of constitution.

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Durand, Cédric, and Sébastien Villemot. "Balance sheets after the EMU: an assessment of the redenomination risk." Socio-Economic Review 18, no. 2 (2018): 367–94. http://dx.doi.org/10.1093/ser/mwy004.

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Abstract The probability of a partial or complete break-up of the euro has risen over the last years. Such an event could create a balance sheet problem for economic agents, if the redenomination process introduced significant currency mismatches between the asset and liability sides. We propose a new assessment of this redenomination risk, by country and by main institutional sector, for two scenarios: a single country exit and a complete break-up. Our main conclusion is that, even though the problem has to be taken seriously, its order of magnitude should not be exaggerated. Only a few sectors are at significant risk: public debts of Greece and Portugal, financial sectors of Greece, Ireland and Luxembourg. In particular, the balance sheet exposure of the non-financial private sector to the redenomination risk appears to be limited.

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Wang, Yue, Lixin Wang, Yuanzhe Li, Mengyao Cui, and Zhuoxuan Zheng. "A Single-Event Burnout Hardened Super-Junction Trench SOI LDMOS with Additional Hole Leakage Paths." Electronics 11, no. 22 (2022): 3764. http://dx.doi.org/10.3390/electronics11223764.

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In this paper, a novel super-junction trench silicon-on-insulator laterally-diffused metal-oxide-semiconductor (SJT SOI LDMOS) power device with additional hole leakage paths to improve single-event burnout (SEB) performance under high liner energy transfer (LET) is proposed for the first time. The electrical characteristics and SEB performance of the proposed SJT SOI LDMOS are both enhanced effectively. The replacement of a lightly doped N drift region with a heavily doped P pillar and N pillar considerably improves the tradeoff between breakdown voltage (BVDS) and specific on-resistance (Ron,sp). Compared with the conventional trench SOI LDMOS (CT SOI LDMOS), the static figures of merit (FOM, BVDS2/Ron,sp) of the SJT SOI LDMOS increases by 239%. The SEB performance of the SJT SOI LDMOS is significantly improved as the holes induced by the heavy ion can be quickly absorbed to the trench source metal through the heavily doped P+ region and P buried region rather than the base resistor of the parasitic bipolar junction transistor (BJT). The SEB threshold voltage (VSEB) of the CT SOI LDMOS is 58 V (39% of the BVDS) and that of the SJT SOI LDMOS is up to 173 V (87% of the BVDS) at high LET of 1 pC/μm.

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De Biasio, F., M. M. Miglietta, S. Zecchetto, and A. della Valle. "Numerical models sea surface wind compared to scatterometer observations for a single Bora event in the Adriatic Sea." Advances in Science and Research 11, no. 1 (2014): 41–48. http://dx.doi.org/10.5194/asr-11-41-2014.

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Abstract. We compare the sea surface wind fields forecasted by a Global Circulation Model (GCM) and three Limited Area Models (LAMs) in an operational-like set-up, with the wind remotely sensed by the NASA QuikSCAT scatterometer. The comparison is performed for a single case of Bora wind in the Adriatic Sea, with the purpose to understand the ability of the model forecasts in reproducing the mesoscale features captured by the scatterometer, and to investigate on the suitability of LAM and GCM forecasts as possible forcing in storm surge models (SSMs). The performance is evaluated by means of statistical parameters regarding wind speed and direction showing that, at least in terms of classical statistical parameters, the GCM offer the most advantageous choice in terms of cost/benefit.

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Laštovička-Medin, G., G. Kramberger, M. Rebarz, et al. "A brief overview of the studies on the irreversible breakdown of LGAD testing samples irradiated at the critical LHC-HL fluences." Journal of Instrumentation 17, no. 07 (2022): C07020. http://dx.doi.org/10.1088/1748-0221/17/07/c07020.

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Abstract LGAD sensors will be employed in the CMS MTD and ATLAS HGTD upgrades to mitigate the high levels of pile-up expected in the High Luminosity phase of the LHC. Over the last several years, much attention has been focused on designing radiation tolerant gain implants to ensure that these sensors survive the expected fluences, (more than 1–2 × 1015 neq/cm2). However, in test beams with protons and a fs-laser, highly irradiated LGADs operated at a high voltage, have been seen to exhibit violent burn-out events that render the sensors inoperable. This paper will focus on the critical electric field and accordingly the bias thresholds to mitigate the risk of Single Event Burnout (SEB).

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Frauen, Claudia, Dietmar Dommenget, Nicholas Tyrrell, Michael Rezny, and Scott Wales. "Analysis of the Nonlinearity of El Niño–Southern Oscillation Teleconnections*." Journal of Climate 27, no. 16 (2014): 6225–44. http://dx.doi.org/10.1175/jcli-d-13-00757.1.

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Abstract El Niño–Southern Oscillation (ENSO) has significant variations and nonlinearities in its pattern and strength. ENSO events vary in their position along the equator, with some located in the central Pacific (CP) and others in the east Pacific (EP). To study how these variations are reflected in global ENSO teleconnections, both observations and idealized atmospheric general circulation model (AGCM) simulations are analyzed. Clear nonlinearities exist in observed teleconnections of sea level pressure (SLP) and precipitation. However, it is difficult to distinguish if these are caused by the different signs, strengths, or spatial patterns of events (strong El Niño events mostly being EP events and strong La Niña events mostly being CP events) or by combinations of these. Therefore, sensitivity experiments are performed with an AGCM forced with idealized EP and CP ENSO sea surface temperature (SST) patterns with varying signs and strengths. The response is generally stronger for warm events than for cold events and the teleconnection patterns vary with changing SST anomaly patterns. EP events show stronger nonlinearities than CP events. The nonlinear responses to ENSO events can be explained as a combination of nonlinear responses to a linear ENSO (fixed pattern but varying signs and strengths) and a linear response to a nonlinear ENSO (varying patterns). Any observed event is a combination of these aspects. While in most tropical regions these add up, leading to stronger nonlinear responses than expected from the single components, in some regions they cancel each other, resulting in little overall nonlinearity. This leads to strong regional differences in ENSO teleconnections.

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Budroweit, Jan, Mattis Jaksch, Rubén Garcia Alía, Andrea Coronetti, and Alexander Kölpin. "Heavy Ion Induced Single Event Effects Characterization on an RF-Agile Transceiver for Flexible Multi-Band Radio Systems in NewSpace Avionics." Aerospace 7, no. 2 (2020): 14. http://dx.doi.org/10.3390/aerospace7020014.

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Nowadays, technologies have a massive impact on the design of avionic systems, even for the conservative space industry. In this paper, the single event effect (SEE) characterization of a highly integrated and radio frequency (RF) agile transceiver is being presented which is an outstanding candidate for future radio systems in NewSpace applications and space avionics. The device being investigated allows programmable re-configuration of RF specifications, where classical software-defined radios (SDR) only define an on-demand re-configuration of the signal processing. RF related configurations are untouched for common SDR and developed discretely by the specific application requirements. Due to the high integrity and complexity of the device under test (DUT), state-of-the-art radiation test procedures are not applicable and customized testing procedures need to be developed. The DUT shows a very robust response to linear energy transfer (LET) values up to 62.5 MeV.cm²/mg, without any destructives events and a moderate soft error rate.

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Yevick, David, and Yong Hwan Lee. "Accelerated rare event sampling: Refinement and Ising model analysis." International Journal of Modern Physics C 28, no. 01 (2017): 1750012. http://dx.doi.org/10.1142/s0129183117500127.

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In this paper, a recently introduced accelerated sampling technique [D. Yevick, Int. J. Mod. Phys. C 27, 1650041 (2016)] for constructing transition matrices is further developed and applied to a two-dimensional [Formula: see text] Ising spin system. By permitting backward displacements up to a certain limit for each forward step while evolving the system to first higher and then lower energies within a restricted interval that is steadily displaced toward zero temperature as the computation proceeds, accuracy can be greatly enhanced. Simultaneously, the elements obtained from numerous independent calculations are collected in a single transition matrix. The relative accuracy of this novel method is established through a comparison to a transition matrix procedure based on the Metropolis algorithm in which the temperature is appropriately varied during the calculation and the results interpreted in terms of the distribution of realizations over both energy and magnetization.

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