Relevant bibliographies by topics / SPARC (Scalable Processor ARChitecture)

Contents

  1. Journal articles

Academic literature on the topic 'SPARC (Scalable Processor ARChitecture)'

Author: Grafiati
Published: 4 June 2021
Last updated: 9 February 2022

Create a spot-on reference in APA, MLA, Chicago, Harvard, and other styles

Select a source type:

Consult the lists of relevant articles, books, theses, conference reports, and other scholarly sources on the topic 'SPARC (Scalable Processor ARChitecture).'

Next to every source in the list of references, there is an 'Add to bibliography' button. Press on it, and we will generate automatically the bibliographic reference to the chosen work in the citation style you need: APA, MLA, Harvard, Chicago, Vancouver, etc.

You can also download the full text of the academic publication as pdf and read online its abstract whenever available in the metadata.

Journal articles on the topic "SPARC (Scalable Processor ARChitecture)"

1

Agrawal, Anant, and Robert B. Garner. "SPARC: A scalable processor architecture." Future Generation Computer Systems 7, no. 2-3 (1992): 303–9. http://dx.doi.org/10.1016/0167-739x(92)90017-6.

Full text
APA, Harvard, Vancouver, ISO, and other styles
2

Kongetira, P., K. Aingaran, and K. Olukotun. "Niagara: A 32-Way Multithreaded Sparc Processor." IEEE Micro 25, no. 2 (2005): 21–29. http://dx.doi.org/10.1109/mm.2005.35.

Full text
APA, Harvard, Vancouver, ISO, and other styles
3

Lee, Roland L., Alex Y. Kwok, and Fayé A. Briggs. "The floating point performance of a superscalar SPARC processor." ACM SIGOPS Operating Systems Review 25, Special Issue (1991): 28–37. http://dx.doi.org/10.1145/106974.106978.

Full text
APA, Harvard, Vancouver, ISO, and other styles
4

Becker, J., and A. Thomas. "Scalable Processor Instruction Set Extension." IEEE Design and Test of Computers 22, no. 2 (2005): 136–48. http://dx.doi.org/10.1109/mdt.2005.43.

Full text
APA, Harvard, Vancouver, ISO, and other styles
5

CHOI, M., and S. MAENG. "An Energy Efficient Instruction Window for Scalable Processor Architecture." IEICE Transactions on Electronics E91-C, no. 9 (2008): 1427–36. http://dx.doi.org/10.1093/ietele/e91-c.9.1427.

Full text
APA, Harvard, Vancouver, ISO, and other styles
6

Buchenrieder, K., R. Kress, A. Pyttel, A. Sedlmeier, and C. Veith. "Scalable processor architecture for Java with explicit thread support." Electronics Letters 33, no. 18 (1997): 1532. http://dx.doi.org/10.1049/el:19971049.

Full text
APA, Harvard, Vancouver, ISO, and other styles
7

Mao-Yin Wang and Cheng-Wen Wu. "A Mesh-Structured Scalable IPsec Processor." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 18, no. 5 (2010): 725–31. http://dx.doi.org/10.1109/tvlsi.2009.2016102.

Full text
APA, Harvard, Vancouver, ISO, and other styles
8

Ibrahim, Atef. "Scalable digit-serial processor array architecture for finite field division." Microelectronics Journal 85 (March 2019): 83–91. http://dx.doi.org/10.1016/j.mejo.2019.01.011.

Full text
APA, Harvard, Vancouver, ISO, and other styles
9

Mandolesi, P. S., P. Julian, and A. G. Andreou. "A Scalable and Programmable Simplicial CNN Digital Pixel Processor Architecture." IEEE Transactions on Circuits and Systems I: Regular Papers 51, no. 5 (2004): 988–96. http://dx.doi.org/10.1109/tcsi.2004.827626.

Full text
APA, Harvard, Vancouver, ISO, and other styles
10

Feehrer, John, Sumti Jairath, Paul Loewenstein, et al. "The Oracle Sparc T5 16-Core Processor Scales to Eight Sockets." IEEE Micro 33, no. 2 (2013): 48–57. http://dx.doi.org/10.1109/mm.2013.49.

Full text
APA, Harvard, Vancouver, ISO, and other styles
More sources
You might also be interested in the extended bibliographies on the topic 'SPARC (Scalable Processor ARChitecture)' for particular source types:
Journal articles
We offer discounts on all premium plans for authors whose works are included in thematic literature selections. Contact us to get a unique promo code!

To the bibliography