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Harter, Andrew Charles. "Three-dimensional integrated circuit layout." Thesis, University of Cambridge, 1990. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.335724.
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Megas, Dimitrios, and Kleber Leandro Pizolato Someira. "Data Transformation in a Three Dimensional Integrated Circuit Implementation." Thesis, Monterey, California. Naval Postgraduate School, 2012. http://hdl.handle.net/10945/6834.
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Three-dimensional integration is an emerging chip fabrication technique in which multiple integrated circuit dies are joined using conductive posts. 3D integration offers several performance and security advantages, including extremely high bandwidth between the two dies and the ability to augment a processor with a separate die housing custom security features. This thesis performs a feasibility and requirements analysis of a data transformation coprocessor in a three-dimensional integrated circuit. We propose a novel coprocessor architecture in which one layer (control layer) houses application-specific coprocessors for cryptography and compression, which provide acceleration for applications running on a general-purpose processor in another layer (computational layer). The main application supported from our proposed 3DIC is the one that performs real-time trace collection, compresses the trace, and optionally encrypts the compressed trace, which protects the data from interception during transmission to permanent off-chip storage for offline program analysis. Although we are not building a hardware device for simulation we present the architecture for a 3D data transformation processor and a rationale for each of the key design decisions, including a compression study that determined the optimal compression algorithm for a specific set of traces.
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Joyner, James W. "Opportunities and limitations of three-dimensional integration for interconnect design." Diss., Georgia Institute of Technology, 2003. http://hdl.handle.net/1853/13763.
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Pine, Shannon Robert. "Manufacturing structurally integrated three dimensional phased array antennas." Thesis, Available online, Georgia Institute of Technology, 2006, 2006. http://etd.gatech.edu/theses/available/etd-04062006-115019/.
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Thesis (M. S.)--Mechanical Engineering, Georgia Institute of Technology, 2006.<br>Dr. Jonathan Colton, Committee Chair ; Dr. John Muzzy, Committee Member ; Dr. Daniel Baldwin, Committee Member ; Dr. John Schultz, Committee Member.
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Zaveri, Jesal. "Electrical and fluidic interconnect design and technology for 3D ICS." Thesis, Georgia Institute of Technology, 2011. http://hdl.handle.net/1853/39550.
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For decades, advances in device scaling has proven to be critical in improving the performance and productivity of 2D systems. In this thesis, we explore how advances in technology have pushed functional integration to such a high-level that interconnection and packaging issues represent real barriers to further progress. While three-dimensional (3D) integration offers to be a potential contender to overcome the barriers of increased energy consumption due to interconnects and bandwidth limitations, there are certain challenges that must be overcome before systems can be successfully stacked. Cooling and power delivery are among these key challenges in the integration of high performance 3D ICs. To address these challenges, microchannel heat sinks for inter-stratum cooling and through-silicon vias (TSVs) for signaling and power delivery between stacked ICs were explored. Novel integration schemes to integrate these uidic and electrical interconnects in conventional CMOS processes were also explored. Compact physical modeling was utilized to understand the trade-offs involved in the integration of electrical and microfluidic interconnects in a 3D IC stack. These concepts were demonstrated experimentally by showing different CMOS compatible methods of fabricating microchannels and integration of high aspect ratio (~20:1) and high density (200,000/cm²) electrical TSVs in the fins of the microchannels for signaling and power delivery. A novel mesh process for bottom up plating of high aspect ratio TSVs is also shown in this work. Fluidic reliability measurements are shown to demonstrate the feasibility of this technology. This work also demonstrates the design and fabrication of a 3D testbed which consists of a 2 chip stack with microchannel cooling on each level. Preliminary testing of the stack along with interlayer electro-fluidic I/Os has also been demonstrated.
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Xie, Jianyong. "Electrical-thermal modeling and simulation for three-dimensional integrated systems." Diss., Georgia Institute of Technology, 2013. http://hdl.handle.net/1853/50307.
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The continuous miniaturization of electronic systems using the three-dimensional (3D) integration technique has brought in new challenges for the computer-aided design and modeling of 3D integrated circuits (ICs) and systems. The major challenges for the modeling and analysis of 3D integrated systems mainly stem from four aspects: (a) the interaction between the electrical and thermal domains in an integrated system, (b) the increasing modeling complexity arising from 3D systems requires the development of multiscale techniques for the modeling and analysis of DC voltage drop, thermal gradients, and electromagnetic behaviors, (c) efficient modeling of microfluidic cooling, and (d) the demand of performing fast thermal simulation with varying design parameters. Addressing these challenges for the electrical/thermal modeling and analysis of 3D systems necessitates the development of novel numerical modeling methods.
This dissertation mainly focuses on developing efficient electrical and thermal numerical modeling and co-simulation methods for 3D integrated systems. The developed numerical methods can be classified into three categories. The first category aims to investigate the interaction between electrical and thermal characteristics for power delivery networks (PDNs) in steady state and the thermal effect on characteristics of through-silicon via (TSV) arrays at high frequencies. The steady-state electrical-thermal interaction for PDNs is addressed by developing a voltage drop-thermal co-simulation method while the thermal effect on TSV characteristics is studied by proposing a thermal-electrical analysis approach for TSV arrays.
The second category of numerical methods focuses on developing multiscale modeling approaches for the voltage drop and thermal analysis. A multiscale modeling method based on the finite-element non-conformal domain decomposition technique has been developed for the voltage drop and thermal analysis of 3D systems. The proposed method allows the modeling of a 3D multiscale system using independent mesh grids in sub-domains. As a result, the system unknowns can be greatly reduced. In addition, to improve the simulation efficiency, the cascadic multigrid solving approach has been adopted for the voltage drop-thermal co-simulation with a large number of unknowns.
The focus of the last category is to develop fast thermal simulation methods using compact models and model order reduction (MOR). To overcome the computational cost using the computational fluid dynamics simulation, a finite-volume compact thermal model has been developed for the microchannel-based fluidic cooling. This compact thermal model enables the fast thermal simulation of 3D ICs with a large number of microchannels for early-stage design. In addition, a system-level thermal modeling method using domain decomposition and model order reduction is developed for both the steady-state and transient thermal analysis. The proposed approach can efficiently support thermal modeling with varying design parameters without using parameterized MOR techniques.
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Dilli, Zeynep. "Physical aspects of VLSI design with a focus on three-dimensional integrated circuit applications." College Park, Md.: University of Maryland, 2007. http://hdl.handle.net/1903/7717.
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Thesis (Ph. D.) -- University of Maryland, College Park, 2007.<br>Thesis research directed by: Dept. of Electrical and Computer Engineering. Title from t.p. of PDF. Includes bibliographical references. Published by UMI Dissertation Services, Ann Arbor, Mich. Also available in paper.
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Cho, Minki. "Design methodology to characterize and compensate for process and temperature variation in digital systems." Diss., Georgia Institute of Technology, 2012. http://hdl.handle.net/1853/50148.
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The main objective of this dissertation is to investigate a design methodology that can characterize and compensate for process and temperature variation. First, a design methodology is discussed to handle process variation in low-power memory for image processing application. This is followed by a design technique to characterize and recover TSV-defect-induced signal degradation in a 3D integrated circuit. For thermal variation, the spatiotemporal power migration is proposed as a methodology to handle thermal issues in digital systems both during the test and normal operation. The power migration continuously distributes the generated heat in space and time to control chip temperature. To enable this approach a unique method is developed, and verified through hardware for post-fabrication characterization of thermal system and prediction of transient variation in chip temperature. The inverse temperature dependence in a digital logic is characterized through hardware to help better thermal management in wide operating voltage design.
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Han, Ki Jin. "Electromagnetic modeling of interconnections in three-dimensional integration." Diss., Atlanta, Ga. : Georgia Institute of Technology, 2009. http://hdl.handle.net/1853/29642.
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Thesis (Ph.D)--Electrical and Computer Engineering, Georgia Institute of Technology, 2009.<br>Committee Chair: Madhavan Swaminathan; Committee Member: Andrew E. Peterson; Committee Member: Emmanouil M. Tentzeris; Committee Member: Hao-Min Zhou; Committee Member: Saibal Mukhopadhyay. Part of the SMARTech Electronic Thesis and Dissertation Collection.
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Xu, Yuanzhe, and 徐远哲. "Variational analysis for 3D integrated circuit on-chip structures based on process-variation-aware electromagnetic-semiconductor coupledsimulation." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 2011. http://hub.hku.hk/bib/B47047616.
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Ahmed, Mohammad Abrar. "Early Layout Design Exploration in TSV-based 3D Integrated Circuits." PDXScholar, 2017. https://pdxscholar.library.pdx.edu/open_access_etds/3617.
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Through silicon via (TSV) based 3D integrated circuits have inspired a novel design paradigm which explores the vertical dimension, in order to alleviate the performance and power limitations associated with long interconnects in 2D circuits. TSVs enable vertical interconnects across stacked and thinned dies in 3D-IC designs, resulting in reduced wirelength, footprint, faster speed, improved bandwidth, and lesser routing congestion. However, the usage of TSVs itself gives rise to many critical design challenges towards the minimization of chip delay and power consumption. Therefore, realization of the benefits of 3D ICs necessitates an early and realistic prediction of circuit performance during the early layout design stage.
The goal of this thesis is to meet the design challenges of 3D ICs by providing new capabilities to the existing floorplanning framework [87]. The additional capabilities included in the existing floorplanning tool is the co-placement of TSV islands with circuit blocks and performing non-deterministic assignment of signals to TSVs. We also replace the wirelength and number of TSVs in the floorplanning cost function with the total delay in the nets. The delay-aware cost function accounts for RC delay impact of TSVs on the delay of individual signal connection, and obviates the efforts required to balance the weight contributions of wirelength and TSVs in the wirelength-aware floorplanning. Our floorplanning tool results in 5% shorter wirelength and 21% lesser TSVs compared to recent approaches. The delay in the cost function improves total delay in the interconnects by 10% - 12% compared to wirelength-aware cost function.
The influence of large coupling capacitance between TSVs on the delay, power and coupling noise in 3D interconnects also offers serious challenges to the performance of 3D-IC. Due to the degree of design complexity introduced by TSVs in 3D ICs, the importance of early stage evaluation and optimization of delay, power and signal integrity of 3D circuits cannot be ignored. The unique contribution of this work is to develop methods for accurate analysis of timing, power and coupling noise across multiple stacked device layers during the floorplanning stage. Incorporating the impact of TSV and the stacking of multiple device layers within floorplanning framework will help to achieve 3D layouts with superior performance.
Therefore, we proposed an efficient TSV coupling noise model to evaluate the coupling noise in the 3D interconnects during floorplanning. The total coupling noise in 3D interconnects is included in the cost function to optimize positions of TSVs and blocks, as well as nets-to-TSVs assignment to obtain floorplans with minimized coupling noise. We also suggested diagonal TSV arrangement for larger TSV pitch and nonuniform pitch arrangement for reducing worst TSV-to-TSV coupling, thereby minimizing the coupling noise in the interconnects.
This thesis also focuses on more realistic evaluation and optimization of delay and power in TSV based 3D integrated circuits considering the interconnect density on individual device layers. The floorplanning tool uses TSV locations and delay, non-uniform interconnect density across multiple stacked device layers to assess and optimize the buffer count, delay, and interconnect power dissipation in a design. It is shown that the impact of non-uniform interconnect density, across the stacked device layers, should not be ignored, as its contribution to the performance of the 3D interconnects is consequential.
A wire capacitance-aware buffer insertion scheme is presented that determines the optimal distance between adjacent buffers on the individual device layers for nonuniform wire density between stacked device layers. The proposed approach also considers TSV location on a 3D wire to optimize the buffer insertion around TSVs. For 3D designs with uniform wire density across stacked device layers, we propose a TSV-aware buffer insertion approach that appropriately models the TSV RC delay impact on interconnect delay to determine the optimum interval between adjacent buffers for individual 3D nets. Moreover, our floorplanning tool help achieve 3D layouts with superior performance by incorporating the impact of nonuniform density on the delay, power and coupling noise in the interconnects during floorplanning.
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Ha, Myunghyun. "EM simulation using the Laguerre-FDTD scheme for multiscale 3-D interconnections." Diss., Georgia Institute of Technology, 2011. http://hdl.handle.net/1853/42850.
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As the current electronic trend is toward integrating multiple functions in a single electronic device, there is a clear need for increasing integration density which is becoming more emphasized than in the past. To meet the industrial need and realize the new system-integration law [1], three-dimensional (3-D) integration is becoming necessary. 3-D integration of multiple functional IC chip/package modules requires co-simulation of the chip and the package to evaluate the performance of the system accurately. Due to large scale differences in the physical dimensions of chip-package structures, the chip-package co-simulation in time-domain using the conventional FDTD scheme is challenging because of Courant-Friedrich-Levy (CFL) condition that limits the time step. Laguerre-FDTD has been proposed to overcome the limitations on the time step. To enhance performance and applicability, SLeEC methodology [2] has been proposed based on the Laguerre-FDTD method. However, the SLeEC method still has limitations to solve practical 3-D integration problems.
This dissertation proposes further improvements of the Laguerre-FDTD and SLeEC method to address practical problems in 3-D interconnects and 3-D integration. A method that increases the accuracy in the conversion of the solutions from Laguerre-domain to time-domain is demonstrated. A methodology that enables the Laguerre-FDTD simulation for any length of time, which was challenging in prior work, is proposed. Therefore, the analysis of the low-frequency response can be performed from the time-domain simulation for a long time period. An efficient method to analyze frequency-domain response using time-domain simulations is introduced. Finally, to model practical structures, it is crucial to model dispersive materials. A Laguerre-FDTD formulation for frequency-dependent dispersive materials is derived in this dissertation and has been implemented.
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Mao, Jifeng. "Modeling of simultaneous switching noise in on-chip and package power distribution networks using conformal mapping, finite difference time domain and cavity resonator methods." Diss., Available online, Georgia Institute of Technology, 2005, 2004. http://etd.gatech.edu/theses/available/etd-10062004-125025/.
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Thesis (Ph. D.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2005.<br>Madhavan Swaminathan, Committee Chair ; Sung Kyu Lim, Committee Member ; Abhijit Chatterjee, Committee Member ; David C. Keezer, Committee Member ; C. P. Wong, Committee Member. Vita. Includes bibliographical references.
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Honrao, Chinmay. "Fine-pitch Cu-snag die-to-die and die-to-interposer interconnections using advanced slid bonding." Thesis, Georgia Institute of Technology, 2013. http://hdl.handle.net/1853/50333.
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Multi-chip integration with emerging technologies such as a 3D IC stack or 2.5D interposer is primarily enabled by the off-chip interconnections. The I/O density, speed and bandwidth requirements for emerging mobile and high-performance systems are projected to drive the interconnection pitch to less than 20 microns by 2015. A new class of low-temperature, low-pressure, high-throughput, cost-effective and maufacturable technologies are needed to enable such fine-pitch interconnections.
A range of interconnection technologies are being pursued to achieve these fine-pitch interconnections, most notably direct Cu-Cu interconnections and copper pillars with solder caps. Direct Cu-Cu bonding has been a target in the semiconductor industry due to the high electrical and thermal conductivity of copper, its high current-carrying capability and compatibility with CMOS BEOL processes. However, stringent coplanarity requirements and high temperature and high pressure bonding needed for assembly have been the major barriers for this technology.
Copper-solder interconnection technology has therefore become the main workhouse for off-chip interconnections, and has recently been demonstrated at pitches as low as 40 microns. However, the current interconnection approaches using copper-solder structures are not scalable to finer feature sizes due to electromigration, and reliability issues arising with decreased solder content. Solid Liquid Inter-Diffusion (SLID) bonding is a promising solution to achieve ultra-fine-pitch and ultra-short interconnections with a copper-solder system, as it relies on the conversion of the entire solder volume into thermally-stable and highly electromigration-resistant intermetallics with no residual solder. Such a complete conversion of solders to stable intermetallics, however, relies on a long assembly time or a subsequent post-annealing process.
To achieve pitches lower than 30 micron pitch, this research aims to study two ultra-short copper-solder interconnection approaches: (i) copper pillar and solder cap technology, and (ii) a novel technology which will enable interconnections with improved electrical performance by fast and complete conversion of solders to stable intermetallics (IMCs) using Solid Liquid Diffusion (SLID) bonding approach. SLID bonding, being a liquid state diffusion process, combined with a novel, alternate layered copper-solder bump structure, leads to higher diffusion rates and a much faster conversion of solder to IMCs. Moreover this assembly bonding is done at a much lower temperature and pressure as compared to that used for Cu-Cu interconnections.
FEM was used to study the effect of various assembly and bump-design characteristics on the post-assembly stress distribution in the ultra-short copper-solder joints, and design guidelines were evolved based on these results. Test vehicles, based on these guidelines, were designed and fabricated at 50 and 100 micron pitch for experimental analysis. The bumping process was optimized, and the effect of current density on the solder composition, bump-height non-uniformity and surface morphology of the deposited solder were studied. Ultra-short interconnections formed using the copper pillar and solder cap technology were characterized.
A novel multi-layered copper-solder stack was designed based on diffusion modeling to optimize the bump stack configuration for high-throughput conversion to stable Cu3Sn intermetallic. Following this modeling, a novel bumping process with alternating copper and tin plating layers to predesigned thicknesses was then developed to fabricate the interconnection structure. Alternate layers of copper and tin were electroplated on a blanket wafer, as a first demonstration of this stack-technology. Dies with copper-solder test structures were bonded using SLID bonding to validate the formation of stable intermetallics.
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Pourbakhsh, Seyed Alireza. "Dummy TSV-Based Timing Optimization for 3D On-Chip Memory." Thesis, North Dakota State University, 2016. https://hdl.handle.net/10365/29093.
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Design and fabrication of three-dimensional (3D) ICs is one the newest and hottest trends in semiconductor manufacturing industry. In 3D ICs, multiple 2D silicon dies are stacked vertically, and through silicon vias (TSVs) are used to transfer power and signals between different dies. The electrical characteristic of TSVs can be modeled with equivalent circuits consisted of passive elements. In this thesis, we use “dummy” TSVs as electrical delay units in 3D SRAMs. Our results prove that dummy TSVs based delay units are as effective as conventional delay cells in performance, increase the operational frequency of SRAM up to 110%, reduce the usage of silicon area up to 88%, induce negligible power overhead, and improve robustness against voltage supply variation and fluctuation.
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Williams, David Arfon. "Silicon on insulator layers for three dimensional circuitry." Thesis, University of Cambridge, 1987. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.236130.
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This dissertation is an account of experimental work conducted at the Microelectronics Research Laboratory of the Physics Department, Cambridge University. Structures have been studied, principally by electron microscopy, to assess the viability of a dual electron beam technique in the production of multiple layer structures. Silicon on insulator structures, where devices are made in individual islands of silicon on an insulating substrate, are of great use for many applications in microelectronics. One of these will be the use of multiple layers of devices in 'three dimensional' circuits. The dual electron beam technique is one way of producing silicon on insulator layers, and the experiments described here are performed on silicon films made by this method. For device applications, the silicon must be single crystal, and the technique uses seeding from a single crystal wafer. The film is grown by rapidly melting and recrystallizing a layer of polycrystalline silicon, and qualitative models of the regrowth process are presented. The results are also compared with quantitative models. Several investigations have been carried out to assess the suitability of the technique for producing stacked layers, where the recrystallization of upper layers must not adversely affect devices already formed in lower layers. The study has found that the dual electron beam technique is well suited to the formation of multiple silicon on insulator layers. The regrowth has been found to behave as predicted on a macroscopic scale, but shows features not previously observed when studied in detail. In particular, the existence of faceting of a submicron scale in the recrystallization front has been proven.
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Somani, Ajay. "Environmentally benign manufacturing of three dimensional integrated circuits." Thesis, Massachusetts Institute of Technology, 2007. http://hdl.handle.net/1721.1/40350.
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Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Materials Science and Engineering, 2007.<br>Includes bibliographical references (p. 221-231).<br>Along with scaling down in size, novel materials have been introduced into the semiconductor industry to enable continued improvements in performance and cost as predicted by Moore's law. It has become important now more than ever to include an environmental impact evaluation of future technologies, before they are introduced into manufacturing, in order to identify potentially environmentally harmful materials or processes and understand their implications, costs, and mitigation requirements. In this thesis, we introduce a methodology to compare alternative options on the environmental axis, along with the cost and performance axes, in order to create environmentally aware and benign technologies. This methodology also helps to identify potential performance and cost issues in novel technologies by taking a transparent and bottoms-up assessment approach. This methodology is applied to the evaluation of the MIT 3D IC technology in comparison to a standard CMOS 2D IC approach. Both options are compared on all three axes - performance, cost and environmental impact.<br>(cont.) The "handle wafer" unit process in the existing 3D IC technology, which is a crucial process for back-to-face integration, is found to have a large environmental impact because of its use of thick metal sacrificial layers and high energy consumption. We explore three different handle wafer options, between-die channel, oxide release layer, and alternative low-temperature permanent bonding. The first two approaches use a chemical handle wafer release mechanism; while the third explores solid liquid inter-diffusion (SLID) bonding using copper-indium at 2000C. Preliminary results for copper-indium bonding indicate that a sub-micron thick multi-layer copper-indium stack, when bonded to a 300 nm thick copper film results in large voids in the bonding interface primarily due to rough as-deposited films. Finally, we conduct an overall assessment of these and other proposed handle wafer technologies. The overall assessment shows that but the oxide release layer approach appears promising; however, each process option has its strength and weaknesses, which need to be understood and pursued accordingly.<br>by Ajay Somani.<br>Ph.D.
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Feero, Brett Stanley. "Three dimensional networks-on-chip a performance evaluation /." Online access for everyone, 2008. http://www.dissertations.wsu.edu/Thesis/Spring2008/b_feero_042208.pdf.
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Das, Shamik 1977. "Design automation and analysis of three-dimensional integrated circuits." Thesis, Massachusetts Institute of Technology, 2004. http://hdl.handle.net/1721.1/18051.
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Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2004.<br>Includes bibliographical references (p. 165-176).<br>This dissertation concerns the design of circuits and systems for an emerging technology known as three-dimensional integration. By stacking individual components, dice, or whole wafers using a high-density electromechanical interconnect, three-dimensional integration can achieve scalability and performance exceeding that of conventional fabrication technologies. There are two main contributions of this thesis. The first is a computer-aided design flow for the digital components of a three-dimensional integrated circuit (3-D IC). This flow primarily consists of two software tools: PR3D, a placement and routing tool for custom 3-D ICs based on standard cells, and 3-D Magic, a tool for designing, editing, and testing physical layout characteristics of 3-D ICs. The second contribution of this thesis is a performance analysis of the digital components of 3-D ICs. We use the above tools to determine the extent to which 3-D integration can improve timing, energy, and thermal performance. In doing so, we verify the estimates of stochastic computational models for 3-D IC interconnects and find that the models predict the optimal 3-D wire length to within 20% accuracy. We expand upon this analysis by examining how 3-D technology factors affect the optimal wire length that can be obtained. Our ultimate analysis extends this work by directly considering timing and energy in 3-D ICs. In all cases we find that significant performance improvements are possible. In contrast, thermal performance is expected to worsen with the use of 3-D integration. We examine precisely how thermal behavior scales in 3-D integration and determine quantitatively how the temperature may be controlled during the circuit placement process. We also show how advanced packaging<br>(cont.) technologies may be leveraged to maintain acceptable die temperatures in 3-D ICs. Finally, we explore two issues for the future of 3-D integration. We determine how technology scaling impacts the effect of 3-D integration on circuit performance. We also consider how to improve the performance of digital components in a mixed-signal 3-D integrated circuit. We conclude with a look towards future 3-D IC design tools.<br>by Shamik Das.<br>Ph.D.
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Rahman, Arifur 1970. "System-level performance evaluation of three-dimensional integrated circuits." Thesis, Massachusetts Institute of Technology, 2001. http://hdl.handle.net/1721.1/8760.
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Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2001.<br>Includes bibliographical references (p. 173-187).<br>As the critical dimensions in VLSI design continue to shrink, system performance of integrated circuits (ICs) will be increasingly dominated by interconnect delay [1]. For the technology generations approaching 50 nm and beyond, innovative system architectures and interconnect technologies will be required to meet the projected system performance [2]. Interconnect material solutions such as copper and low-k inter-level dielectric (ILD) offer only a limited improvement in system performance. Significant and scalable solutions to the interconnect delay problem will require fundamental changes in system design, architecture, and fabrication technologies. Three-dimensional (3-D) ICs can alleviate interconnect delay problems by offering flexibility in system design, placement and routing. They (3-D ICs) can be formed by vertical integration of multiple device layers using wafer bonding, recrystallization, or selective epitaxial growth. The flexibility to place devices along the vertical dimension allows higher device density and smaller form factor in 3-D ICs. The critical signal path that may limit system performance can also be shortened to achieve faster clock speed. By 3-D integration, device layers fabricated with different front-end process technologies can be stacked along the 3rd dimension to form systems-on-a-chip [3]. In this thesis work, opportunities and challenges for 3-D integration of logic networks, microprocessors, and programmable logic have been explored based on system-level modeling and analysis. A stochastic wire-length distribution model has been derived to predict interconnection complexity in 3-D ICs. As more device layers are integrated, the 3-D wire-length distribution becomes narrower compared to that of 2-D ICs, resulting in a significant reduction in the number and length of semi-global and global wires. In 3-D ICs with 2-4 device layers, 30% - 50% reduction in wire-length can be achieved. Besides performance modeling, thermal analysis has also been performed to assess power dissipation and heat removal issues in 3-D ICs. The total capacitance associated with signal interconnects and clock networks can be reduced by 3-D integration, leading to lower power dissipation for system performance comparable to that of 2-D ICs. However, for higher system performance in 3-D ICs, power dissipation increases significantly, and it is likely that innovative cooling techniques will be needed for reliable operation of devices and interconnects.<br>by Arifur Rahman.<br>Ph.D.
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Tadepalli, Rajappa 1979. "Characterization of bonded copper interconnects for three-dimensional integrated circuits." Thesis, Massachusetts Institute of Technology, 2002. http://hdl.handle.net/1721.1/8428.
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Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Materials Science and Engineering, 2002.<br>Includes bibliographical references (leaves 52-54).<br>The unprecedented growth of the semiconductor industry is demanding ultra large-scale integrated (ULSI) circuits with increasing performance at minimum cost and power dissipation. As the critical dimensions in ULSI design continue to shrink, system performance of integrated circuits will be increasingly dominated by interconnect delay. Three-dimensional (3-D) ICs can reduce interconnect delay problems by offering flexibility in system design, placement and routing. 3-D ICs can be formed by vertical integration of multiple device layers using wafer bonding, recrystallization or selective epitaxial growth. The flexibility to place devices along the vertical dimension allows higher device density and reduced total interconnect lengths in 3-D ICs. One approach to fabrication of 3D integrated circuits is to bond previously-processed device layers using metal-metal bonds that also serve as layer-to-layer interconnects. Evaluation of the feasibility of wafer bonding for 3-D integration relies on our ability to characterize bonded interconnects. The reliability of devices containing multi-layer thin film structures is strongly influenced by the adhesion properties of the many interfaces present. Interface fracture failure is highly likely given the high thermal stresses developed during processing and also during service. A four-point bend test technique has been used to evaluate the strength of Cu-Cu bonds. Test structures were fabricated by bonding wafers containing copper lines (with Ta barrier) that were patterned on silicon dioxide. Tests on the thermocompression-bonded copper lines yielded reproducible fracture toughness values (1-10 J/m2 ) for bonds created at 300°C-400°C. The effect of process parameters on bond strength was studied. It was found that surface copper oxide removal prior to bonding using a forming gas purge (95%Ar-5%H2 ) resulted in higher toughness values and lesser variations compared to a N2 purge. Also, bond strength was found to increase with increasing bonding temperature. Thicker bonded films resulted in stronger bonds. Interface failure was found to be most likely at the Cu-Cu and Ta-Silicon dioxide interfaces. The results obtained from different process conditions were used to optimize the bonding process.<br>by Rajappa Tadepalli.<br>S.M.
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Bazaz, Rishik. "Design exchange formats for assessing ohmic drops and thermal profiles in three dimensional integrated circuits." Thesis, Georgia Institute of Technology, 2013. http://hdl.handle.net/1853/47615.
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dimensional integrated circuits (3D ICs) fabricated with through-silicon vias (TSVs) have smaller planar dimensions, shorter wire length, and better performance than 2D ICs. Heat dissipation causing temperature increase has posed new challenges for design of 3D integrated circuits (IC). In addition to the thermal problem, 3D ICs also require careful design of power grids/network because many inter-tier resistive through-silicon vias in 3D IC can cause larger voltage drop than 2D ICs. The performance optimization of a 3D stack requires validation of thermal and electrical integrity during the co-design.
Many 3D stacks will combine digital and analog circuitry, requiring a strong mixed-signal design approach. This will require close collaboration between different domains of circuit fabrication which traditionally have been working separately. Hence there must be some standards to facilitate smooth and effective design of 3D ICs.
In this thesis, we perform steady-state electrical and thermal simulations to analyze the properties of a 3D stack. We optimize electrical and thermal performance using genetic algorithm to achieve optimized power map profile for minimizing voltage drop and temperature, which can benefit both thermal and power integrity management.
This thesis presents initial efforts in designing such standards. Steady state electrical and thermal simulations are performed to demonstrate the necessary information that needs to be exchanged between the dies to ensure adequate co-design. The main purpose of a Design Exchange Format (DEF) between dies is to permit sharing of information necessary for design by external parties without disclosing their intellectual property (IP). The requirements of the standards should be the minimum necessary to produce satisfactory answers. Producing such models is just a customer support function. The role of the standards is to facilitate the transfer of information through a compact model, not necessarily to build one.
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Bonnard, Rémi. "Burst CMOS image sensor with on-chip analog to digital conversion." Thesis, Strasbourg, 2016. http://www.theses.fr/2016STRAD006/document.
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Ce travail vise à étudier l’apport des technologies d’intégration 3D à l’imagerie CMOS ultra-rapide. La gamme de vitesse d’acquisition considérée ici est du million au milliard d’images par seconde. Cependant au-delà d’une dizaine de milliers d’images par seconde, les architectures classiques de capteur d’images sont limitées par la bande passante des buffers de sortie. Pour atteindre des fréquences supérieures, une architecture d’imageur burst est utilisée où une séquence d’une centaine d’images est acquise et stockée dans le capteur. Les technologies d’intégration 3D ont connu un engouement depuis une dizaine d’années et sont considérées comme une solution complémentaire aux travaux menés sur les dispositifs (transistors, composants passifs) pour améliorer les performances des circuits intégrés. Notre choix s’est porté sur une technologie où les circuits intégrés sont directement empilés avant la mise en boitier (3D-SIC). La densité d’interconnexions entre les différents circuits est suffisante pour permettre l’implémentation d’interconnexions au niveau du pixel. L’intégration 3D offre d’intéressants avantages à l’imagerie intégrée car elle permet de déporter l’électronique de lecture sous le pixel. Elle permet ainsi de maximiser le facteur de remplissage du pixel tout en offrant une large place aux circuits de conditionnement du signal. Dans le cas de l’imagerie burst, cette technologie permet de consacrer une plus grande surface aux mémoires dédiées au stockage de la séquence d’image et ce au plus proche des pixels. Elle permet aussi de réaliser sur la puce la conversion analogique numérique des images acquises<br>This work aims to study the inflows of the 3D integration technology to ultra-high speed CMOS imaging. The acquisition speed range considered here is between one million to one billion images per second. However above ten thousand images per second, classical image sensor architectures are limited by the data bandwidth of the output buffers. To reach higher acquisition frequencies, a burst architecture is used where a set of about one hundred images are acquired and stored on-chip. 3D integration technologies become popular more than ten years ago and are considered as a complementary solution to the technological improvements of the devices. We have chosen a technology where integrated circuits are stacked on the top of each other (3D-SIC). The interconnection density between the circuits is high enough to enable interconnections at the pixel level. The 3D integration offers some significant advantages because it allows deporting the readout electronic below the pixel. It thus increases the fill factor of the pixel while offering a wide area to the signal processing circuit. For burst imaging, this technology provides more room to the memory dedicated to the image storage while staying close to the pixel. It also allows implementing analog to digital converter on-chip
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Athikulwongse, Krit. "Placement for fast and reliable through-silicon-via (TSV) based 3D-IC layouts." Diss., Georgia Institute of Technology, 2012. http://hdl.handle.net/1853/45783.
Full textAbstract:
The objective of this research is to explore the feasibility of addressing the major performance and reliability problems or issues, such as wirelength, stress-induced carrier mobility variation, temperature, and quality trade-offs, found in three-dimensional integrated circuits (3D ICs) that use through-silicon vias (TSVs) at placement stage. Four main works that support this goal are included. In the first work, wirelength of TSV-based 3D ICs is the main focus. In the second work, stress-induced carrier mobility variation in TSV-based 3D ICs is examined. In the third work, temperature inside TSV-based 3D ICs is investigated. In the final work, the quality trade-offs of TSV-based 3D-IC designs are explored.
In the first work, a force-directed, 3D, and gate-level placement algorithm that efficiently handles TSVs is developed. The experiments based on synthesized benchmarks indicate that the developed algorithm helps generate GDSII layouts of 3D-IC designs that are optimized in terms of wirelength. In addition, the impact of TSVs on other physical aspects of 3D-IC designs is also studied by analyzing the GDSII layouts.
In the second work, the model for carrier mobility variation caused by TSV and STI stresses is developed as well as the timing analysis flow considering the stresses. The impact of TSV and STI stresses on carrier mobility variation and performance of 3D ICs is studied. Furthermore, a TSV-stress-driven, force-directed, and 3D placement algorithm is developed. It exploits carrier mobility variation, caused by stress around TSVs after fabrication, to improve the timing and area objectives during placement. In addition, the impact of keep-out zone (KOZ) around TSVs on stress, carrier mobility variation, area, wirelength, and performance of 3D ICs is studied.
In the third work, two temperature-aware global placement algorithms are developed. They exploit die-to-die thermal coupling in 3D ICs to improve temperature during placement. In addition, a framework used to evaluate the results from temperature-aware global placements is developed. The main component of the framework is a GDSII-level thermal analysis that considers all structures inside a TSV-based 3D IC while computing temperature. The developed placers are compared with several state-of-the-art placers published in recent literature. The experimental results indicate that the developed algorithms help improve the temperature of 3D ICs effectively.
In the final work, three block-level design styles for TSV-based die-to-wafer bonded 3D ICs are discussed. Several 3D-IC layouts in the three styles are manually designed. The main difference among these layouts is the position of TSVs. Finally, the area, wirelength, timing, power, temperature, and mechanical stress of all layouts are compared to explore the trade-offs of layout quality.
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Zhao, Xin. "Reliable clock and power delivery network design for three-dimensional integrated circuits." Diss., Georgia Institute of Technology, 2012. http://hdl.handle.net/1853/45881.
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The main objective of this thesis is to design reliable clock-distribution networks and power-delivery networks for three-dimensional integrated circuits (3D ICs) using through-silicon vias (TSVs). This dissertation supports this goal by addressing six research topics. The first four works focus on 3D clock tree synthesis for low power, pre-bond testability, TSV-induced obstacle avoidance, and TSV utilization. The last two works develop modeling approaches for reliability analysis on 3D power-delivery networks.
In the first work, a clock synthesis algorithm is developed for low-power and low-slew 3D clock network design. The impact of various design parameters on clock performance, including the wirelength, clock power, clock slew, and skew, is investigated. These parameters cover the TSV count, TSV parasitics, the maximum loading capacitance of the clock buffers, and the supply voltage.
In the second work, a clock synthesis algorithm is developed to construct 3D clock networks for both pre-bond testability and post-bond operability. Pre-bond testing of 3D stacked ICs involves testing each individual die before bonding, which can improve the overall yield of 3D ICs by avoiding stacking defective dies with good ones. Two key techniques including TSV-buffer insertion and redundant tree generation are implemented to minimize clock skew and ensure pre-bond testing. The impact of TSV utilization and TSV parasitics on clock power is also investigated.
In the third work, an obstacle-aware clock tree synthesis method is presented for through-silicon-via (TSV)-based 3D ICs. A unique aspect of this problem lies in the fact that various types of TSVs become obstacles during 3D clock routing including signal, power/ground, and clock TSVs. These TSVs may occupy silicon area or routing layers. The generated clock tree does not sacrifice wirelength or clock power too much and avoids TSV-induced obstacles.
In the fourth work, a decision-tree-based clock synthesis (DTCS) method is developed for low-power 3D clock network design, where TSVs form a regular 2D array. This TSV array style is shown to be more manufacturable and practical than layouts with TSVs located at irregular spots. The DTCS method explores the entire solution space for the best TSV array utilization in terms of low power. Close-to-optimal solutions can be found for power efficiency with skew minimization in short runtime.
In the fifth work, current crowding and its impact on 3D power grid integrity is investigated. Due to the geometry of TSVs and connections to the global power grid, significant current crowding can occur. The current density distribution within a TSV and its connections to the global power grid is explored. A simple TSV model is implemented to obtain current density distributions within a TSV and its local environment. This model is checked for accuracy by comparing with identical models simulated using finite element modeling methods. The simple TSV models are integrated with the global power wires for detailed chip-scale power analysis.
In the sixth work, a comprehensive multi-physics modeling approach is developed to analyze electromigration (EM) in TSV-based 3D connections. Since a TSV has regions of high current density, grain boundaries play a significant role in EM dominating atomic transport. The transient analysis is performed on atomic transport including grain and grain boundary structures. The evolution of atomic depletion and accumulation is simulated due to current crowding. And the TSV resistance change is modeled.
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King, Calvin R. Jr. "Thermal management of three-dimensional integrated circuits using inter-layer liquid cooling." Diss., Georgia Institute of Technology, 2012. http://hdl.handle.net/1853/44759.
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Heat removal technologies are among the most critical needs for three-dimensional (3D) stacking of high-performance microprocessors. This research reports a 3D integration platform that can support the heat removal requirements for 3D integrated circuits that contain high-performance microprocessors in the 3D stack.
This work shows the use of wafer-level batch fabrication to develop advanced electrical and fluidic three-dimensional interconnect networks in a 3D stack. Fabrication results are shown for the integration of microchannels and electrical through-silicon vias (TSVs). A compact physical model is developed to determine the design trade-offs for microchannel heat sink and electrical TSV integration. An experimental thermal measurement test-bed for evaluating a 3D inter-layer liquid cooling platform is developed. Experimental thermal testing results for an air-cooled chip and a liquid-cooled chip are compared. Microchannel heat sink cooling shows a significant junction temperature and heat sink thermal resistance reduction compared to air-cooling. The on-chip integrated microchannel heat sink, which has a thermal resistance of 0.229 °C/W, enables cooling of >100W/cm² of each high-power density chip, while maintaining an average junction temperature of less than 50°C. Cooling liquid is circulated through the 3D stack (two layers) at flow rates of up to 100 ml/min.
The ability to assemble chips with integrated electrical and fluidic I/Os and seal fluidic interconnections at each strata interface is demonstrated using three assembly and fluidic sealing techniques. Assembly results show the stacking of up to four chips that contain integrated electrical and fluidic I/O interconnects, with an electrical I/O density of ~1600/cm².
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Schoenfliess, Kory Michael. "Performance Analysis of System-on-Chip Applications of Three-dimensional Integrated Circuits." NCSU, 2006. http://www.lib.ncsu.edu/theses/available/etd-12172005-143909/.
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In the research community, three-dimensional integrated circuit (3DIC) technology has garnered attention for its potential use as a solution to the scaling gap between MOSFET device characteristics and interconnects. The purpose of this work is to examine the performance advantages offered by 3DICs. A 3D microprocessor-based test case has been designed using an automated 3DIC design flow developed by the researchers of North Carolina State University. The test case is based on an open architecture that is exemplary of future complex System-on-Chip (SoC) designs. Specialized partitioning and floorplanning procedures were integrated into the design flow to realize the performance gains of vertical interconnect structures called 3D vias. For the post-design characterization of the 3DIC, temperature dependent models that describe circuit performance over temperature variations were developed. Together with a thermal model of the 3DIC, the performance scaling with temperature was used to predict the degree of degradation of the delay and power dissipation of the 3D test case. Using realistic microprocessor workloads, it was shown that the temperatures of the 3DIC thermal model are convergent upon a final value. The increase in delay and power dissipation from the thermal analysis was found to be negligibly small when compared to the performance improvements of the 3DIC. Timing analysis of the 3D design and its 2D version revealed a critical path delay reduction of nearly 26.59% when opting for a 3D implementation. In addition, the 3D design offered power dissipation savings of an average of 3% while running at a proportionately higher clock frequency.
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Weerasekera, Roshan. "System Interconnection Design Trade-offs in Three-Dimensional (3-D) Integrated Circuits." Doctoral thesis, Stockholm : Informations- och kommunikationsteknik, Kungliga Tekniska högskolan, 2008. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-9586.
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Tadepalli, Rajappa 1979. "Characterization and requirements for Cu-Cu bonds for three-dimensional integrated circuits." Thesis, Massachusetts Institute of Technology, 2007. http://hdl.handle.net/1721.1/38515.
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Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Materials Science and Engineering, 2007.<br>This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.<br>Includes bibliographical references (p. 197-206).<br>Three-dimensional integrated circuit (3D IC) technology enables heterogeneous integration of devices fabricated from different technologies, and reduces global RC delay by increasing the device density per unit chip area. Wafer-level Cu-Cu thermocompression bonding provides an attractive route to 3D IC fabrication, with Cu serving as both the electrical and mechanical interconnection between adjacent device layers. While the bonding process is currently employed for such applications, the lack of quantitative understanding of the bond quality and reliability has made developing robust processes extremely challenging. The current work addresses this problem through the development and implementation of bond toughness measurement techniques that investigate the effects of thin film patterning, surface chemistry and process parameters on the Cu-Cu bond quality under a range of loading conditions. The four-point bend test was used to quantify Cu-Cu bond toughness, Gc, under mixed-mode loading and to develop an optimized process flow that enabled the creation of high- toughness bonds (> 5 J/m2) at a bonding temperature of 300 oC. Mixed-mode loading induces significant plastic energy dissipation in ductile layers, resulting in an overestimation of the true adhesive strength of the interface.<br>(cont.) The chevron test method has been developed to allow bond toughness measurements under mode I loading, thereby probing the 'true' work of adhesion of the bonded interface. Furthermore, analysis of the bonded chevron specimen with different layer thicknesses was performed to allow the specimen to be used to characterize the bonded interface under mixed-mode loading conditions. Chevron tests reveal that the toughness of patterned Cu films is a strong function of the feature size and orientation. For debond propagation across periodic bonded and unbonded regions, a pronounced increase in Gc was observed, compared to debond propagation along a continuous bonded interface. Effects of patterning were significantly different in ductile thermocompression and brittle fusion bonded systems, with the latter showing a reduction in toughness due to patterning. The ultimate limit of low temperature Cu-Cu adhesion was investigated using pull-off force measurements in Atomic Force Microscope (AFM) under ultra-high vacuum (UHV) conditions. These measurements show that the work of adhesion of Cu bonds created at room temperature is ~ 3 J/m2, similar to Gc for wafer-level bonds created at 300 oC and measured using the chevron test.<br>(cont.) Deliberate pre-adhesion exposure of the Cu surfaces to 10-6 Torr O2 leads to a dramatic reduction in adhesion (to 0.1 J/m2), suggesting the formation of a Cu oxide that is detrimental to the Cu-Cu bonding process. The UHV-AFM measurements suggest that strong Cu-Cu bonds can be created by bonding clean Cu surfaces at room temperature, thereby eliminating several thermal stability issues in the thermocompression bonding process. The thermal management problem in 3D ICs containing multiple device layers was examined using an analytical model of forced liquid cooling via Cu-sealed integrated microchannels. Integration of microchannels requires a reduction in the area available for interconnects and adhesion, causing a trade-off between the inter-layer bonded area and the size and density of the channels that can be included. The optimum channel density is a function of the achievable local Cu-Cu bond strength.<br>by Rajappa Tadepalli.<br>Ph.D.
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Yeleswarapu, Krishnamurthy. "TCAD simulation framework for the study of TSV-device interaction." Thesis, Georgia Institute of Technology, 2013. http://hdl.handle.net/1853/51785.
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With the reduction in transistor dimensions to a few tens of nanometers as a result of aggressive scaling, interconnect delay has now become one of the major bottlenecks to chip performance. Secondly, interconnect power and area have both become a significant part of the total chip power and area respectively. These concerns have led to an effort to find a solution that would reduce interconnect delay and leakage, while also reducing the area they occupy in a chip, so that either the chip area could be reduced, or more functionality could be incorporated within a certain area. 3D integration, i.e., stacking of various sub-systems of a chip on top of each other, enables chip-makers to achieve higher packaging efficiencies, thereby reducing system cost, while also reducing delay (and thus increasing the available bandwidth). Through Silicon Vias (TSVs) have emerged as the key interconnect technology for 3D ICs, as they enable significant reduction in delay and leakage compared to wire-bonded dies, while also occupying less area in a package. They also enable stacking of sub-systems which differ in functionality, and stacking of multiple dies. Also, unlike wire-bond, dies need not be bandwidth limited by the number of wire bonds that can be made between two levels in a stack. While TSVs offer many advantages, one of the concerns when implementing a 3D system using TSVs is the mechanisms of interaction between a TSV and a device in its vicinity. Another concern is with regards to the interaction between the TSV and its surrounding material. The purpose of this thesis is to develop a TCAD framework for process and device co-simulation of a TSV transistor system to study the various mechanisms of interaction between them, as well as between the TSV and substrate. The utility of this tool has been demonstrated by studying two mechanisms of interaction, the effect of TSV-induced stress, and the effect of TSV-device electrical coupling, on the electrical performance of bulk NMOS and PMOS transistors. The results from 3D TCAD simulations suggest that designers can scale the keep out zone (KOZ) around TSVs more aggressively, allowing for more efficient utilization of silicon area, without a drastic performance penalty.
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Visan, Silviu. "Simulation électromagnétique 3D basée sur la méthode des différences finies dans le domaine temporel : application à l'étude de structures planaires utilisées dans les circuits intégrés monolithiques microondes et millimétriques." Grenoble INPG, 1994. http://www.theses.fr/1994INPG0014.
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Ce travail de these a permis la mise au point et l'implementation d'une methode de simulation electromagnetique tridimensionnelle basee sur les differences finies dans le domaine temporel (fdtd - finite difference time domain). Le logiciel qui a ete realise sert a caracteriser des structures planaires, notamment celles utilisees dans les circuits integres monolithiques microondes (mmic - microwave monolithic integrated circuits). Le chapitre 1 presente le contexte de l'etude. Dans le chapitre 2 nous presentons en detail la methode qui est a la base de nos simulations. Il resulte qu'elle presente des avantages importants: tres bonne generalite, caracterisation large bande d'une structure apres une seule simulation, possibilite de prendre en compte a la fois des structures fermees et des structures ouvertes. Dans le chapitre 3, la methode a ete validee par l'etude d'une cavite resonante a 30 ghz, d'une ligne microruban uniforme, et d'un trou metallise sur une ligne microruban. Dans le chapitre 4, une etude complete a ete effectuee sur les structures coplanaires utilisees dans les mmic. Nous avons etudie des lignes uniformes, des discontinuites uniaxiales (court- circuit, circuit ouvert, gap, saut de largeur) et des discontinuites multiaxiales (coude angle droit, te, avec ou sans ponts a air). Une etude comparative a ete realisee entre deux solutions possibles pour la suppression du mode fentes couplees dans les mmic: le pont a air et les trous metallises. Le chapitre 5 presente l'etude des interconnexions entre des modules mmic et des modules hybrides. On a ainsi presente les variations des parametres s de l'interconnexion en fonction des parametres technologiques de celle-ci. Dans le chapitre 6, la simulation d'une antenne planaire a donne des resultats tout a fait conformes aux mesures experimentales. Les conclusions de ce travail sont presentees dans le chapitre 7
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Minz, Jacob Rajkumar. "Physical Design Automation for System-on-Packages and 3D-Integrated Circuits." Diss., Georgia Institute of Technology, 2006. http://hdl.handle.net/1853/14012.
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The focus of this research was to develop interconnect-centric
physical design tools for 3D technologies.
A new routing model for the SOP structure was developed which
incorporated the 3D structure and formalized the resource structure
that facilitated the development of the global routing tool.
The challenge of this
work was to intelligently convert the 3D SOP routing problem into a set
of 2D problems which could be solved efficiently.
On the lines of MCM, the global routing problem
was divided into a number of phases namely, coarse pin distribution,
net distribution, detailed pin distribution, topology generation, layer
assignment, channel assignment and local routing. The novelty in this
paradigm is due to the feed-through vias needed by the nets which traverse
through multiple placement layers. To gain further improvements in
performance, optical
routing was proposed and a cost analysis study was done. The areas for
the placement of waveguides were efficiently determined, which reduced
delays and maximized utilization.
The global router developed was integrated into a simulated-annealing based
floorplanner to investigate trade-offs of various objectives. Since power-supply
noise suppression is of paramount importance in SOP, a model was developed
for the SOP power-supply network. Decap allocation, and
insertion were also integrated into the framework. The challenges
in this work were to integrate computationally intensive analysis tools with
a floorplanning that works to its best efficency provided the evaluation of
the cost functions are rapid. Trajectory-based approaches were used to sample
representative data points for congestion analysis and interpolate the
the congestion metric during the optimization schedule. Efficient
algorithms were also proposed for 3D clock routing, which acheived
equal skews under uniform and worst thermal profiles. Other
objectives such as wirelength, through-vias, and
power were also handled.
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Wang, Shengcheng [Verfasser], and M. B. [Akademischer Betreuer] Tahoori. "Reliable Design of Three-Dimensional Integrated Circuits / Shengcheng Wang ; Betreuer: M. B. Tahoori." Karlsruhe : KIT-Bibliothek, 2018. http://d-nb.info/1161008772/34.
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Fernando, Pradeep R. "Genetic algorithm based two-dimensional and three-dimensional floorplanning for VLSI ASICs." [Tampa, Fla] : University of South Florida, 2006. http://purl.fcla.edu/usf/dc/et/SFE0001549.
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Kalargaris, Charalampos. "Design methodologies and tools for vertically integrated circuits." Thesis, University of Manchester, 2017. https://www.research.manchester.ac.uk/portal/en/theses/design-methodologies-and-tools-for-vertically-integrated-circuits(63c9c674-566a-44e5-b6b6-8a277b1adf08).html.
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Vertical integration technologies, such as three-dimensional integration and interposers, are technologies that support high integration densities while offering shorter interconnect lengths as compared to planar integration and other packaging technologies. To exploit these advantages, however, several challenges lay across the designing, manufacturing and testing stages of integrated systems. Considering the high complexity of modern microelectronic devices and the diverse features of vertical integration technologies, this thesis sheds light on the circuit design process. New methodologies and tools are offered in order to assess and improve traditional objectives in circuit design, such as performance, power, and area for vertically integrated circuits. Interconnects on different interposer materials are investigated, demonstrating the several trade-offs between power, performance, area, and crosstalk. A backend design flow is proposed to capture the performance and power gains from the introduction of the third dimension. Emphasis is also placed on the power consumption of modern circuits due to the immense growth of battery-operated devices in the last fifteen years. Therefore, the effect of scaling the operating voltage in three-dimensional circuits is investigated as it is one of the most efficient techniques for reducing power while considering the performance of the circuit. Furthermore, a solution to eliminate timing penalties from the usage of voltage scaling technique at finer circuits granularities is also presented in this thesis.
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Park, Jin Hong. "Physics and technology of low temperature germanium MOSFETs for monolithic three dimensional integrated circuits /." May be available electronically:, 2009. http://proquest.umi.com/login?COPT=REJTPTU1MTUmSU5UPTAmVkVSPTI=&clientId=12498.
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Rodriguez, Omar. "Thermo-Mechanical Reliability of Micro-Interconnects in Three-Dimensional Integrated Circuits: Modeling and Simulation." DigitalCommons@USU, 2010. https://digitalcommons.usu.edu/etd/737.
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Three-dimensional integrated circuits (3D ICs) have been designed with the purpose of achieving higher communication speed by reducing the interconnect length between integrated circuits, and integrating heterogeneous functions into one single package, among other advantages. As a growing, new technology, researchers are still studying the different parameters that impact the overall lifetime of such packages in order to ensure the customer receives reliable end products. This study focused on the effect of four design parameters on the lifetime of the interconnects and, in particular, solder balls and through-silicon vias (TSVs). These parameters included TSV pitch, TSV diameter, underfill stiffness and underfill thickness. A three-dimensional finite element model of a 3D IC package was built in ANSYS to analyze the effect of these parameters under thermo-mechanical cyclic loading. The stresses and damage in the interconnects of the IC were evaluated using Coffin-Manson and the energy partitioning fatigue damage models. A three-level Taguchi design of experiment method was utilized to evaluate the effect of each parameter. Minitab software was used to assess the main effects of the selected design parameters. Locations of maximum stresses and possible damage initiation were discussed, and recommendations were made to the manufacturer for package optimization.
Due to the very small scale of the interconnects, conducting mechanical tests and measuring strains in small microscopic scale material is very complicated and challenging; therefore, it is very difficult to validate finite element and analytical analysis of stress and strain in microelectronic devices. At the next step of this work, a new device and method were proposed to facilitate testing and strain measurements of material at microscopic scale.
This new micro-electromechanical system (MEMS) consisted of two piezoelectric members that were constrained by a rigid frame and that sandwiched the test material. These two piezoelectric members act as load cell and strain measurement sensors. As the voltage is applied to the first member, it induces a force to the specimen and deforms it, which in turn deforms the second piezoelectric member. The second piezoelectric member induces an output voltage that is proportional to its deformation. Therefore, the strain and stresses in the test material can be determined by knowing the mechanical characteristics of the piezoelectric members. Advantages of the proposed system include ease of use, particularly at microscopic scale, adaptability to measure the strain of different materials, and flexibility to measure the modulus of elasticity for an unknown material. An analytical analysis of the device and method was presented, and the finite element simulation of the device was accomplished. The results were compared and discussed. An inelastic specimen was also analyzed and sensitivity of the device to detecting nonlinear behavior was evaluated. A characteristic curve was developed for the specific geometry and piezoelectric material.
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Jung, Moongon. "Low power and reliable design methodologies for 3D ICs." Diss., Georgia Institute of Technology, 2014. http://hdl.handle.net/1853/51824.
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The main objective of this dissertation is to explore and develop computer-aided-design methodologies and optimization techniques for reliability, performance, and power of through-silicon-via-based 3D IC designs. Through-silicon-via (TSV), a vertical interconnect element between dies, is the key enabling technology in 3D ICs. This new design element provides unprecedented design freedom as well as challenges. To maximize benefits and overcome challenges in TSV-based 3D ICs, new analysis methodologies and optimization techniques should be developed. In this dissertation, first, the robustness of 3D power delivery network is assessed under different power/ground TSV placement schemes and TSV RC variations. Next, thermo-mechanical stress and reliability problems are examined in full-chip/stack scale using the principle of linear superposition of stress tensors. Finally, physical design methods for low power 3D designs are explored to enhance the 3D power benefit over the 2D counterpart.
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Lewis, Dean Leon. "Design for pre-bond testability in 3D integrated circuits." Diss., Georgia Institute of Technology, 2012. http://hdl.handle.net/1853/45756.
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In this dissertation we propose several DFT techniques specific to 3D
stacked IC systems. The goal has explicitly been to create techniques that
integrate easily with existing IC test systems. Specifically, this means
utilizing scan- and wrapper-based techniques, two foundations
of the digital IC test industry.
First, we describe a general test architecture for 3D ICs. In this
architecture, each tier of a 3D design is wrapped in test control logic that
both manages tier test
pre-bond and integrates the tier into the large test architecture post-bond.
We describe a new kind of boundary scan to provide the necessary test control
and observation of the partial circuits, and we propose
a new design methodology for test hardcore that ensures both pre-bond functionality
and post-bond optimality. We present the application of these techniques to
the 3D-MAPS test vehicle, which has proven their effectiveness.
Second, we extend these DFT techniques to circuit-partitioned designs. We find
that boundary scan design is generally sufficient, but that some 3D designs require
special DFT treatment. Most importantly, we demonstrate that the functional
partitioning inherent in 3D design can potentially decrease the total test cost
of verifying a circuit.
Third, we present a new CAD algorithm for designing 3D test wrappers. This algorithm
co-designs the pre-bond and post-bond wrappers to simultaneously minimize test
time and routing cost. On average, our algorithm utilizes over 90% of the wires
in both the pre-bond and post-bond wrappers.
Finally, we look at the 3D vias themselves to develop a low-cost, high-volume
pre-bond test methodology appropriate for production-level test. We describe
the shorting probes methodology, wherein large test probes are used to contact
multiple small 3D vias. This technique is an all-digital test method that
integrates seamlessly into existing test flows. Our
experimental results demonstrate two key facts: neither the large capacitance
of the probe tips nor the process variation in the 3D vias and the probe tips
significantly hinders the testability of the circuits.
Taken together, this body of work defines a complete test methodology for
testing 3D ICs pre-bond, eliminating one of the key hurdles to the
commercialization of 3D technology.
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Feng, Jia. "High-performance germanium-on-insulator MOSFETs for three-dimensional integrated circuits based on rapid melt growth /." May be available electronically:, 2009. http://proquest.umi.com/login?COPT=REJTPTU1MTUmSU5UPTAmVkVSPTI=&clientId=12498.
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Nain, Rajeev Kumar. "Floorplan Design and Yield Enhancement of 3-D Integrated Circuits." PDXScholar, 2011. https://pdxscholar.library.pdx.edu/open_access_etds/2810.
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We have developed a placement-aware 3-D floorplanning algorithm that enables additional wirelength reduction by planning for 3-D placement of logic gates in selected circuit modules during the floorplanning stage. Thus it also bridges the existing gap between 3-D floorplanning and 3-D placement. To reduce the solution space of 3-D floorplanning which is known to be an NP-hard problem, we derive a set of feasibility conditions on the topological representation of a floorplan. In addition, we have designed a fast module packing algorithm that satisfies a set of constraints for placement-aware 3-D floorplanning. Furthermore, we have designed an efficient evolutionary algorithm that is used in the proposed 3-D floorplanning algorithm for multi-objective combinatorial optimization. Our results show that the proposed placement-aware 3-D floorplanning algorithm is very fast, and it reduces the system level total wirelength by 9.8% compared to existing state-of-the-art floorplanning tools that do not plan for 3-D placement of floorplanning modules.
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Isaacs, Steven. "Two-phase flow and heat transfer in pin-fin enhanced micro-gaps." Thesis, Georgia Institute of Technology, 2013. http://hdl.handle.net/1853/50282.
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In modern microprocessors, thermal management has become one of the main hurdles in continued performance enhancement. Cooling schemes utilizing single phase microfluidics have been investigated extensively for enhanced heat dissipation from microprocessors. However, two-phase fluidic cooling devices are becoming a promising approach, and are less understood. This study aims to examine two-phase flow and heat transfer within a pin-fin enhanced micro-gap. The pin-fin array covered an area of 1cm x 1cm and had a pin diameter, height and pitch of 150μm, 200μm and 225μm, respectively, (aspect ratio of 1.33). This study covers both uniformly and partially heated scenarios. The working fluid used was R245fa. The average heat transfer coefficient and high speed flow visualization results indicated a rapid transition to the annular flow regime with a strong dependence on heat flux. Also, unique, conically-shaped two-phase wakes were observed, demonstrating the lateral spreading capability of the pin-fin array geometry.
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Lee, Young-Joon. "CAD methodologies for low power and reliable 3D ICs." Diss., Georgia Institute of Technology, 2013. http://hdl.handle.net/1853/47635.
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The main objective of this dissertation is to explore and develop computer-aided-design (CAD) methodologies and optimization techniques for reliability, timing performance, and power consumption of through-silicon-via(TSV)-based and monolithic 3D IC designs. The 3D IC technology is a promising answer to the device scaling and interconnect problems that industry faces today. Yet, since multiple dies are stacked vertically in 3D ICs, new problems arise such as thermal, power delivery, and so on. New physical design methodologies and optimization techniques should be developed to address the problems and exploit the design freedom in 3D ICs. Towards the objective, this dissertation includes four research projects.
The first project is on the co-optimization of traditional design metrics and reliability metrics for 3D ICs. It is well known that heat removal and power delivery are two major reliability concerns in 3D ICs. To alleviate thermal problem, two possible solutions have been proposed: thermal-through-silicon-vias (T-TSVs) and micro-fluidic-channel (MFC) based cooling. For power delivery, a complex power distribution network is required to deliver currents reliably to all parts of the 3D IC while suppressing the power supply noise to an acceptable level. However, these thermal and power networks pose major challenges in signal routability and congestion. In this project, a co-optimization methodology for signal, power, and thermal interconnects in 3D ICs is presented. The goal of the proposed approach is to improve signal, thermal, and power noise metrics and to provide fast and accurate design space explorations for early design stages.
The second project is a study on 3D IC partition. For a 3D IC, the target circuit needs to be partitioned into multiple parts then mapped onto the dies. The partition style impacts design quality such as footprint, wirelength, timing, and so on. In this project, the design methodologies of 3D ICs with different partition styles are demonstrated. For the LEON3 multi-core microprocessor, three partitioning styles are compared: core-level, block-level, and gate-level. The design methodologies for such partitioning styles and their implications on the physical layout are discussed. Then, to perform timing optimizations for 3D ICs, two timing constraint generation methods are demonstrated that lead to different design quality.
The third project is on the buffer insertion for timing optimization of 3D ICs. For high performance 3D ICs, it is crucial to perform thorough timing optimizations. Among timing optimization techniques, buffer insertion is known to be the most effective way. The TSVs have a large parasitic capacitance that increases the signal slew and the delay on the downstream. In this project, a slew-aware buffer insertion algorithm is developed that handles full 3D nets and considers TSV parasitics and slew effects on delay. Compared with the well-known van Ginneken algorithm and a commercial tool, the proposed algorithm finds buffering solutions with lower delay values and acceptable runtime overhead.
The last project is on the ultra-high-density logic designs for monolithic 3D ICs. The nano-scale 3D interconnects available in monolithic 3D IC technology enable ultra-high-density device integration at the individual transistor-level. The benefits and challenges of monolithic 3D integration technology for logic designs are investigated. First, a 3D standard cell library for transistor-level monolithic 3D ICs is built and their timing and power behavior are characterized. Then, various interconnect options for monolithic 3D ICs that improve design quality are explored. Next, timing-closed, full-chip GDSII layouts are built and iso-performance power comparisons with 2D IC designs are performed. Important design metrics such as area, wirelength, timing, and power consumption are compared among transistor-level monolithic 3D, gate-level monolithic 3D, TSV-based 3D, and traditional 2D designs.
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Sane, Hemant. "Power supply noise analysis for 3D ICs using through-silicon-vias." Thesis, Georgia Institute of Technology, 2010. http://hdl.handle.net/1853/33875.
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3D design is being recognized widely as the next BIG thing in system integration. However, design and analysis tools for 3D are still in infancy stage. Power supply noise analysis is one of the critical aspects of a design. Hence, the area of noise analysis for 3D designs is a key area for future development. The following research presents a new parasitic RLC modeling technique for 3D chips containing TSVs as well as a novel optimization algorithm for power-ground network of a 3D chip with the aim of minimizing noise in the network. The following work also looks into an existing commercial IR drop analysis tool and presents a way to modify it with the aim of handling 3D designs containing TSVs.
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Redmond, Matthew J. "Thermal management of 3-D stacked chips using thermoelectric and microfluidic devices." Thesis, Georgia Institute of Technology, 2013. http://hdl.handle.net/1853/50240.
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This thesis employs computational and experimental methods to explore hotspot cooling and high heat flux removal from a 3-D stacked chip using thermoelectric and microfluidic devices. Stacked chips are expected to improve microelectronics performance, but present severe thermal management challenges. The thesis provides an assessment of both thermoelectric and microfluidic technologies and provides guidance for their implementation in the 3-D stacked chips.
A detailed 3-D thermal model of a stacked electronic package with two dies and four ultrathin integrated TECs is developed to investigate the efficacy of TECs in hotspot cooling for 3-D technology. The numerical analysis suggests that TECs can be used for on demand cooling of hotspots in 3-D stacked chip architecture. A strong vertical coupling is observed between the top and bottom TECs and it is found that the bottom TECs can detrimentally heat the top hotspots. As a result, TECs need to be carefully placed inside the package to avoid such undesired heating. Thermal contact resistances between dies, inside the TEC module, and between the TEC and heat spreader are shown to significantly affect TEC performance.
TECs are most effective for cooling localized hotspots, but microchannels are advantageous for cooling large background heat fluxes. In the present work, the results of heat transfer and pressure drop experiments in the microchannels with water as the working fluid are presented and compared to the previous microchannel experiments and CFD simulations. Heat removal rates of greater than 100 W/cm2 are demonstrated with these microchannels, with a pressure drop of 75 kPa or less. A novel empirical correlation modeling method is proposed, which uses finite element modeling to model conduction in the channel walls and substrate, coupled with an empirical correlation to determine the convection coefficient. This empirical correlation modeling method is compared to resistor network and CFD modeling. The proposed modeling method produced more accurate results than resistor network modeling, while solving 60% faster than a conjugate heat transfer model using CFD.
The results of this work demonstrate that microchannels have the ability to remove high heat fluxes from microelectronic packages using water as a working fluid. Additionally, TECs can locally cool hotspots, but must be carefully placed to avoid undesired heating. Future work should focus on overcoming practical challenges including fabrication, cost, and reliability which are preventing these technologies from being fully leveraged.
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Liu, Xi. "Experimental and theoretical assessment of Through-Silicon Vias for 3D integrated microelectronic packages." Diss., Georgia Institute of Technology, 2013. http://hdl.handle.net/1853/50249.
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With continued push toward 3D integrated packaging, Through-Silicon Vias (TSVs) play an increasingly important role in interconnecting stacked silicon dies. Although progress is being made in the fabrication of TSVs, experimental and theoretical assessment of their thermomechanical reliability is still in infancy. This work explores the thermomechanical reliability of TSVs through numerical models and innovative experimental characterization techniques. Starting with free-standing wafers, this work examines failure mechanisms such as Si and SiO₂ cohesive cracking as well as SiO₂/Cu interfacial cracking. Such cohesive crack propagation and interfacial crack propagation are studied using fracture mechanics finite-element modeling, and the energy available for crack propagation is determined through crack extension using the proposed centered finite-difference approach (CFDA). In parallel to the simulations, silicon wafers with TSVs are designed and fabricated and subjected to thermal shock test. Cross-sectional SEM failure analysis is carried out to study cohesive and interfacial crack initiation and propagation under thermal excursions. In addition, local micro-strain fields under thermal excursions are mapped through synchrotron X-ray diffraction. To understand the 3D to 2D strain measurement data projection process, a new data interpretation method based on beam intensity averaging is proposed and validated with measurements. Building upon the work on free-standing wafers, this research studies the package assembly issues and failure mechanisms in multi-die stacks. Comprehensive design-of-simulations study is carried out to assess the effect of various material and geometry parameters on the reliability of 3D microelectronic packages. Through experimentally-measured strain fields, thermal cycling tests, and simulations, design guidelines are developed to enhance the thermomechanical reliability of TSVs used in future 3D microelectronic packages.
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Natu, Nitish Umesh. "Design and prototyping of temperature resilient clock distribution networks." Thesis, Georgia Institute of Technology, 2014. http://hdl.handle.net/1853/51812.
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Clock Distribution Networks play a vital role in performance and reliability of a system. However, temperature gradients observed in 3D ICs hamper the functionality of CDNs in terms of varying skew and propagation delay. This thesis presents two compensation techniques, Adaptive Voltage and Controllable Delay, to overcome these problems. The compensation methods are validated using a FPGA-based test vehicle. Modification in traditional buffer design are also presented and the performance as well as the area and power overhead of both the implementations is compared.
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Ramachandran, Koushik. "Conductive anodic filament reliability of fine-pitch through-vias in organic packaging substrates." Diss., Georgia Institute of Technology, 2013. http://hdl.handle.net/1853/50228.
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This research reports for the first time conductive anodic filament reliability of copper plated-through-vias with spacing of 75 – 200 µm in thin glass fiber reinforced organic packaging substrates with advanced epoxy-based and cyclo-olefin polymer resin systems. Reliability studies were conducted in halogenated and halogen-free substrates with improved test structure designs including different conductor spacing and geometry. Accelerated test condition (temperature, humidity and DC bias voltage) was used to investigate the effect of conductor spacing and substrate material influence on insulation reliability behavior. Characterization studies included gravimetric measurement of moisture sorption, extractable ion content analysis, electrical resistance measurement, impedance spectroscopy measurement, optical microscopy and scanning electron microscopy analysis and elemental characterization using energy dispersive x-ray spectroscopy. The accelerated test results and characterization studies indicated a strong dependence of insulation failures on substrate material system, conductor spacing and geometry. This study presents advancements in the understanding of failure processes and chemical nature of failures in fine-pitch copper plated-through-vias in newly developed organic substrates and demonstrates potential methods to mitigate failures for high density organic packages.
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Hua, Hao. "Design and verification methodology for complex three-dimensional digital integrated circuit." 2006. http://www.lib.ncsu.edu/theses/available/etd-06012006-102436/unrestricted/etd.pdf.
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Chang, Yao-Jen, and 張耀仁. "Three-Dimensional Integrated Circuit Key Technology: Metal to Polymer Hybrid Bonding." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/b8ejgu.
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碩士<br>國立交通大學<br>電子研究所<br>100<br>The main topics of this thesis include electrical characterization and reliability investigation of metal to polymer hybrid bonding in three-dimensional integrated circuit. Hybrid bonding is one of the most important technologies in 3D-ICs because of dielectric polymer and metal can provide reinforcement of bonding strength and electrical interconnection simultaneously. Cu/Sn micro-bumps and BCB (benezocy-clobutene) were adopted and optimized to form metallization and dielectric material for hybrid bonding. As the result, a wafer-level three-dimensional integration scheme with Cu TSVs, based on face-to- face and Cu/Sn micro-bumps to BCB low temperature hybrid bonding, was demonstrated. The main process flow includes the sequence of Cu TSV formation, Cu/Sn and BCB development, hybrid bonding, wafer thinning and backside re-distribution metal layer. Kelvin structure and daisy chain design were fabricated for electrical characterization and stability evaluation. Reliability tests such as current stressing and humidity test were performed without deterioration, showing good sealing ability of BCB. The results of Kelvin structure for 10μm TSV are 49.3 mΩ for 5μm TSV and 12.6 mΩ, indicating excellent electrical characterization to allow the possibility of future mass production for 3D IC area.