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Journal articles on the topic 'Three-dimensional integrated circuit'

Author: Grafiati

Published: 4 June 2021

Last updated: 10 February 2022

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1

Koo, Jae-Mo, Sungjun Im, Linan Jiang, and Kenneth E. Goodson. "Integrated Microchannel Cooling for Three-Dimensional Electronic Circuit Architectures." Journal of Heat Transfer 127, no. 1 (2005): 49–58. http://dx.doi.org/10.1115/1.1839582.

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The semiconductor community is developing three-dimensional circuits that integrate logic, memory, optoelectronic and radio-frequency devices, and microelectromechanical systems. These three-dimensional (3D) circuits pose important challenges for thermal management due to the increasing heat load per unit surface area. This paper theoretically studies 3D circuit cooling by means of an integrated microchannel network. Predictions are based on thermal models solving one-dimensional conservation equations for boiling convection along microchannels, and are consistent with past data obtained from straight channels. The model is combined within a thermal resistance network to predict temperature distributions in logic and memory. The calculations indicate that a layer of integrated microchannel cooling can remove heat densities up to 135W/cm2 within a 3D architecture with a maximum circuit temperature of 85°C. The cooling strategy described in this paper will enable 3D circuits to include greater numbers of active levels while exposing external surface area for functional signal transmission.

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2

Zeping Zhao, Zeping Zhao, Jiaojiao Wang Jiaojiao Wang, Xueyan Han Xueyan Han, Zhike Zhang Zhike Zhang, and Jianguo Liu Jianguo Liu. "Ultra-compact four-lane hybrid-integrated ROSA based on three-dimensional microwave circuit design." Chinese Optics Letters 17, no. 3 (2019): 030401. http://dx.doi.org/10.3788/col201917.030401.

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3

Hübler, A. C., G. C. Schmidt, H. Kempa, K. Reuter, M. Hambsch, and M. Bellmann. "Three-dimensional integrated circuit using printed electronics." Organic Electronics 12, no. 3 (2011): 419–23. http://dx.doi.org/10.1016/j.orgel.2010.12.010.

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4

Wilson, R. Mark. "The carbon nanotube integrated circuit goes three-dimensional." Physics Today 70, no. 9 (2017): 14–16. http://dx.doi.org/10.1063/pt.3.3680.

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5

Akasaka, Yoichi. "Three-dimensional integrated circuit: technology and application prospect." Microelectronics Journal 20, no. 1-2 (1989): 105–12. http://dx.doi.org/10.1016/0026-2692(89)90125-0.

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6

Wang, Kang-Jia, and Zhong-Liang Pan. "Integrated microchannel cooling in a three dimensional integrated circuit: A thermal management." Thermal Science 20, no. 3 (2016): 899–902. http://dx.doi.org/10.2298/tsci1603899w.

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Microchannel cooling is a promising technology for solving the three-dimensional integrated circuit thermal problems. However, the relationship between the microchannel cooling parameters and thermal behavior of the three dimensional integrated circuit is complex and difficult to understand. In this paper, we perform a detailed evaluation of the influence of the microchannel structure and the parameters of the cooling liquid on steady-state temperature profiles. The results presented in this paper are expected to aid in the development of thermal design guidelines for three dimensional integrated circuit with microchannel cooling.

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7

Fourie, Coenrad J., Olaf Wetzstein, Thomas Ortlepp, and Jürgen Kunert. "Three-dimensional multi-terminal superconductive integrated circuit inductance extraction." Superconductor Science and Technology 24, no. 12 (2011): 125015. http://dx.doi.org/10.1088/0953-2048/24/12/125015.

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8

Tianming, Ni, Chang Hao, Zhang Xiaoqiang, Xiao Hao, and Huang Zhengfeng. "Research on physical unclonable functions circuit based on three dimensional integrated circuit." IEICE Electronics Express 15, no. 23 (2018): 20180782. http://dx.doi.org/10.1587/elex.15.20180782.

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9

Kokubun, Y., T. Baba, and K. Iga. "Silicon optical printed circuit board for three-dimensional integrated optics." Electronics Letters 21, no. 11 (1985): 508–9. http://dx.doi.org/10.1049/el:19850360.

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10

Wu, Banqiu, and Ajay Kumar. "Extreme ultraviolet lithography and three dimensional integrated circuit—A review." Applied Physics Reviews 1, no. 1 (2014): 011104. http://dx.doi.org/10.1063/1.4863412.

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11

Shimomura, Kei, Makoto Hirose, and Yukio Takahashi. "Multislice imaging of integrated circuits by precession X-ray ptychography." Acta Crystallographica Section A Foundations and Advances 74, no. 1 (2018): 66–70. http://dx.doi.org/10.1107/s205327331701525x.

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A method for nondestructively visualizing multisection nanostructures of integrated circuits by X-ray ptychography with a multislice approach is proposed. In this study, tilt-series ptychographic diffraction data sets of a two-layered circuit with a ∼1.4 µm gap at nine incident angles are collected in a wideQrange and then artifact-reduced phase images of each layer are successfully reconstructed at ∼10 nm resolution. The present method has great potential for the three-dimensional observation of flat specimens with thickness on the order of 100 µm, such as three-dimensional stacked integrated circuits based on through-silicon vias, without laborious sample preparation.

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12

Nishikawa, Kenjiro, Ichihiko Toyoda, Kenji Kamogawa, Tsuneo Tokumitsu, and Masayoshi Tanaka. "Three-dimensional monolithic microwave integrated circuit technology for fully computer-aided design-compatible monolithic microwave integrated circuit development." International Journal of RF and Microwave Computer-Aided Engineering 8, no. 6 (1998): 498–506. http://dx.doi.org/10.1002/(sici)1099-047x(199811)8:6<498::aid-mmce9>3.0.co;2-e.

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13

Chen, Y. J., T. L. Yang, J. J. Yu, C. L. Kao, and C. R. Kao. "Gold and palladium embrittlement issues in three-dimensional integrated circuit interconnections." Materials Letters 110 (November 2013): 13–15. http://dx.doi.org/10.1016/j.matlet.2013.07.078.

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14

Fujimori, Yoshihiko, Takashi Tsuto, Hiroyuki Tsukamoto, Kazuya Okamoto, and Kyoichi Suwa. "Macroinspection methodology for through silicon via array in three-dimensional integrated circuit." Journal of Micro/Nanolithography, MEMS, and MOEMS 13, no. 1 (2014): 011204. http://dx.doi.org/10.1117/1.jmm.13.1.011204.

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15

Zhang, Jing. "Modeling of Thermally Induced Stresses in Three-Dimensional Bonded Integrated Circuit Wafers." Journal of Electronic Materials 40, no. 5 (2011): 670–73. http://dx.doi.org/10.1007/s11664-010-1502-z.

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16

Chen, Chiao-Wen, Tsung-Chieh Chiu, Ying-Ta Chiu, Chiu-Wen Lee, and Kwang-Lung Lin. "Current induced segregation of intermetallic compounds in three-dimensional integrated circuit microbumps." Intermetallics 85 (June 2017): 117–24. http://dx.doi.org/10.1016/j.intermet.2017.02.012.

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17

Dong Gang, Wu Wen-Shan, and Yang Yin-Tang. "Stack-through silicon via dynamic power consumption optimization in three-dimensional integrated circuit." Acta Physica Sinica 64, no. 2 (2015): 026601. http://dx.doi.org/10.7498/aps.64.026601.

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18

Chan, V. W. C., P. C. H. Chan, and Mansun Chan. "Three-dimensional CMOS SOI integrated circuit using high-temperature metal-induced lateral crystallization." IEEE Transactions on Electron Devices 48, no. 7 (2001): 1394–99. http://dx.doi.org/10.1109/16.930657.

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19

Su, Fei, Kerm Sin Chian, Sung Yi, and Fulong Dai. "Development and instrumentation of an integrated three–dimensional optical testing system for application in integrated circuit packaging." Review of Scientific Instruments 76, no. 9 (2005): 093109. http://dx.doi.org/10.1063/1.2042647.

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20

Yan, Haixia, Qiang Zhou, Xianlong Hong, and Zhuoyuan Li. "Efficient hierarchical algorithm for mixed mode placement in three dimensional integrated circuit chip designs." Tsinghua Science and Technology 14, no. 2 (2009): 161–69. http://dx.doi.org/10.1016/s1007-0214(09)70025-2.

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21

Yarbrough, A. D., G. C. Dalman, and C. A. Lee. "Fabrication techniques for a novel three-dimensional monolithic integrated circuit transmission line in silicon." Electronics Letters 24, no. 25 (1988): 1533. http://dx.doi.org/10.1049/el:19881046.

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22

Hsu, Hao, Tzu-Yang Lin, and Fan-Yi Ouyang. "Evaluation of Electromigration Behaviors of Pb-Free Microbumps in Three-Dimensional Integrated Circuit Packaging." Journal of Electronic Materials 43, no. 1 (2013): 236–46. http://dx.doi.org/10.1007/s11664-013-2840-4.

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23

Bardt, Jeffrey A., Gerald R. Bourne, Tony L. Schmitz, John C. Ziegert, and W. Gregory Sawyer. "Micromolding three-dimensional amorphous metal structures." Journal of Materials Research 22, no. 2 (2007): 339–43. http://dx.doi.org/10.1557/jmr.2007.0035.

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In this article, we report a simple and inexpensive approach to micromolding of complex, three-dimensional, high aspect ratio structures (with non-line-of-sight features) out of a high-strength amorphous metal. Inexpensive sacrificial silicon molds were created using lithography and etching techniques originally developed for integrated circuit production by the microelectronics industry and later adopted for microelectromechanical (MEMS) manufacturing. Multiple silicon layers were stacked, and the metallic glass was forced into the cavities under heat and pressure in an open air environment. Following cooling, the metallic structures were released by etching the silicon away in a potassium hydroxide (KOH) bath. Process studies showed that temperature is the most significant variable governing mold-filling. Transmission electron microscopy (TEM) sections of the mold/glass interface showed successful replication of features with characteristic dimensions on the order of 10 nanometers and no discernible gap between the silicon and the metallic glass. This scalable micromolding process leverages the inexpensive and readily available aspects of silicon lithography to economically support the mass customization (low volume production) of metal microcomponents without elaborate infrastructure needs.

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24

Liou, Jian-Chiun, and Fan-Gang Tseng. "Three-Dimensional Architecture of Multiplexing Data Registration Integrated Circuit for Large-Array Ink Jet Printhead." Journal of Imaging Science and Technology 52, no. 1 (2008): 010508. http://dx.doi.org/10.2352/j.imagingsci.technol.(2008)52:1(010508).

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25

Watanabe, Naoya, Motohiro Suzuki, Kenji Kawano, Michiyuki Eto, and Masahiro Aoyagi. "Fabrication of a membrane probe card using transparent film for three-dimensional integrated circuit testing." Japanese Journal of Applied Physics 53, no. 6S (2014): 06JM06. http://dx.doi.org/10.7567/jjap.53.06jm06.

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26

Chang, Y. W., Chih Chen, T. C. Chang, C. J. Zhan, J. Y. Juang та Annie T. Huang. "Fast phase transformation due to electromigration of 18μm microbumps in three-dimensional integrated-circuit integration". Materials Letters 137 (грудень 2014): 136–38. http://dx.doi.org/10.1016/j.matlet.2014.08.156.

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27

Petrosyants, Konstantin O., and Nikita I. Ryabov. "Quasi-3D Thermal Simulation of Integrated Circuit Systems in Packages." Energies 13, no. 12 (2020): 3054. http://dx.doi.org/10.3390/en13123054.

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The problem of thermal modeling of modern three-dimensional (3D) integrated circuit (IC) systems in packages (SiPs) is discussed. An effective quasi-3D (Q3D) approach of thermal design is proposed taking into account the specific character of 3D IC stacked multilayer constructions. The fully-3D heat transfer equation for global multilayer construction is reduced to the set of coupled two-dimensional (2D) equations for separate construction layers. As a result, computational difficulties, processor time, and RAM volume are significantly reduced, while accuracy can be provided. A software tool, Overheat-3D-IC, was developed on the base of the generalized Q3D package numerical model. For the first time, the global 3D thermal performances across the modern integrated circuit/through-silicon via/ball grid array (IC-TSV-BGA) and multi-chip (MC)-embedded printed circuit board (PCB) packages were simulated. A ten times decrease of central processing unit (CPU) time was achieved as compared with the 3D solutions obtained by commercial universal 3D simulators, while saving the sufficient accuracy. The simulation error of maximal temperature TMAX determination for different types of packages was not more than 10–20%.

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28

Lin, Shawn-Yu, J. G. Fleming, and E. Chow. "Two- and Three-Dimensional Photonic Crystals Built with VLSI Tools." MRS Bulletin 26, no. 8 (2001): 627–31. http://dx.doi.org/10.1557/mrs2001.157.

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The drive toward miniature photonic devices has been hindered by our inability to tightly control and manipulate light. Moreover, photonics technologies are typically not based on silicon and, until recently, only indirectly benefited from the rapid advances being made in silicon processing technology. In the first part of this article, the successful fabrication of three-dimensional (3D) photonic crystals using silicon processing will be discussed. This advance has been made possible through the use of integrated-circuit (IC) fabrication technologies (e.g., very largescale integration, VLSI) and may enable the penetration of Si processing into photonics. In the second part, we describe the creation of 2D photonic-crystal slabs operating at the λ = 1.55 μm communications wavelength. This class of 2D photonic crystals is particularly promising for planar on-chip guiding, trapping, and switching of light.

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29

Wang, Fengjuan, and Ningmei Yu. "Thermal management of coaxial through-silicon-via (C-TSV)-based three-dimensional integrated circuit (3D IC)." IEICE Electronics Express 13, no. 11 (2016): 20151117. http://dx.doi.org/10.1587/elex.13.20151117.

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30

Kim, Namjae, and Shiho Kim. "Self-Convectional Three-Dimensional Integrated Circuit Cooling System using Micro Flat Heat Pipe for Portable Devices." Heat Transfer Engineering 35, no. 10 (2013): 924–32. http://dx.doi.org/10.1080/01457632.2014.859514.

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31

Hubbard, Joshua D., Ruben Acevedo, Kristen M. Edwards, et al. "Fully 3D-printed soft robots with integrated fluidic circuitry." Science Advances 7, no. 29 (2021): eabe5257. http://dx.doi.org/10.1126/sciadv.abe5257.

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The emergence of soft robots has presented new challenges associated with controlling the underlying fluidics of such systems. Here, we introduce a strategy for additively manufacturing unified soft robots comprising fully integrated fluidic circuitry in a single print run via PolyJet three-dimensional (3D) printing. We explore the efficacy of this approach for soft robots designed to leverage novel 3D fluidic circuit elements—e.g., fluidic diodes, “normally closed” transistors, and “normally open” transistors with geometrically tunable pressure-gain functionalities—to operate in response to fluidic analogs of conventional electronic signals, including constant-flow [“direct current (DC)”], “alternating current (AC)”–inspired, and preprogrammed aperiodic (“variable current”) input conditions. By enabling fully integrated soft robotic entities (composed of soft actuators, fluidic circuitry, and body features) to be rapidly disseminated, modified on demand, and 3D-printed in a single run, the presented design and additive manufacturing strategy offers unique promise to catalyze new classes of soft robots.

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32

Tang, Siqi, Jiang Yan, Jing Zhang, et al. "Fabrication of Low Cost and Low Temperature Poly-Silicon Nanowire Sensor Arrays for Monolithic Three-Dimensional Integrated Circuits Applications." Nanomaterials 10, no. 12 (2020): 2488. http://dx.doi.org/10.3390/nano10122488.

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In this paper, the poly-Si nanowire (NW) field-effect transistor (FET) sensor arrays were fabricated by adopting low-temperature annealing (600 °C/30 s) and feasible spacer image transfer (SIT) processes for future monolithic three-dimensional integrated circuits (3D-ICs) applications. Compared with other fabrication methods of poly-Si NW sensors, the SIT process exhibits the characteristics of highly uniform poly-Si NW arrays with well-controlled morphology (about 25 nm in width and 35 nm in length). Conventional metal silicide and implantation techniques were introduced to reduce the parasitic resistance of source and drain (SD) and improve the conductivity. Therefore, the obtained sensors exhibit >106 switching ratios and 965 mV/dec subthreshold swing (SS), which exhibits similar results compared with that of SOI Si NW sensors. However, the poly-Si NW FET sensors show the Vth shift as high as about 178 ± 1 mV/pH, which is five times larger than that of the SOI Si NW sensors. The fabricated poly-Si NW sensors with 600 °C/30 s processing temperature and good device performance provide feasibility for future monolithic three-dimensional integrated circuit (3D-IC) applications.

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33

Sun, Wookyung, Sujin Choi, Bokyung Kim, and Junhee Park. "Three-Dimensional (3D) Vertical Resistive Random-Access Memory (VRRAM) Synapses for Neural Network Systems." Materials 12, no. 20 (2019): 3451. http://dx.doi.org/10.3390/ma12203451.

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Memristor devices are generally suitable for incorporation in neuromorphic systems as synapses because they can be integrated into crossbar array circuits with high area efficiency. In the case of a two-dimensional (2D) crossbar array, however, the size of the array is proportional to the neural network’s depth and the number of its input and output nodes. This means that a 2D crossbar array is not suitable for a deep neural network. On the other hand, synapses that use a memristor with a 3D structure are suitable for implementing a neuromorphic chip for a multi-layered neural network. In this study, we propose a new optimization method for machine learning weight changes that considers the structural characteristics of a 3D vertical resistive random-access memory (VRRAM) structure for the first time. The newly proposed synapse operating principle of the 3D VRRAM structure can simplify the complexity of a neuron circuit. This study investigates the operating principle of 3D VRRAM synapses with comb-shaped word lines and demonstrates that the proposed 3D VRRAM structure will be a promising solution for a high-density neural network hardware system.

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34

Kapoor, Dipesh, Cher Ming Tan, and Vivek Sangwan. "Evaluation of the Potential Electromagnetic Interference in Vertically Stacked 3D Integrated Circuits." Applied Sciences 10, no. 3 (2020): 748. http://dx.doi.org/10.3390/app10030748.

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Advancements in the functionalities and operating frequencies of integrated circuits (IC) have led to the necessity of measuring their electromagnetic Interference (EMI). Three-dimensional integrated circuit (3D-IC) represents the current advancements for multi-functionalities, high speed, high performance, and low-power IC technology. While the thermal challenges of 3D-IC have been studied extensively, the influence of EMI among the stacked dies has not been investigated. With the decreasing spacing between the stacked dies, this EMI can become more severe. This work demonstrates the potential of EMI within a 3D-IC numerically, and determines the minimum distance between stack dies to reduce the impact of EMI from one another before they are fabricated. The limitations of using near field measurement for the EMI study in stacked dies 3D-IC are also illustrated.

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35

Heck, Martijn J. R. "Highly integrated optical phased arrays: photonic integrated circuits for optical beam shaping and beam steering." Nanophotonics 6, no. 1 (2017): 93–107. http://dx.doi.org/10.1515/nanoph-2015-0152.

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AbstractTechnologies for efficient generation and fast scanning of narrow free-space laser beams find major applications in three-dimensional (3D) imaging and mapping, like Lidar for remote sensing and navigation, and secure free-space optical communications. The ultimate goal for such a system is to reduce its size, weight, and power consumption, so that it can be mounted on, e.g. drones and autonomous cars. Moreover, beam scanning should ideally be done at video frame rates, something that is beyond the capabilities of current opto-mechanical systems. Photonic integrated circuit (PIC) technology holds the promise of achieving low-cost, compact, robust and energy-efficient complex optical systems. PICs integrate, for example, lasers, modulators, detectors, and filters on a single piece of semiconductor, typically silicon or indium phosphide, much like electronic integrated circuits. This technology is maturing fast, driven by high-bandwidth communications applications, and mature fabrication facilities. State-of-the-art commercial PICs integrate hundreds of elements, and the integration of thousands of elements has been shown in the laboratory. Over the last few years, there has been a considerable research effort to integrate beam steering systems on a PIC, and various beam steering demonstrators based on optical phased arrays have been realized. Arrays of up to thousands of coherent emitters, including their phase and amplitude control, have been integrated, and various applications have been explored. In this review paper, I will present an overview of the state of the art of this technology and its opportunities, illustrated by recent breakthroughs.

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36

Lee, Chang-Chun, Yu-Min Lin, Chia-Ping Hsieh, et al. "Assembly technology development and failure analysis for three-dimensional integrated circuit integration with ultra-thin chip stacking." Microelectronic Engineering 156 (April 2016): 24–29. http://dx.doi.org/10.1016/j.mee.2016.01.040.

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37

Mossa, Siraj Fulum, Syed Rafay Hasan, and Omar Sayed Ahmed Elkeelany. "Grouped through silicon vias for lower L d i /d t drop in three‐dimensional integrated circuit." IET Circuits, Devices & Systems 10, no. 1 (2016): 44–53. http://dx.doi.org/10.1049/iet-cds.2015.0065.

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38

Sabbavarapu, Srinivas, Amit Acharyya, P. Balasubramanian, and C. Ramesh Reddy. "Fast 3D Integrated Circuit Placement Methodology using Merging Technique." Defence Science Journal 69, no. 3 (2019): 217–22. http://dx.doi.org/10.14429/dsj.69.14410.

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In the recent years the advancement in the field of microelectronics integrated circuit (IC) design technologies proved to be a boon for design and development of various advanced systems in-terms of its reduction in form factor, low power, high speed and with increased capacity to incorporate more designs. These systems provide phenomenal advantage for armoured fighting vehicle (AFV) design to develop miniaturised low power, high performance sub-systems. One such emerging high-end technology to be used to develop systems with high capabilities for AFVs is discussed in this paper. Three dimensional IC design is one of the emerging field used to develop high density heterogeneous systems in a reduced form factor. A novel grouping based partitioning and merge based placement (GPMP) methodology for 3D ICs to reduce through silicon vias (TSVs) count and placement time is proposed. Unlike state-of-the-art techniques, the proposed methodology does not suffer from initial overlap of cells during intra-layer placement which reduces the placement time. Connectivity based grouping and partitioning ensures less number of TSVs and merge based placement further reduces intra layer wire-length. The proposed GPMP methodology has been extensively against the IBMPLACE database and performance has been compared with the latest techniques resulting in 12 per cent improvement in wire-length, 13 per cent reduction in TSV and 1.1x improvement in placement time.

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Cheng, Chuantong, Beiju Huang, Xurui Mao, et al. "Monolithic optoelectronic integrated broadband optical receiver with graphene photodetectors." Nanophotonics 6, no. 6 (2017): 1343–52. http://dx.doi.org/10.1515/nanoph-2017-0023.

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AbstractOptical receivers with potentially high operation bandwidth and low cost have received considerable interest due to rapidly growing data traffic and potential Tb/s optical interconnect requirements. Experimental realization of 65 GHz optical signal detection and 262 GHz intrinsic operation speed reveals the significance role of graphene photodetectors (PDs) in optical interconnect domains. In this work, a novel complementary metal oxide semiconductor post-backend process has been developed for integrating graphene PDs onto silicon integrated circuit chips. A prototype monolithic optoelectronic integrated optical receiver has been successfully demonstrated for the first time. Moreover, this is a firstly reported broadband optical receiver benefiting from natural broadband light absorption features of graphene material. This work is a perfect exhibition of the concept of monolithic optoelectronic integration and will pave way to monolithically integrated graphene optoelectronic devices with silicon ICs for three-dimensional optoelectronic integrated circuit chips.

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40

Huang, Lei, Shibin Shen, Fei Xie, Jing Zhao, Jianing Han, and Kai Feng. "A Novel Multi-Pattern Solder Joint Simultaneous Segmentation Algorithm for PCB Selective Packaging Systems." International Journal of Pattern Recognition and Artificial Intelligence 33, no. 13 (2019): 2058005. http://dx.doi.org/10.1142/s0218001420580057.

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To prevent any negative electromagnetic influence of high-density integrated circuits, an insulation package needs to be specially designed to shield it. Aiming at the low efficiency and material waste in traditional packaging methods, a printed circuit board (PCB) selective packaging system based on a multi-pattern solder joint simultaneous segmentation algorithm and three-dimensional printing technology is introduced in this paper. Firstly, the structure of PCB selective packaging system is designed. Secondly, to solve the existing problems, such as multi-pattern solder joints which are located densely in small welding areas and are hard to be extracted in the small-area integrated circuit board, a multi-pattern solder joint simultaneous segmentation algorithm is developed based on (geometrical) neighborhood features to extract and locate the optimal PCB solder joint areas. Finally, tests using three actual PCB are carried out to compare the proposed method with traditional multi-threshold solder joint extraction methods. Test results indicate that the proposed algorithm is simple and effective. Diverse solder joints can be optimally located and simultaneously extracted from the collected PCB image, which greatly improves the filling rate of the solder joint areas and filters out false pixels. Thus, this method provides a reliable location-finding tool to help place solder points in PCB selective packaging systems.

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41

Kim, Youn-Jang, Jae-Hong Lim, and Kyeong-Keun Choi. "Study of Bonded Wafers by Using a Synchrotron Radiation Transmission X-ray Microscopy for Three-Dimensional Integrated Circuit." Journal of Nanoelectronics and Optoelectronics 15, no. 7 (2020): 904–8. http://dx.doi.org/10.1166/jno.2020.2770.

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Synchrotron radiation transmission X-ray microscopy (SRTXM) was applied for visualization of the interfacial layer in bonded wafer pairs. The X-ray energy of 6.54 keV with a monitoring window was utilized to enhance a resolution of transmission X-ray microscopy (TXM). The monitoring window was designed a locally uncovered area of the bonded wafer pairs to make the thickness of bonded wafers less than 200 μm. The experimental results showed that the technique has sub-micron meter resolution. Also this technique can improve the resolution of the synchrotron X-ray for nanoelectronics application.

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42

Choobineh, Leila, and Ankur Jain. "An explicit analytical model for rapid computation of temperature field in a three-dimensional integrated circuit (3D IC)." International Journal of Thermal Sciences 87 (January 2015): 103–9. http://dx.doi.org/10.1016/j.ijthermalsci.2014.08.012.

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43

Onga, S., S. Kambayashi, M. Yoshimi, K. Natori та M. Kashiwagi. "9.5×9.5mm2 - Area recrystallization, 6μm-viahole filling and thin CMOS SOI designing for realizing three-dimensional integrated circuit". Microelectronic Engineering 15, № 1-4 (1991): 175–78. http://dx.doi.org/10.1016/0167-9317(91)90206-s.

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44

Li, Bing-Jie, Zhen-Song Li, Yan-Ping Zhao, Zheng-Wang Li, and Min Miao. "Modeling and Optimization Design of Signal Interconnect Channel Considering Signal Integrity in Three Dimensional Integrated Circuits." Journal of Nanoelectronics and Optoelectronics 16, no. 5 (2021): 773–80. http://dx.doi.org/10.1166/jno.2021.2999.

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The signal integrity (SI) analysis of a high-speed signal interconnect channel composed of through silicon vias (TSVs) and horizontal re-distribution layers (RDL) is carried out, and the problems of SI, such as transmission loss, crosstalk and coupling effect in the transmission channel, are analyzed and studied. These signal integrity issues are considered in this paper, a signal interconnect channel model is proposed and the equivalent circuit model is deduced as well. Compared with the traditional one, this interconnect channel model has better performance in SI. Further sweep frequency analysis is carried out for different material parameters to achieve signal transmission performance optimization aimed at this model. Test samples of the proposed signal interconnect channel model are designed and fabricated according to the process index, and measured to verify the actual transmission performance. The design and optimization rule of high-speed signal interconnect channel are summarized which proved that the proposed structure has more advantages in signal transmission performance, and has important guiding significance for practical design.

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Bachnak, Nouhad. "MEMS Packaging with 3D-MID Technology." International Symposium on Microelectronics 2011, no. 1 (2011): 000484–90. http://dx.doi.org/10.4071/isom-2011-wa1-paper6.

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3D-MID (three dimensional molded interconnect devices) technology (which is already broadly used for 3D-MID mobile phone antennas) is also used for MEMS packaging and sensors applications. 3D-MID allows miniaturization by the integration of mechanical and electronic functions in one part. The 3D electronic circuit is integrated into a 3D plastic casing or carrier, making it possible to achieve much more compact construction and much greater function density. More and more applications involving electrical and electro-optical circuits are made using 3D-MID technology. Typical 3D-MID applications are: Sensor packaging, LED packaging, security casings, RFIDs and Antennas. The main areas of application are in the automotive, medical, industrial technology and telecommunications sectors.

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Van Asselt, Robert L., and Heinrich Becker. "Development of accurate linewidth measurement techniques for in-process wafers." Proceedings, annual meeting, Electron Microscopy Society of America 46 (1988): 54–55. http://dx.doi.org/10.1017/s0424820100102353.

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Measurements of the device geometries on “in-process” wafers present some interesting challenges. Sample coating is not possible and the measurement probe must not damage the devices. The Scanning Electron Microscope (SEM) is the standard tool for submicrometer measurements. However, operating at the low electron beam accelerating voltage required to avoid damage to integrated circuits introduces problems in resolution. Also, the measurement accuracy may be limited by the effects of surface charging and topography. Further, SEM linewidth standards do not exist at the present time. Optical measurements are attractive because, in general, they display greater precision, are typically less expensive to implement and have a higher throughput. However, diffraction effects associated with the complex three-dimensional geometries of integrated circuit structures make accurate measurements very difficult. The "blur" regions that occur in the optical image at each edge must be interpreted to predict the actual location of the structure edges.

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Kuang, Ye, Lan Yao, Sheng-Hai Yu, Shuo Tan, Xiu-Jun Fan, and Yi-Ping Qiu. "Design and Electromagnetic Properties of a Conformal Ultra Wideband Antenna Integrated in Three-Dimensional Woven Fabrics." Polymers 10, no. 8 (2018): 861. http://dx.doi.org/10.3390/polym10080861.

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Wearable antennas play an important role in transmitting signals wirelessly in body-worn systems, helping body-worn applications to achieve real-time monitoring and improving the working efficiency as well as the life quality of the users. Over conventional antenna types, ultra wideband (UWB) antennas have advantages of very large operating bandwidth, low power consumption, and high data transmission speed, therefore, they become of great interest for body-worn applications. One of the strategies for making the antenna comfortable to wear is replacing the conventional rigid printed circuit board with textile materials in the manufacturing process. In this study, a novel three-dimensional woven fabric integrated UWB antenna was proposed and fabricated with pure textile materials. The antenna electromagnetic properties were simulated and measured and its properties under bending were investigated. The antenna operated in a wide bandwidth from 2.7 to 13 GHz with the proper radiation pattern and gain value. At the same time, the antenna performance under bending varied in a reasonable range indicating that the antenna is prospectively applied on the curved surfaces of the human body. Additionally, the current distribution of the antenna showed that different conductive parts had different current densities indicating the uniqueness of the three-dimensional textile-based antenna.

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Shi, Bing, Ankur Srivastava, and Avram Bar‐Cohen. "Co‐design of micro‐fluidic heat sink and thermal through‐silicon‐vias for cooling of three‐dimensional integrated circuit." IET Circuits, Devices & Systems 7, no. 5 (2013): 223–31. http://dx.doi.org/10.1049/iet-cds.2013.0026.

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Yao, Mingjun, Jun Fan, Ning Zhao, Zhiyi Xiao, Daquan Yu, and Haitao Ma. "Simplified low-temperature wafer-level hybrid bonding using pillar bump and photosensitive adhesive for three-dimensional integrated circuit integration." Journal of Materials Science: Materials in Electronics 28, no. 12 (2017): 9091–95. http://dx.doi.org/10.1007/s10854-017-6642-y.

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Ye, Lei, Jian Li, Hui Zhang, Dongmei Liang, and Zhuochen Wang. "An Integrated Front-end Circuit Board for Air-Coupled CMUT Burst-Echo Imaging." Sensors 20, no. 21 (2020): 6128. http://dx.doi.org/10.3390/s20216128.

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To conduct burst-echo imaging with air-coupled capacitive micromachined ultrasonic transducers (CMUTs) using the same elements in transmission and reception, this work proposes a dedicated and integrated front-end circuit board design to build an imaging system. To the best of the authors’ knowledge, this is the first air-coupled CMUT burst-echo imaging using the same elements in transmission and reception. The reported front-end circuit board, controlled by field programmable gate array (FPGA), consisted of four parts: an on-board pulser, a bias-tee, a T/R switch and an amplifier. Working with our 217 kHz 16-element air-coupled CMUT array under 100 V DC bias, the front-end circuit board and imaging system could achieve 22.94 dB signal-to-noise ratio (SNR) in burst-echo imaging in air, which could represent the surface morphology and the three-dimensional form factor of the target. In addition, the burst-echo imaging range of our air-coupled CMUT imaging system, which could work between 52 and 273 mm, was discussed. This work suggests good potential for ultrasound imaging and gesture recognition applications.

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