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Journal articles on the topic 'TSPC logic'

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Published: 4 June 2025

Last updated: 15 July 2025

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CHENG, KUO-HSING, SHUN-WEN CHENG, and WEN-SHIUAN LEE. "64-BIT PIPELINE CARRY LOOKAHEAD ADDER USING ALL-N-TRANSISTOR TSPC LOGICS." Journal of Circuits, Systems and Computers 15, no. 01 (2006): 13–27. http://dx.doi.org/10.1142/s0218126606002915.

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This paper proposes two improved circuit techniques of True Single-Phase Clocking (TSPC) logic, which called Nonfull Swing TSPC (NSTSPC) and All-N-TSPC (ANTSPC). The voltage of internal node of the NSTSPC is not full swing; it saves partial dynamic power dissipation. And the ANTSPC uses NMOS transistors to replace PMOS transistors, the output loading of Φ-section is therefore reduced and a higher layout density is obtained. Through postlayout simulation comparisons between number of stacked MOS transistors and delay time, and supply voltage vs maximum frequency, the proposed NSTSPC and ANTSPC circuits show better operation speed and power performance than the conventional TSPC circuit. Finally, the new TSPC circuits are applied to a 64-bit hierarchical pipeline Carry Lookahead Adder (CLA), which based on TSMC 0.35 μm CMOS process technology. By using the techniques of NSTSPC and ANTSPC alternately, the 64-bit CLA is successfully implemented as a pipelined structure. The results of post-layout simulation show that the 64-bit CLA can be operated on 1.25 GHz clock frequency and its power/maximal frequency ratio is 151.4 μW/MHz.

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Gyawali, Yadu Prasad, and Mohit Angurala. "Design of Frequency Divider (FD/2 and FD 2/3) Circuits for a Phase Locked Loop." International Journal on Future Revolution in Computer Science & Communication Engineering 8, no. 1 (2022): 27–31. http://dx.doi.org/10.17762/ijfrcsce.v8i1.2103.

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This paper reports on three design of Frequency Divider (FD/2) and Frequency Divider (FD 2/3) circuits. Tanner EDA tool developed on 130nm CMOS technology with a voltage supply of 1.3 V is used to build, model, and compare all circuits. For the FD/2 circuit, E-TSPC Pass Transistor logic uses 1.77 µW, whereas TSPC logic consumes 5.57 µW for the FD 2/3 circuit. It implies that the TSPC logic is the best solution since it meets the speed and power consumption requirements.

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Klekotko, A., M. Baszczyk, S. Biereigel, et al. "Radiation hard true single-phase-clock logic for high-speed circuits in 28 nm CMOS." Journal of Instrumentation 18, no. 02 (2023): C02068. http://dx.doi.org/10.1088/1748-0221/18/02/c02068.

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Abstract True Single-Phase-Clock (TSPC) dynamic logic is widely used in high-speed circuits such as high-speed SERDES (Serializer/Deserializer) and frequency dividers. TSPC flip-flops (FF) are known for their high operational speed and low power consumption, compared to static FFs. Due to the relatively high leakage currents in modern CMOS processes, the use of leakage protection techniques of the storage nodes in TSPC must be considered, especially at high radiation doses. In this paper, the limitations originating from Total Ionization Dose (TID)-induced subthreshold leakage currents are analysed and radiation-hardening-by-design (RHBD) circuit techniques are proposed. Additionally, Single Event Upsets (SEU) are investigated by quantifying the critical charge of the leakage protected TSPC FF. The results are compared to both the static and the TSPC FF without leakage mitigation.

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Razavi, Behzad. "TSPC Logic [A Circuit for All Seasons]." IEEE Solid-State Circuits Magazine 8, no. 4 (2016): 10–13. http://dx.doi.org/10.1109/mssc.2016.2603228.

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Siddaiah, Premananda Belegehalli, Sahithi Narsepalli, Sanya Mittal, and Abdur Rehman. "Area and power efficient divide-by-32/33 dual-modulus pre-scaler using split-path TSPC with AVLS for frequency divider." Journal of Electrical Engineering 74, no. 5 (2023): 403–12. http://dx.doi.org/10.2478/jee-2023-0048.

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Abstract Pre-scalers are electronic circuits used in phase-locked loops to multiply frequencies. This is achieved by dividing the high-frequency signals generated from a voltage-controlled oscillator. The high-frequency operation of pre-scaler circuits leads to significantly higher power consumption. To address this, D flip-flops (D-FF) realized using true-single phase clocking (TSPC) logic. The work suggests incorporating the Adaptive Voltage Level Source (AVLS) circuit with the Dual Modulus Pre-Scaler (DMPS) circuit to reduce power consumption. In addition to the incorporation of the AVLS circuit, pass transistor logic (PTL) used in the feedback, further minimizes transistors and power. This paper proposes three different designs for divide-by-32/33 DMPS circuit. The proposed-1 design combines regular TSPC-based D-FF with PTL in the feedback and an AVLS circuit, resulting in an average power reduction of 36.5%. The proposed-2 design employs split-path TSPC-based D-FF with logic gates and an AVLS circuit, achieving a power reduction of 46.9%. The proposed-3 design employs split-path TSPC-based D-FF with PTL in the feedback and an AVLS circuit, achieving a significant power reduction of 47.8% compared to the existing DMPS circuit and transistor count by 9.1%. The proposed circuits are realized using a CMOS 180 nm technology node. Cadence Virtuoso and Spectre tools are used. The proposed divide-by-32/33 DMPS circuits also realized in the CMOS 45 nm technology node to verify the functionality in the lower technology node. A power reduction of 46.86% observed when compared to the reference circuit. The proposed designs are both power- and area-efficient, making them promising solutions for minimizing power consumption in pre-scaler circuits.

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Shen, Tianchen, Jiabing Liu, Chunyi Song, and Zhiwei Xu. "A High-Speed Low-Power Divide-by-3/4 Prescaler using E-TSPC Logic DFFs." Electronics 8, no. 5 (2019): 589. http://dx.doi.org/10.3390/electronics8050589.

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A high-speed, low-power divide-by-3/4 prescaler based on an extended true single-phase clock D-flip flop (E-TSPC DFF) is presented. We added two more transistors and a mode control signal to the conventional E-TSPC based divide-by-4 divider to achieve the function of the divide-by-3/4 dual modulus frequency divider. The designed divide-by-3/4 achieved higher speed and lower power operation with mode control compared with the conventional ones. The prescaler was comprised of sixteen transistors and integrates an inverter in the second DFF to provide output directly. The power consumption was minimized due to the reduced number of stages and transistors. In addition, the prescaler operating speed was also improved due to a reduced critical path. We compared the simulation results with conventional E-TSPC based divide-by-3/4 dividers in the same process, where the figure-of-merit (FoM) of the proposed divider was 17.4–75.5% better than conventional ones. We have also fabricated the prescaler in a 40 nm complementary metal oxide semiconductor (CMOS) process. The measured highest operating frequency was 9 GHz with 0.303 mW power consumption under 1.35 V power supply, which agrees with the simulation well. The measurement results demonstrate that the proposed divider achieves high-speed and low-power operation.

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Varun, Krishan Bal, and Tripathi Rohit. "Power optimization in TSPC D flip-flop based 4-bit counter." i-manager’s Journal on Electronics Engineering 12, no. 3 (2022): 1. http://dx.doi.org/10.26634/jele.12.3.18977.

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In the present communication, the basic D flip flop has been considered with TSPC (True Single Phase Clock) logic for designing a novel 4-bit counter on 45 and 32nm technology. Here, it was with average power of 309 μWatts and 166.8 μWatts, which is very high on the respective technologies. The challenge is to reduce the average power and off state leakage power. To consider the challenge, two different techniques have been considered for power saving as, sleeping transistors and technique, modified TSPC D flip-flop (modified version In comparative study of simulations, it is observed that employing modified version of TSPC D flip-flop shows the most optimum results in terms of propagation delays and average power. Average power has been obtained as 260.3 μWatts which is 15.76% less than base counter on 45nm technology, and 133.2 μWatts which is 20.14 % less on 32nm technology. Moreover, Transistor sizing has also been used for separate analysis in which case the average power consumption has been found most minimum in 6/4 aspect ratio as 196.6 μWatts and 70.31 μWatts in both technologies respectively, among 6/4, 5/3 and 4/2 ratios.

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PH, Pavan, and Lalitha S. "Design of Low-Cost Stochastic Number Generator Using TSPC Logic in 45nm Technology." International Journal of Science and Research (IJSR) 12, no. 9 (2023): 1388–94. http://dx.doi.org/10.21275/sr23916161201.

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Li, Xiaoran, Jian Gao, Zhiming Chen, and Xinghua Wang. "High-Speed Wide-Range True-Single-Phase-Clock CMOS Dual Modulus Prescaler." Electronics 9, no. 5 (2020): 725. http://dx.doi.org/10.3390/electronics9050725.

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This manuscript presents two novel low-power high-speed true-single-phase-clock (TSPC) prescalers with division ratios of 2/3 and 4/5, respectively, in a standard 90-nm CMOS technology. The logic gates incorporated between the D-flip-flops (DFFs) of a conventional 2/3 prescaler are modified to reduce the propagation delay and hence increase the maximum operating frequency. The measurement results show that the proposed divide-by-2/3 and divide-by-4/5 prescalers can operate up to 17 GHz and 15.3 GHz, respectively, which increase by 5.4 GHz and 4.3 GHz compared with conventional TSPC prescalers. The power of the proposed divide-by-2/3 prescaler is 0.67 mW and 0.92 mW, and 0.87 mW and 1.06 mW for the proposed divide-by-4/5 prescaler. The chip occupies an area of 20 × 35 μm2 and 20 × 50 μm2 for the proposed divide-by-2/3 and divide-by-4/5 prescalers.

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Dhatrish, Tewari, and Khosla Mamta. "A Low Power Solution to Clock Domain Crossing." International Journal of Trend in Scientific Research and Development 6, no. 4 (2022): 1022–25. https://doi.org/10.5281/zenodo.6644583.

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Because of the increased complexity of designs in recent years, we now have multiple components on a single chip that employ independent clocks, meaning that these clocks are not synchronized. As a result, problems with Clock Domain Crossing will occur, which, if not resolved, will proliferate and destroy the entire chip. Data crossing clock domains can cause a variety of problems, including as metastability and data loss, which can lead to the device failing completely. To overcome the clock domain crossing concerns, this work presents a dual flip flop synchronizer that employs TSPC logic and is based on the SOI technology. TSPC synchronizer when implemented in SOI technology gives outstanding results. It improves the rise time by 46.15 %, the fall time by 28.57 %, dissipates 24.23% less power, power delay product by a huge margin of 59.20 % when compared to its bulk CMOS counterpart. When implemented on a chip, it also takes up the least amount of space. All the circuits are designed in DSCH and simulated in Microwind software.

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Dharani, S., and MA Asuvanti. "D Flip Flop Using AVLG Technique with Static Body Biasing Using Cadence Virtuoso Tool." Journal of Electronic Design Engineering 5, no. 3 (2019): 16–21. https://doi.org/10.5281/zenodo.3567510.

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The world is growing at an ultra-fast speed and so is the technology. Today, small devices with maximum efficiency and minimum power are in demand and so came the flip flops. They are used in large number of applications ranging from data storage to microprocessors. In this paper, a new circuit for D flip flop is proposed which uses two techniques, namely, AVL and body biasing techniques on 5 transistor TSPC D flip flop. The D flip flop circuit based on 5 transistor TSPC AVL technique is already existing. The body biasing technique is applied on the already existing circuit in order to minimize the power consumption. The simulations of these circuits are done on Cadence Virtuoso tool using 180nm technology. The detailed description is given in this research paper.

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Bany Hamad, Ghaith, Syed Rafay Hasan, Otmane Ait Mohamed, and Yvon Savaria. "New Insights Into the Single Event Transient Propagation Through Static and TSPC Logic." IEEE Transactions on Nuclear Science 61, no. 4 (2014): 1618–27. http://dx.doi.org/10.1109/tns.2014.2305434.

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Tang, Fang, and Amine Bermak. "Lower-power TSPC-based Domino Logic Circuit Design with 2/3 Clock Load." Energy Procedia 14 (2012): 1168–74. http://dx.doi.org/10.1016/j.egypro.2011.12.1071.

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Varun, Krishan Bal, and Tripathi Rohit. "Leakage power optimization using sleeping approaches in TSPC D flip-flop." i-manager's Journal on Circuits and Systems 10, no. 2 (2022): 10. http://dx.doi.org/10.26634/jcir.10.2.18978.

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In this paper, the basic D flip-flop has been considered with TSPC (True Single-Phase Clock) logic. Here, the leakage power of 1031 pW fell to the power for the operation of the memory elements, which is a lot compared to other triggers. The challenge is to reduce the optimal power off to conserve idle power. To solve this problem, three different powersaving techniques were considered, such as Technique 1: sleeping transistors, Technique 2: sleepy stack, and Technique 3: sleepy keeper. In a comparative study, it was observed that Technique 1 is the most optimal method for delays (falling and rising) and off-state leakage power compared to the other methods considered. The off-state leakage power was 1.753 pW, which is 93.07% and 76.90% less than by Techniques 2 and 3, respectively.

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Shaik Peerla, Rizwan, Ashudeb Dutta, and Bibhu Datta Sahoo. "An Extended Range Divider Technique for Multi-Band PLL." Journal of Low Power Electronics and Applications 13, no. 3 (2023): 43. http://dx.doi.org/10.3390/jlpea13030043.

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This paper presents a multiplexer-based extended range multi-modulus divider (ER-MMD) technique for multi-band phase locked loop (PLL). The architecture maintains a modular structure by using conventional 2/3 divider cells and a multiplexer without adding any extra logic circuitry. The area and power overhead is minimal. The 2/3 divider cells are designed using true single phase clock (TSPC) logic for ER-MMD to operate in the sub-10 GHz range. A division range of 2 to 511 is achieved using this logic. The ER-MMD operates at a maximum frequency of 6 GHz with a worst-case current of 625 μA when powered with a 1 V supply. A dual voltage controlled oscillator (VCO), L5/S band PLL for Indian Regional Navigation Satellite System (IRNSS) application is designed, which incorporates an ER-MMD based on the proposed approach as a proof of concept. This technique achieves the best power efficiency of 12 GHz/mW, among the state-of-the-art ER-MMD designs.

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Ravi, T., and V. Kannan. "Design and Analysis of Low Power CNTFET TSPC D - Flip Flop Based Shift Registers." Applied Mechanics and Materials 229-231 (November 2012): 1651–55. http://dx.doi.org/10.4028/www.scientific.net/amm.229-231.1651.

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This paper enumerates the efficient design and analysis of low power CNTFET True single phase clock logic D Flip flop based shift registers. The TSPC D flip flop and shift registers are designed using Stanford University CNTFET model and proposed 10nm CNTFET model with sleepy keeper low power technique. The CNTFET is emerging as a viable replacement to the MOSFET. The transient and power analyses are obtained with operating voltage of 1V and the operating frequency at 1GHz. The simulation results are obtained and the analysis are compared with circuits designed using 32nm MOSFET. The comparison results are indicated that the proposed 10nm CNTFET based design and the low power technique are more efficient in power saving as compared to MOSFET design.

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Shao, Yujuan, Huiming Liu, and Wenshen Wang. "A High-Speed Low Power Multi-Modulus Frequency Divider based on TSPC logic using 55nm CMOS." IOP Conference Series: Materials Science and Engineering 452 (December 13, 2018): 042120. http://dx.doi.org/10.1088/1757-899x/452/4/042120.

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Huang, Yajie, Chao Luo, and Guoping Guo. "A Cryogenic 8-Bit 32 MS/s SAR ADC Operating down to 4.2 K." Electronics 12, no. 6 (2023): 1420. http://dx.doi.org/10.3390/electronics12061420.

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This paper presents a cryogenic 8-bit 32 MS/s successive approximation register (SAR) analog-to-digital converter (ADC) which operates down to 4.2 K. This work uses a modified liquid helium temperature (LHT) SMIC 0.18 μm CMOS technology to support the post-layout simulation. The proposed architecture adopts an offset-promoted dynamic comparator, waveform shaping circuit and true single-phase clock (TSPC) based sar logic circuit to achieve high realizing frequency and low power dissipation. At 1.8-V supply, 1.7 V input amplitude and 32 MS/s sampling frequency, the ADC achieves a power consumption of 2.4 mW and a signal-to-noise and distortion ratio (SNDR) of 47.7 dB, obtaining a figure of merit (FOM) of 378 fJ/conversion-step. The layout area of the ADC is about 0.253 mm2.

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Shankar, Bhukya, and Ravikanth Sivangi. "A Low Power, Leakage Reduction, High Speed 8-Bit Ripple Carry TSPC Adder using MTCMOS Dynamic Logic." CVR Journal of Science & Technology 10, no. 1 (2016): 35–38. http://dx.doi.org/10.32377/cvrjst1008.

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Badiali, Alessandro, and Mattia Borgarino. "Low-Power Silicon-Based Frequency Dividers: An Overview." Electronics 14, no. 4 (2025): 652. https://doi.org/10.3390/electronics14040652.

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Frequency divider circuits divide the frequency of an input signal by a specified ratio. They are critical components in analog, digital, and mixed-signal microelectronics. In power-constrained environments, such as cryogenic electronics or implanted biomedical devices, minimizing power consumption is crucial. This paper reviews operational principles, benefits, trade-offs, and circuit solutions of three main typologies of frequency divider: Current Mode Logic (CML), Injection-Locking (IL), and True Single-Phase Clock (TSPC). Distinct trade-offs between operation speed, power efficiency, complexity, and integration make each of them suitable for specific applications. Nevertheless, hybrid circuit solutions combining different typologies could potentially balance performance and energy efficiency. This paper thus also reports and discusses examples of hybrid frequency dividers. Examples of frequency dividers implemented in emerging technologies, such as the FinFETs CMOS, are addressed, as well. The purpose of this paper is to guide designers in selecting frequency divider solutions that best meet the design-specific requirements.

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Hao, Muzhen, Xiaodong Liu, Zhizhe Liu, et al. "A Broadband High-speed Programmable Multi-modulus Divider Based on CMOS Process." Journal of Physics: Conference Series 2132, no. 1 (2021): 012046. http://dx.doi.org/10.1088/1742-6596/2132/1/012046.

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Abstract This paper introduces a design of a high-speed programmable multi-modulus divider (MMD) based on 65nm CMOS process. The design adopts the cascade structure of 7 level 2/3 frequency dividers, and expands the frequency division range by adjusting the number of cascade stages, so as to achieve a continuous frequency division ratio of 16 to 255. Among them, the first level 2/3 frequency divider adopts the D flip-flop design of CML (current mode logic) structure, the second level 2/3 frequency divider adopts the D flip-flop design of E-TSPC (extended true-single-phase-clock) structure. The whole circuit realizes the working frequency range of 13∼18GHz high frequency and large bandwidth. This design has completed layout drawing and parasitic parameter extraction simulation. The simulation results show that the operating frequency range of the circuit can reach 13∼18GHz. When the input signal is 18GHz and the frequency division ratio is 255, the phase noise is about -135dBc/Hz@1kHz. It has the advantages of high frequency, large bandwidth, and low phase noise.

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Zhao, Minxiong, and Jiwei Huang. "Design of a multi-modulus divider with a wide frequency dividing range and low power consumption." Journal of Physics: Conference Series 2524, no. 1 (2023): 012008. http://dx.doi.org/10.1088/1742-6596/2524/1/012008.

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Abstract A method of moduli expansion was presented to address the issue of wrongly altering the divider ratio at the boundary of the modulus expansion when multi-mode dividers (MMD) were utilized in fractional-N phase locked loops (PLLs). The multi-mode frequency divider was designed as the cascade of the 2/3 frequency dividers with an RS control terminal. Compared to traditional methods, only one OR gate is required for each modulus expansion, reducing the chip area. The 2/3 divider was designed using a True Single-Phase Clocked (TSPC) D-trigger structure, and each D-trigger uses a logic control technique with clearing and setting the number. An eight-stage multi-mode frequency divider with modulus expansion was developed using SMIC 55 nm CMOS technology. The simulation results demonstrated the large frequency divider range of the multi-mode frequency divider and its ability to carry out consistent switching operations over the 8–511 frequency divider range. The power consumption is 66.04W at a supply voltage of 1V, an input frequency of 2GHz, and an output frequency of 250MHz.

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Saha, Aloke, Sushil Kumar, Debajit Das та Mrinmoy Chakraborty. "LP-HS Logic Evaluation on TSMC 0.18μm CMOS Technology". International Journal of High Speed Electronics and Systems 26, № 04 (2017): 1740024. http://dx.doi.org/10.1142/s0129156417400249.

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Present paper analyses different aspects of “Low Power-High Speed” (LP-HS) logic in favour of present day ULSI system focus. At first, the speed-power efficiency of LP-HS logic is investigated by designing some basic digital building blocks like Buffer, OR, AND, XOR etc. Next, the Voltage Transfer Characteristics (VTC), Noise Margin (NM) and the temperature effect on logic threshold with respect to LP-HS Buffer circuit are examined. The robustness and reliability of LP-HS Logic has been measured in terms of corner analysis with TT (Typical), FF (Fastest) and SS (Slowest) PVT (Process Voltage Temperature) variations on LP-HS XOR circuit. The worst case delay and PDP variation is recorded. Finally the 8:1 Multiplexer is designed, optimized and evaluated based on LP-HS Logic. The evaluated results are compared with some recent competitive designs to benchmark. To resolve reliability issue the corner analysis with PVT variation has been performed on designed 8:1 Multiplexor circuit. All the simulations are done on TSMC 0.18μm CMOS technology using Tanner EDA V.13 at 25°C temperature with 1.8V supply rail.

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Gupta, Kirti, Neeta Pandey, and Maneesha Gupta. "MOS Current Mode Logic with Capacitive Coupling." ISRN Electronics 2012 (November 5, 2012): 1–7. http://dx.doi.org/10.5402/2012/473257.

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A new MOS current mode logic (MCML) style exhibiting capacitive coupling to enhance the switching speed of the digital circuits is proposed. The mechanism of capacitive coupling and its effect on the delay are analytically modeled. SPICE simulations to validate the accuracy of the analytical model have been carried out with TSMC 0.18 μm CMOS technology parameters. Several logic gates such as five-stage ring oscillator, NAND, XOR2, XOR3, multiplexer, and demultiplexer based on the proposed logic style are implemented and their performance is compared with the conventional logic gates. It is found that the logic gates based on the proposed MCML style lower the delay by 23 percent. An asynchronous FIFO based on the proposed MCML style has also been implemented as an application.

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CHANG, ROBERT C., PO-CHUNG HUNG, and HSIN-LEI LIN. "LOW POWER ENERGY RECOVERY COMPLEMENTARY PASS-TRANSISTOR LOGIC." Journal of Circuits, Systems and Computers 15, no. 04 (2006): 491–504. http://dx.doi.org/10.1142/s0218126606003271.

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A proposed adiabatic logic called Energy Recovery Complementary Pass-transistor Logic (ERCPL) is presented in this paper. It operates with a two-phase nonoverlapping power-clock supply. It uses bootstrapping to achieve efficient power saving and eliminates any nonadiabatic losses on the charge-steering devices. A scheme is used to recover part of the energy trapped in the bootstrapping nodes. We compare the energy dissipation between ERCPL and other logic circuits by simulation. Simulation results show that a pipelined ERCPL carry look-ahead adder can achieve a power reduction of 80% over the conventional CMOS case. Operation of an 8-bit ERCPL CLA fabricated using the TSMC 0.35 μm 1P4M CMOS technology has been experimentally verified.

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Chanda, Manash, Swapnadip De, and Chandan Kumar Sarkar. "Design and Analysis of 32-Bit CLA Using Energy Efficient Adiabatic Logic for Ultra-Low-Power Application." Journal of Circuits, Systems and Computers 24, no. 10 (2015): 1550160. http://dx.doi.org/10.1142/s0218126615501601.

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This paper shows that a conventional semi-custom design-flow based on a energy efficient adiabatic logic (EEAL) cell library allows any VLSI designer to design and verify complex adiabatic arithmetic units in a simple way, thus, enjoying the energy reduction benefits of adiabatic logic. A family of semi-custom EEAL-based 32-bit carry-lookahead adder (CLA) has been designed in a TSMC 90-nm CMOS process technology and verified by CADENCE Design suite. Differential cascode voltage swing (DCVS) logic has been used to implement the newly proposed EEAL and it uses only a sinusoidal clock supply to ensure correct operation. Post-layout simulations show that semi-custom adiabatic arithmetic units can save significant amount of energy, as compared to the previously reported single clocked adiabatic logic and logically equivalent static CMOS implementation. Extensive CADENCE simulations have been done for the verification of the functionality of the proposed logic structure.

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Gupta, Kirti, Neeta Pandey, and Maneesha Gupta. "Multithreshold MOS Current Mode Logic Based Asynchronous Pipeline Circuits." ISRN Electronics 2012 (December 5, 2012): 1–7. http://dx.doi.org/10.5402/2012/529194.

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Multithreshold MOS Current Mode Logic (MCML) implementation of asynchronous pipeline circuits, namely, a C-element and a double-edge triggered flip-flop is proposed. These circuits use multiple-threshold MOS transistors for reducing power consumption. The proposed circuits are implemented and simulated in PSPICE using TSMC 0.18 μm CMOS technology parameters. The performance of the proposed circuits is compared with the conventional MCML circuits. The results indicate that the proposed circuits reduce the power consumption by 21 percent in comparison to the conventional ones. To demonstrate the functionality of the proposed circuits, an asynchronous FIFO has also been implemented.

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Pandey, Neeta, Damini Garg, Kirti Gupta, and Bharat Choudhary. "Hybrid Dynamic MCML Style: A High Speed Dynamic MCML Style." Journal of Engineering 2016 (2016): 1–10. http://dx.doi.org/10.1155/2016/8027150.

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This paper proposes hybrid dynamic current mode logic (H-DyCML) as an alternative to existing dynamic CML (DyCML) style for digital circuit design in mixed-signal applications. H-DyCML introduces complementary pass transistors for implementation of logic functions. This allows reduction in the stacked source-coupled transistor pair levels in comparison to the existing DyCML style. The resulting reduction in transistor pair levels permits significant speed improvement. SPICE simulations using TSMC 180 nm and 90 nm CMOS technology parameters are carried out to verify the functionality and to identify their advantages. Some issues related to the compatibility of the complementary pass transistor logic have been investigated and the appropriate solutions have been proposed. The performance of the proposed H-DyCML gates is compared with the existing DyCML gates. The comparison confirms that proposed H-DyCML gates is faster than the existing DyCML gates.

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Lima, Vitor Gonçalves, Guilherme Paim, Rodrigo Wuerdig, et al. "Enhancing Side Channel Attack-Resistance of the STTL Combining Multi-Vt Transistors with Capacitance and Current Paths Counterbalancing." Journal of Integrated Circuits and Systems 15, no. 1 (2020): 1–11. http://dx.doi.org/10.29292/jics.v15i1.100.

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Differential power analysis (DPA) exploits the difference between the instantaneous power of the circuit arches transitions to stole the state as information aiming to unveil the cryptographic key. Secure triple track logic (STTL) is a circuit-level countermeasure to DPA attacks based on dual-rail precharge logic (DPL). STTL is robust to attacks due to the delay in an insensitive feature that mitigates the logic glitches generated by the different path delays that lead to the logic gate inputs until they stabilize. The main STTL drawback, however, is the asymmetry of the transistor topology. Asymmetry causes unbalanced internal capacitances and different internal paths for the current flow, and DPA exploits it as a source of information leakage. Our work proposes three circuit topologies, combining multi-Vt transistors with a circuit counterbalancing strategy, aiming to improve the STTL DPA attack-resistance. Data encryption standard substitution-box circuit, designed in a TSMC 40 nm CMOS process, is our application case study to evaluate the DPA attack-resistance. Results gathered at the application-level show that our proposals outperform DPA attack-resistance of the prior work.

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Tang, Kwok L., and Robert J. Mulholland. "Comparing fuzzy logic with classical controller designs." IEEE Transactions on Systems, Man, and Cybernetics 17, no. 6 (1987): 1085–87. http://dx.doi.org/10.1109/tsmc.1987.6499321.

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Ferilli, Stefano. "WoMan: Logic-Based Workflow Learning and Management." IEEE Transactions on Systems, Man, and Cybernetics: Systems 44, no. 6 (2014): 744–56. http://dx.doi.org/10.1109/tsmc.2013.2273310.

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Mann, Aarushi, Naman Malhotra, and Neeta Pandey. "Adaption of Power Gating in Positive Feedback Adiabatic Logic Circuits." International Journal of Advance Research and Innovation 7, no. 3 (2019): 1–6. http://dx.doi.org/10.51976/ijari.731901.

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Positive Feedback Adiabatic Logic (PFAL), a quasi static and differential logic adiabatic family, is one of the most robust, with significant reduction in power consumption has been chosen in this work. Power Gating has been adapted in order to further reduce power dissipation. It is accomplished by sleep state control units that switch circuits between awake and idle. Two power gating methodologies, footer and header, have been evaluated and compared. The functional verification and power evaluations have been performed using TSPICE simulations with 180nm TSMC CMOS parameters. Power consumption has also been examined by varying supply voltage, frequency of the power clock signal and load capacitance. The observed overhead in awake state power dissipations is compensated for with the significant decrease in idle state power dissipation.

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Lakshmi Prasanna, J., V. Sahiti, E. Raghuveera, and M. Ravi Kumar. "CMOS based Power Efficient Digital Comparator with Parallel Prefix Tree Structure." International Journal of Engineering & Technology 7, no. 2.7 (2018): 647. http://dx.doi.org/10.14419/ijet.v7i2.7.10915.

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A 128-Bit Digital Comparator is designed with Digital Complementary Metal Oxide Semiconductor (CMOS) logic, with the use of Parallel Prefix Tree Structure [1] technique. The comparison is performed on Most Significant Bit (MSB) to the Least Significant Bit (LSB). The comparison for the lower order bits carried out only when the MSBs are equal. This technique results in Optimized Power consumption and improved speed of operation. To make the circuit regular, the design is made using only CMOS logic gates. Transmission gates were used in the existing design and are replaced with the simple AND gates. This 128-Bit comparator is designed using Cadence TSMC 0.18µm technology and optimized the Power dissipation to 0.28mW and with a Delay of 0.87μs.

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Zhao, Lei, Yan Lu, and Rui P. Martins. "A Digital LDO With Co-SA Logics and TSPC Dynamic Latches for Fast Transient Response." IEEE Solid-State Circuits Letters 1, no. 6 (2018): 154–57. http://dx.doi.org/10.1109/lssc.2018.2885217.

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Lin, Jin-Fa, Zheng-Jie Hong, Chang-Ming Tsai, Bo-Cheng Wu, and Shao-Wei Yu. "Novel Low-Complexity and Low-Power Flip-Flop Design." Electronics 9, no. 5 (2020): 783. http://dx.doi.org/10.3390/electronics9050783.

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In this paper, a compact and low-power true single-phase flip-flop (FF) design with fully static operations is presented. The design is developed by using various circuit-reduction schemes and features a hybrid logic style employing both pass transistor logic (PTL) and static complementary metal-oxide semiconductor (CMOS) logic to reduce circuit complexity. These circuit optimization measures pay off in various aspects, including smaller clock-to-Q (CQ) delay, lower average power, lower leakage power, and smaller layout area; and the transistor-count is only 17. Fabricated in TSMC 180 nm CMOS technology, it reduces by over 29% the chip area compared to the conventional transmission gate FF (TGFF). To further show digital circuit/system level advantages, a multi-mode shift register has been realized. Experimental measurement results at 1.8 V/4 MHz show that, compared with the TGFF design, the proposed design saves 64.7% of power consumption while reducing chip area by 26.2%.

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Wang, Bin, and Qing Sheng Hu. "A High-Speed 64b/66b Decoder Used in SerDes." Applied Mechanics and Materials 556-562 (May 2014): 1549–52. http://dx.doi.org/10.4028/www.scientific.net/amm.556-562.1549.

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A high-speed 64b/66b decoder for SerDes system was designed in TSMC 0.18-μm CMOS Technology. The chip is composed of Block Sync, Descrambler, Decode Process and Receive Control. To make the system can be work in high speed, we use a lot of technology such as pipeline strategy, optimization of complicated logics and parallel descrambler.

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Zhao, Xianghong, Longhua Ma, Hongye Su, Jieyu Zhao, and Weiming Cai. "High-Performance Current-Mode Logic Ternary D Flip-Flop Based on Bipolar Complementary Metal Oxide Semiconductor." Journal of Nanoelectronics and Optoelectronics 16, no. 4 (2021): 528–33. http://dx.doi.org/10.1166/jno.2021.2976.

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In this paper, a simple-structured and high-performance current-mode logic (CML) ternary D flip-flop based on BiCMOS is proposed. It combines both advantages of BiCMOS and CML circuits, which is with much more high-speed, strong-drive and anti-interference abilities. Utilizing TSMC 180 nm process, results of simulations carried out by HSPICE illustrate the proposed circuit not only has correct logic function, but also gains improvements of 95.6~98.4% in average D-Q delay and 16.2%~70.4 in PDP compared with advanced ternary D flip-flop. When compared at the same information transmission speed, proposed circuit is more competitive. Furthermore, it can perform up to high frequency of 15 GHz and drive heavier load. All the results prove that proposed circuit is high-performance and very suitable for high-speed and high-frequency applications.

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Pandey, Neeta, Kirti Gupta, and Bharat Choudhary. "New Proposal for MCML Based Three-Input Logic Implementation." VLSI Design 2016 (September 19, 2016): 1–10. http://dx.doi.org/10.1155/2016/8712768.

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This paper presents a new proposal for three-input logic function implementation in MOS current mode logic (MCML) style. The conventional realization of such logic employs three levels of stacked source-coupled transistor pairs. It puts restriction on minimum power supply requirement and results in increased static power. The new proposal presents a circuit element named as quad-tail cell which reduces number of stacked source-coupled transistor levels by two. A three-input exclusive-OR (XOR) gate, a vital element in digital system design, is chosen to elaborate the approach. Its behavior is analyzed and SPICE simulations using TSMC 180 nm CMOS technology parameters are included to support the theoretical concept. The performance of the proposed circuit is compared with its counterparts based on CMOS complementary pass transistor logic, conventional MCML, and cascading of existing two input tripple-tail XOR cells and applying triple-tail concept in conventional MCML topology. It is found that the proposed XOR gate performs best in terms of most of the performance parameters. The sensitivity of the proposed XOR gate towards process variation shows a variation of 1.54 between the best and worst case. As an extension, a realization of 4 : 1 multiplexer has also been included.

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Yazdanbakhsh, Omolbanin, and Scott Dick. "Forecasting of Multivariate Time Series via Complex Fuzzy Logic." IEEE Transactions on Systems, Man, and Cybernetics: Systems 47, no. 8 (2017): 2160–71. http://dx.doi.org/10.1109/tsmc.2016.2630668.

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Abedi, Zahra, Sameer Hemmady, Thomas Antonsen, Edl Schamiloglu, and Payman Zarkesh-Ha. "Application of High-Frequency Leakage Current Model for Characterizing Failure Modes in Digital Logic Gates." Energies 14, no. 10 (2021): 2906. http://dx.doi.org/10.3390/en14102906.

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In this paper, a predictive model is developed to characterize the impact of high-frequency electromagnetic interference (EMI) on the leakage current of CMOS integrated circuits. It is shown that the frequency dependence can be easily described by a transfer function that depends only on a few dominant parasitic elements. The developed analytical model is successfully compared against measurement data from devices fabricated using 180 nm, 130 nm, and 65 nm standard CMOS processes through TSMC. Based on the predictive model, the impact of EMI on leakage current in a CMOS inverter is reduced by increasing the frequency from 10 MHz to 4 GHz.

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Smith, Ronald E. "The Logic and Design of Case Study Research." Sport Psychologist 2, no. 1 (1988): 1–12. http://dx.doi.org/10.1123/tsp.2.1.1.

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Advances in applied sport psychology will require the application of experimental, quasi-experimental, and nonexperimental research methodologies. The case study has stimulated important discoveries in many areas of psychology, although its limitations for drawing causal inferences are widely acknowledged. Case studies vary markedly in their design and methodology, however, and these differences dictate the extent to which alternative explanations can be ruled out on procedural or empirical grounds. The present article discusses design considerations that influence the construct validity, internal and external validity, and reliability of case reports. The application of techniques such as pattern matching, time-series analysis, and goal-attainment scaling to case study methodology is also described. Finally, guidelines for planning and reporting case studies in a manner that enhances their scientific and practical contributions are discussed.

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Dhananjayan, Amrith, and Kiam Tian Seow. "A Metric Temporal Logic Specification Interface for Real-Time Discrete-Event Control." IEEE Transactions on Systems, Man, and Cybernetics: Systems 44, no. 9 (2014): 1204–15. http://dx.doi.org/10.1109/tsmc.2014.2303051.

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Khindria, Ishita, Kashika Hingorani, and Vandana Niranjan. "Low Power ALU using Wave Shaping Diode Adiabatic Logic." Indian Journal of VLSI Design 2, no. 2 (2022): 1–4. http://dx.doi.org/10.54105/ijvlsid.d1209.091422.

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The evolution of portable electronic devices and their widespread application has led to an increased focus on power dissipation as one of the critical parameters. An increase in functionality requirement and design complexity on a single chip has resulted in increased power dissipation. High power dissipation has motivated study and innovation on low power circuit design techniques. Adiabatic logic has been studied as one of the design techniques to reduce power dissipation by reusing the power that was getting dissipated in conventional designs. This paper presents the application of Wave Shaping Diode Adiabatic Logic (WSDAL) to implement an ALU and analyse the improvement in power dissipation as compared to the conventional CMOS design. The WSDAL design uses a slow and time-fluctuating 2-phase sinusoidal Power Clock (PC), which supplies power as well as a clock to the designs. WSDAL uses an Ultra-Low Power Diode (ULPD) structure that operates as a wave shaping device and reduces glitches at the output. The design has been implemented in OrCAD Capture and simulated using Pspice in TSMC 180nm technology. The simulations were performed at 200MHz PC frequency and power dissipation was studied over a range of voltages from 1.4V to 2.2V. The simulations show that WSDAL ALU dissipates less power than the CMOS design. This study indicates that WSDAL-based designs have the potential to be deployed for power dissipation reduction in portable devices.

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Ishita, Khindria, Hingorani Kashika, and Niranjan Vandana. "Low Power ALU using Wave Shaping Diode Adiabatic Logic." Indian Journal of VLSI Design (IJVLSID) 2, no. 2 (2022): 1–4. https://doi.org/10.54105/ijvlsid.D1209.091422.

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<strong>Abstract: </strong>The evolution of portable electronic devices and their widespread application has led to an increased focus on power dissipation as one of the critical parameters. An increase in functionality requirement and design complexity on a single chip has resulted in increased power dissipation. High power dissipation has motivated study and innovation on low power circuit design techniques. Adiabatic logic has been studied as one of the design techniques to reduce power dissipation by reusing the power that was getting dissipated in conventional designs. This paper presents the application of Wave Shaping Diode Adiabatic Logic (WSDAL) to implement an ALU and analyse the improvement in power dissipation as compared to the conventional CMOS design. The WSDAL design uses a slow and time-fluctuating 2-phase sinusoidal Power Clock (PC), which supplies power as well as a clock to the designs. WSDAL uses an Ultra-Low Power Diode (ULPD) structure that operates as a wave shaping device and reduces glitches at the output. The design has been implemented in OrCAD Capture and simulated using Pspice in TSMC 180nm technology. The simulations were performed at 200MHz PC frequency and power dissipation was studied over a range of voltages from 1.4V to 2.2V. The simulations show that WSDAL ALU dissipates less power than the CMOS design. This study indicates that WSDAL-based designs have the potential to be deployed for power dissipation reduction in portable devices.

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Kumar, Rajat, Divyanshu Divyanshu, Danial Khan, Selma Amara, and Yehia Massoud. "Polymorphic Hybrid CMOS-MTJ Logic Gates for Hardware Security Applications." Electronics 12, no. 4 (2023): 902. http://dx.doi.org/10.3390/electronics12040902.

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Various hardware security concerns, such as hardware Trojans and IP piracy, have sparked studies in the security field employing alternatives to CMOS chips. Spintronic devices are among the most-promising alternatives to CMOS devices for applications that need low power consumption, non-volatility, and ease of integration with silicon substrates. This article looked at how hardware can be made more secure by utilizing the special features of spintronics devices. Spintronic-based devices can be used to build polymorphic gates (PGs), which conceal the functionality of the circuits during fabrication. Since spintronic devices such as magnetic tunnel junctions (MTJs) offer non-volatile properties, the state of these devices can be written only once after fabrication for correct functionality. Symmetric circuits using two-terminal MTJs and three-terminal MTJs were designed, analyzed, and compared in this article. The simulation results demonstrated how a single control signal can alter the functionality of the circuit, and the adversary would find it challenging to reverse-engineer the design due to the similarity of the logic blocks’ internal structures. The use of spintronic PGs in IC watermarking and fingerprinting was also explored in this article. The TSMC 65nm MOS technology was used in the Cadence Spectre simulator for all simulations in this work. For the comparison between the structures based on different MTJs, the physical dimension of the MTJs were kept precisely the same.

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Thanh, Toi Le, Lac Truong Tri, and Hoang Trang. "Power Consumption Improvements in AES Decryption Based on Null Convention Logic." International Journal of Circuits, Systems and Signal Processing 15 (April 7, 2021): 254–64. http://dx.doi.org/10.46300/9106.2021.15.29.

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In this paper, we propose a new asynchronous method based on a Null Convention Logic (NCL) to improve power consumption for low power integrated circuits. The reason is because the NCL based designs do not use a clock, it eliminates the problems related to the clock and its power consumption reduces significantly. To show the advantages of the selected method, we propose two design models using the synchronous circuit design method, and the NCL based asynchronous circuit design method. To test these two design models conveniently, we also propose an extra automatic test model. In this study, the AES decryption is used as an example to illustrate both methods. The two above proposed AES decryption models are simulated and synthesized at the various corners by VCS and Design Compiler tool using TSMC standard cell libraries in 65nm technology. The synthesis results of the two above mentioned models indicated that the power consumption of the NCL based asynchronous circuit model is 3 times lower than that of the synchronous circuit model, and significantly improves (from 94% to 98%) compared with the results of the other authors. The processing speed of the NCL based asynchronous circuit paradigm is able to achieve a maximum speed.

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Li, Shengman, Carlo Gilardi, Gilad Zeevi, Subhasish Mitra, and H. S. Philip Wong. "(Keynote) High-Performance Carbon Nanotube Transistors for Logic Platform." ECS Meeting Abstracts MA2024-01, no. 15 (2024): 1174. http://dx.doi.org/10.1149/ma2024-01151174mtgabs.

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Low-dimensional 1D and 2D materials hold promise as candidate channel materials for highly scaled and high-performance transistors beyond the limits of silicon-based transistors. This talk will first motivate transistors built on low-dimensional channels due to the significant speed, energy efficiency, and transistor density benefits enabled by their electronic and physical properties. This talk will focus on 1D carbon nanotube (CNT) semiconductors and describe the advanced device component process modules that have been demonstrated, explaining both the fundamental mechanisms of operation and device-level performance objectives. Single-CNT FET experimental studies give insight into the quality of (1) low resistance N- and P- contacts down to 10 nm contact length, (2) high-capacitance gate dielectrics optimized for deposition on SP2 carbon surfaces, and (3) controlled N- and P- remote dielectric doping. To achieve high current density each transistor must contain multiple CNTs, therefore we will review state-of-the-art strategies to assemble densely aligned arrays of CNT with controlled CNT spacing between 2-10 nm and uniform electronic bandgap. The final portion of the talk will highlight recent advances from our team and others to integrate the best device components together to demonstrate high-performance carbon nanotube MOSFETs. We will elaborate on the remaining challenges and provide a summary of device design tradeoffs that will help guide future studies. We are grateful for support and collaboration from TSMC Corporate Research, DoD, Stanford SystemX Alliance, Stanford Nanofabrication Facility, Stanford Nano Shared Facility, and the University of California at San Diego.

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Ray, Kumar S., and D. Dutta Majumder. "Fuzzy logic control of a nonlinear multivariable steam generating unit using decoupling theory." IEEE Transactions on Systems, Man, and Cybernetics SMC-15, no. 4 (1985): 539–58. http://dx.doi.org/10.1109/tsmc.1985.6313422.

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Aicha, Menssouri, El Khadiri Karim, and Tahiri Ahmed. "The 1.5 bit-per-stage 10-bit pipelined CMOS A/D converter for CMOS image sensor." 1.5 bit-per-stage 10-bit pipelined CMOS A/D converter for CMOS image sensor 14, no. 4 (2023): 2273–82. https://doi.org/10.11591/ijpeds.v14.i4.pp2273-2282.

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This paper presents a 1.5-bit/stage pipeline analog-to-digital converters (ADC) with a 100 MHz operating frequency for CMOS image sensors built using TSMC 90nm CMOS technology. The design features a novel architecture including a comparator, CMOS transmission gates, a sub-ADC logic circuit, bootstrap switches, and a gain-boosted fully differential telescopic op-amp based switched-capacitor MDAC. The ADC operates on a 1.8 V power supply, with a typical power dissipation of 1.632 mW, and a full-scale input signal voltage of 0.8 V. At 100 MHz sampling frequency, it achieves a maximum ENOB of 12.42 bits, an SNR of 76.53 dB, and a FOM of 0.297 pJ/conversion step. This 1.5-bit/stage pipeline ADC is well-suited for CMOS image sensors.

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Zadeh, Lofti A. "Syllogistic reasoning in fuzzy logic and its application to usuality and reasoning with dispositions." IEEE Transactions on Systems, Man, and Cybernetics SMC-15, no. 6 (1985): 754–63. http://dx.doi.org/10.1109/tsmc.1985.6313459.

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