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Journal articles on the topic 'Verilog code'

Author: Grafiati

Published: 5 June 2025

Last updated: 16 July 2025

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Koti, Mr Manjunath, and Dr Basavaraj I. Neelgar. "CAN Tx Frame Implementation using Verilog." Journal of University of Shanghai for Science and Technology 23, no. 07 (2021): 1303–13. http://dx.doi.org/10.51201/jusst/21/07311.

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This article discusses the concept of CAN protocol and its implementation in verilog language. Initially the CAN protocol description is given in brief with the block diagram, later its design, implementation in verilog code is presented. The CAN transmission (Tx) data Frame is realized using verilog code, this is achieved by defining individual sub-blocks verilog codes and combining these to get the CAN transmission of data frame. In the year 1986, CAN data link layer protocol was introduced in SAE conference. In 1993, CAN protocol and high speed physical layer were internationally accredited as ISO 11898. As on today it has 11898-1 to 4 standard documents. The CAN 1.0, 2.0 versions were initially had fixed data rate for the entire frame. In 2012, CAN-FD (Flexible data rate) protocol was introduced. This will allow data phase a second higher bit rate, along with this restriction of 8 bytes is extended up to 64 bytes.In this paper CAN Tx data frame is realized using Xilinx 14.7 version using verilog language.

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Ho, Chia-Tung, Haoxing Ren, and Brucek Khailany. "VerilogCoder: Autonomous Verilog Coding Agents with Graph-based Planning and Abstract Syntax Tree (AST)-based Waveform Tracing Tool." Proceedings of the AAAI Conference on Artificial Intelligence 39, no. 1 (2025): 300–307. https://doi.org/10.1609/aaai.v39i1.32007.

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Due to the growing complexity of modern Integrated Circuits (ICs), automating hardware design can prevent a significant amount of human error from the engineering process and result in less errors. Verilog is a popular hardware description language for designing and modeling digital systems; thus, Verilog generation is one of the emerging areas of research to facilitate the design process. In this work, we propose VerilogCoder, a system of multiple Artificial Intelligence (AI) agents for Verilog code generation, to autonomously write Verilog code and fix syntax and functional errors using collaborative Verilog tools (i.e., syntax checker, simulator, and waveform tracer). Firstly, we propose a task planner that utilizes a novel Task and Circuit Relation Graph retrieval method to construct a holistic plan based on module descriptions. To debug and fix functional errors, we develop a novel and efficient abstract syntax tree (AST)-based waveform tracing tool, which is integrated within the autonomous Verilog completion flow. The proposed methodology successfully generates 94.2% syntactically and functionally correct Verilog code, surpassing the state-of-the-art methods by 33.9% on the VerilogEval-Human v2 benchmark.

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Xu, Ying. "Asynchronous FIFO Design Based on Verilog." Highlights in Science, Engineering and Technology 38 (March 16, 2023): 965–70. http://dx.doi.org/10.54097/hset.v38i.5983.

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With the rapid development of integrated circuits, asynchronous First Input First Output (FIFO) is often used to solve the problem of data transmission across the clock domain. This paper mainly studies the key problem of asynchronous FIFO design - the generation of empty - full signal. To solve this problem, it is necessary to realize the synchronization of signal across the clock domain and convert binary code into gray code to reduce the probability of metastable state. The null and full signals generated by the asynchronous FIFO designed in this paper are false null and false full, but this does not affect the function of the asynchronous FIFO, and will only lose part of the performance. Through Modelsim simulation verification, the designed asynchronous FIFO can realize first-in, first-out of data and correctly generate empty and full signal, which meets the design requirements. The research of this paper is helpful for further application of asynchronous FIFO in data transmission across clock domains.

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Chen, Qinlin, Nairen Zhang, Jinpeng Wang, et al. "The Essence of Verilog: A Tractable and Tested Operational Semantics for Verilog." Proceedings of the ACM on Programming Languages 7, OOPSLA2 (2023): 234–63. http://dx.doi.org/10.1145/3622805.

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With the increasing need to apply modern software techniques to hardware design, Verilog, the most popular Hardware Description Language (HDL), plays an infrastructure role. However, Verilog has several semantic pitfalls that often confuse software and hardware developers. Although prior research on formal semantics for Verilog exists, it is not comprehensive and has not fully addressed these issues. In this work, we present a novel scheme inspired by previous work on defining core languages for software languages like JavaScript and Python. Specifically, we define the formal semantics of Verilog using a core language called λ V , which captures the essence of Verilog using as few language structures as possible. λ V not only covers the most complete set of language features to date, but also addresses the aforementioned pitfalls. We implemented λ V with about 27,000 lines of Java code, and comprehensively tested its totality and conformance with Verilog. As a reliable reference semantics, λ V can detect semantic bugs in real-world Verilog simulators and expose ambiguities in Verilog’s standard specification. Moreover, as a useful core language, λ V has the potential to facilitate the development of tools such as a state-space explorer and a concolic execution tool for Verilog.

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V, S. Sneha, and Joe Nithin. "Implementation of Turbo Coder Using Verilog HDL for LTE." International Journal of Innovative Science and Research Technology 7, no. 7 (2022): 380–83. https://doi.org/10.5281/zenodo.6930806.

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In many communication systems, turbo codesare employed to repair errors. Turbo codes demonstrate high error correction when compared to other error correction methods. A Very Large Scale Integration is suggested in this study. VLSI architecture for the Turbo encoder implementation, Interleaves and de interleaves, and soft-in-soft-out decoders are employed. This study employs a technique that for the encoder portion, includes two recursive systematic convolutional (RSC) encoders , a Block interleaver and the decoder part involve Soft Output Virtebi Algorithm(SOVA) decoder. Aconvolutional code is a sort of error-correcting code used incommunicationsthat creates parity signals by sliding a Boolean polynomial function across a data stream. The word "convolutional coding" comes from the sliding application, which depicts the encoder's "convolution" acrossthe data. Convolutional codes sliding properties make it easier to do trellis decoding with a time-invariant trellis. Convolutional codes can be maximum-likelihood soft-decision decoded with a manageable level of complexity thanks to time invariant trellis decoding. The Viterbi algorithm, also known as the Viterbi path, is a dynamic programming approach for determining the greatest probability estimate of the most probable series of hidden states that leads to a series of observed events. The quantity of times needed to decode the bits is been reduced in this methodology. A block interleaver accepts a set of symbols and rearranges them, without repeating or omitting any of the symbols in the set. The number of symbols in each set is fixed for a given interleaver. Turbo encoding, as well as decoding simulations are done using Modelsim software.

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Fun, Chuah Ching, and Nandha Kumar Thulasiraman. "Synthesizable Verilog Code Generator for Variable-Width Tree Multipliers." Journal of Physics: Conference Series 1962, no. 1 (2021): 012046. http://dx.doi.org/10.1088/1742-6596/1962/1/012046.

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Aminuddin, Zaim Zakwan, Irni Hamiza Binti Hamzah, Ahmad Asri Abd Samat, Mohaiyedin Idris, Alhan Farhanah Abd Rahim, and Zainal Hisham Che Soh. "An FPGA application of home security code using verilog." International Journal of Reconfigurable and Embedded Systems (IJRES) 11, no. 3 (2022): 205. http://dx.doi.org/10.11591/ijres.v11.i3.pp205-214.

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Traditional entrance keys performed a number of drawbacks, including the ease with which they can be stolen, duplicated, or misplaced, allowing unauthorized people to gain access to cash, valuables, and other important documents. As known, most digital electronic entrance locks use application specific integrated circuits (ASICs) as based, which have the disadvantage of being unable to be reconfigured, as opposed to field programmable gate arrays (FPGA). This project proposed a home security code lock using verilog hardware descriptive language (HDL) with two unlocking modes, using a button or a keypad which can be changed using a switch. The 7-segment on the Altera DE2-115 trainer board is used to display the passcode press by the keypad. The result of simulation on the keypad using finite state machine (FSM) technique was fulfill the theoretical concept in which it will go to the next state each time the correct input or passcode was entered. When the wrong input or passcode was entered, it will be entered to reset mode. As the conclusion, a fully comply output according to the theoretical FSM concept is fully achieved in this project.

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Zaim, Zakwan Aminuddin, Hamiza Hamzah Irni, Asri Abd Samat Ahmad, Idris Mohaiyedin, Farhanah Abd Rahim Alhan, and Hisham Che Soh Zainal. "An FPGA application of home security code using verilog." International Journal of Reconfigurable and Embedded Systems (IJRES) 11, no. 3 (2022): 205–14. https://doi.org/10.11591/ijres.v11.i3.pp205-214.

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Wu, Jiang, Zhuo Zhang, Jianjun Xu, et al. "Detraque: Dynamic execution tracing techniques for automatic fault localization of hardware design code." PLOS ONE 17, no. 9 (2022): e0274515. http://dx.doi.org/10.1371/journal.pone.0274515.

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In an error-prone development process, the ability to localize faults is a crucial one. Generally speaking, detecting and repairing errant behavior at an early stage of the development cycle considerably reduces costs and development time. The debugging of the Verilog program takes much time to read the waveform and capture the signal, and in many cases, problem-solving relies heavily on experienced developers. Most existing Verilog fault localization methods utilize the static analysis method to find faults. However, using static analysis methods exclusively may result in some types of faults being inevitably ignored. The use of dynamic analysis could help resolve this issue. Accordingly, in this work, we propose a new fault localization approach for Verilog, named Detraque. After obtaining dynamic execution through test cases, Detraque traces these executions to localize faults; subsequently, it can determine the likelihood of any Verilog statement being faulty and sort the statements in descending order by suspicion score. Through conducting empirical research on real Verilog programs with 61 faulty versions, Detraque can achieve an EXAM score of 18.3%. Thus, Detraque is verified as able to improve Verilog fault localization effectiveness when used as a supplement to static analysis methods.

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V., Sathya, Nalayini C., M. Kiran Kumar, Kumar G., and Dinesh Babu M. "Plagiarism detection in verilog and textual content using linguistic features." Indonesian Journal of Electrical Engineering and Computer Science 38, no. 3 (2025): 1924. https://doi.org/10.11591/ijeecs.v38.i3.pp1924-1935.

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<span lang="EN-US">The illicit act of appropriating programming code has long been an appealing notion due to the immediate time and effort savings it affords perpetrators. However, it is universally acknowledged that concerted efforts are imperative to identify and rectify such transgressions. This is particularly crucial as academic institutions, including universities, may inadvertently confer degrees for work tainted by this form of plagiarism. Consequently, the primary objective of this research is to scrutinize the feasibility of identifying plagiarism within pairs of Verilog algorithms and texts. this study aims to detect plagiarism in textual content and Verilog code by leveraging diverse linguistic characteristics from the WordNet lexical database. The primary objective is to achieve optimal accuracy in identifying instances of plagiarism, incorporating features such as modifications to text structure, synonym substitution, and simultaneous application of these strategies. The system's architecture is intricately designed to unveil instances of plagiarism in both textual content and Verilog code by extracting nuanced characteristics. The systematic process includes preprocessing, detailed analysis, and post-processing, supported by a feature-rich database. Each entry in the database represents a distinctive similarity case, contributing to a thorough and comprehensive approach to plagiarism detection.</span>

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K., L. Sudha, Gowda Ganesh, K.P Gagan, and Reddy P. Adarsh. "Implementation of Luby Transform Error Correcting Codes on FPGA." International Journal of Innovative Science and Research Technology (IJISRT) 8, no. 7 (2025): 3505–10. https://doi.org/10.5281/zenodo.15001456.

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Luby Transform (LT) codes are rate less codes which are a type of fountain codes. They provide good performance over other fountain codes because, more efficient encoding and decoding algorithms can be devised for this code. These codes are rate less codes because they allow for flexible and adaptive rate allocation during the encoding process. With this, any desired code rate can be achieved by controlling the number of parity symbols generated during the encoding process. This paper explains the encoding and decoding aspects of LT codes in detail and generation and decoding is performed using MATLAB. Hardware implementation of LT code is attempted on FPGA by using Verilog code. As it is shown, the codes are very simple to implement and can be used as a more powerful error correcting codes.

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Noorbasha, Fazal, K. Hari Kishore, P. Phani Sarad, et al. "A VLSI implementation of train collision avoidance system using Verilog HDL." International Journal of Engineering & Technology 7, no. 2.8 (2018): 386. http://dx.doi.org/10.14419/ijet.v7i2.8.10468.

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Now a days we see many train accidents that occur in railways. These accidents occur mainly due to cracks in the track, human errors and not identifying the opposite train at the right time. When the train meets with the accident lot of people lose their lives and huge amount of railway property is destroyed and it also takes lot of time to hold back to the normal situations. Most of the accidents happen due to human error and due to lack of communication between the trains and irregularity of Train Traffic Control System. Normally to prevent these accidents we place sensors on either side of the platform to identify the train at right time and to receive traffic signals at the platform properly. Here we came with some different approach which is easy to manage and implement and cost effective. Normally collision occurs when two trains approaching in opposite directions on same track. So, if we manage to prevent two trains travel on the same track then collision can be avoided. Here in this project we have implemented Verilog code to solve this problem. The purpose of this project is to write a Verilog code to detect the opposite train and deviate the train based on priority of the trains thus avoiding collision. In this project we have chosen four different types of trains namely Goods, Passenger, Superfast, Express and we have implemented train collision avoidance using Verilog code by giving priority to each type of train and preference is given to one train to avoid collision.

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Yamini, R., and M. V. Ramya. "Design and Verification of UART using System Verilog." International Journal of Engineering and Advanced Technology (IJEAT) 9, no. 5 (2020): 1208–11. https://doi.org/10.35940/ijeat.E1135.069520.

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The main objective of this paper is to design and verify a full duplex UART module using System Verilog (SV). It is a serial communication protocol which provides communication between the systems without using clock signal. It converts parallel data into serial format and transmits the same. Once the data in serial format is received it is converted into parallel format. Designing of UART includes designing of baud rate generator, receiver, transmitter, interrupt and FIFO modules. Verification involves verifying the design by creating verification environment which allows to reuse the testbench and reduces the code complexity. Randomization is used to check the corner conditions which are hard to reach. 100% assertion and 100% functional coverage is achieved. UART operation is simulated using Questasim software

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Sharma, Anukrati, Aparna Mittal, and Anshika Singh. "Design and Implementation of Braun Multiplier using Verilog: Research." International Journal for Research in Applied Science and Engineering Technology 12, no. 5 (2024): 3378–92. http://dx.doi.org/10.22214/ijraset.2024.62374.

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Abstract: Multiplication is widely used in places like digital signal processing, image processing, instrumentation that require multilayer components. Carry Save Adder and ripple carry adder both are used in parallel processing architecture. They are widely used for signed multiplication i.e. for both negative and positive numbers. We have now designed a Braun multiplier (BM) to improve the speed, power and area capability. We are using the Xilinx tool to verify Braun multipliers using Verilog. We are taking the following considerations: checking using FPGA based instruments and implementing code using Verilog-VHDL. The adders are integrated into multipliers. The result of this research is to modify BM to improve the performance along with reduction in power consumed and also using less area.

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Kwon, Bo-Seung, Sang-Won Jung, Young-Dan Noh, Jong-Sik Lee, and Young-Shin Han. "RTL-DEVS: HDL Design and Simulation Methodology for DEVS Formalism-Based Simulation Tool." Telecom 4, no. 1 (2022): 15–30. http://dx.doi.org/10.3390/telecom4010002.

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DEVS (Discrete Event System Specification) is widely used in modeling and simulation fields to design, validate, and implement complex response systems. DEVS provides a robust formalism for system design using event-driven, state-based models with explicitly defined temporal information. We extend the RTL-DEVS model based on DEVS formalism to enable part of Verilog simulation in DEVS-based simulation tools. The simulation based on RTL-DEVS methodology, which imitates Verilog’s testbench and behavioral module, confirmed through experiments that RTL simulation can be performed sufficiently through the code elaboration process. In multiple simulation results, Verilog simulation and RTL-DEVS-based simulation were able to output equivalent results under limited conditions. DEVS formalism-based modeling can be extended to other DEVS-based simulators when using model-type exchange tools, and this means that the advanced functions or classes of RTL simulation tools can be applied using higher-level language tools.

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Koppala, Neelima, Nagarajan Ashok Kumar, Satyam Satyam, and Neeruganti Vikram Teja. "Proficient matrix codes for error detection and correctionin 8-port network on chip routers." Indonesian Journal of Electrical Engineering and Computer Science 29, no. 3 (2023): 1336. http://dx.doi.org/10.11591/ijeecs.v29.i3.pp1336-1344.

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This paper verifies the applicability of the proposed code to dynamic Network on Chips that have variable faulty blocks with runtime suggesting an online error detection mechanism with adaptive routing algorithm that bypasses faulty components dynamically and the router architecture uses additional diagonal state indications for the reliable network on chip (NoC) operation. In NoC, the permanently faulty routers are disconnected to enable high runtime throughput as data packets are not lost due to self-loopback mechanism. The proposed proficient matrix codes use the capabilities of decimal matrix code technique with minimum check bits for maximum error correction capability. The proposed code is compared with existing codes such as decimal matrix codes, modified decimal matrix codes and parity matrix codes. The codes are developed in verilog hardware description language and simulated in the Xilinx ISE 14.5 tool. This proficient matrix code proves to be efficient for multiple adjacent error detection and correction with trade off in delay. Also 65% code rate is achieved with 22.73% less redundant bits that occupy less area by atleast 11.78%. The codes when used for increased data sizes like 8, 16, 32, and 64 bits, the power delay product decreased by atleast 1.74%.

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Neelima, Koppala, Ashok Kumar Nagarajan, Satyam, and Vikram Teja Neeruganti. "Proficient matrix codes for error detection and correctionin 8-port network on chip routers." Proficient matrix codes for error detection and correctionin 8-port network on chip routers 29, no. 3 (2023): 1336–44. https://doi.org/10.11591/ijeecs.v29.i3.pp1336-1344.

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Sridhar, Krishna. "A Review on Implementation of UART Using System Verilog." INTERANTIONAL JOURNAL OF SCIENTIFIC RESEARCH IN ENGINEERING AND MANAGEMENT 09, no. 01 (2025): 1–9. https://doi.org/10.55041/ijsrem40884.

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UART is one of the most utilized protocols in digital communication systems, which enables efficient serial data transfer between any devices. This paper discusses the design and implementing and simulating a UART module that was first implemented in Vivado without SDK and then changed to EDA Playground. Challenges faced in Vivado as well as those faced afterwards in Visual Studio Code with the success afterward in EDA Playground are discussed as well. The behavioral aspects of UART, including its functionality, protocol compliance, and simulation waveforms, are examined to provide a comprehensive understanding of its operation. Index Terms—UART, Transmitter, Receiver, System Verilog, Vivado, Simulation, EDA playground

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Vidya, Sagar Potharaju*. "FPGA IMPLEMENTATION OF ELLIPTIC CURVE DISCRETE LOGARITHMUSING VERILOG HDL." GLOBAL JOURNAL OF ENGINEERING SCIENCE AND RESEARCHES 4, no. 11 (2017): 151–62. https://doi.org/10.5281/zenodo.1067986.

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Elliptic Curve Discrete Logarithm (ECDL) are most popular choice Elliptic Curve Cryptography (ECC),which gives provision for shorter key lengths as compared to as compared to its counterpart public key cryptosystems, and it can be used for security in embedded systems,wirless communications and personal communication systems. In this paper Elliptic Curve Discrete Logarithm code has been written in Verilog Hardware Description Language (HDL) and implemented on Xilinx Spartan3E Field Programmable Gate Array (FPGA),has taken 403 encoders, decoders with minimum period of 5.043 ns,maximum frequency 198.295 MHz and with a total memory usage of 269824 Kilobytes respectively. The performance of the crypto system is much faster than the software implementation of the same system

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Sardar, Rupam. "2:1 Multiplexer, 1:2 De-multiplexer,2:4 Decoder and 4:2 Encoder Circuit Design with CMOS Technology Implementing with Artificial Neural Network with Verilog HDL Code for Output." INTERANTIONAL JOURNAL OF SCIENTIFIC RESEARCH IN ENGINEERING AND MANAGEMENT 08, no. 03 (2024): 1–11. http://dx.doi.org/10.55041/ijsrem29098.

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The goal of this project is to create a De-multiplexer gate using a complementary metal oxide semiconductor (CMOS) and an artificial neural network.When designing any COMS circuit, we always keep in mind that the lowest possible cost should be the aim.In this work, the circuit was designed using a multilayer artificial neural network. We utilize weights to alter the value and treat negative values as inverters and neurons as transistors in our work.We are also developing Verilog-HdL code to easily apply the De-multiplexer for experimenting with an artificial neural network and set weights to acquire the desired results. The purpose of this project is to use an artificial neural network and a complementary metal oxide semiconductor (CMOS) to develop a decoder gate.We constantly keep in mind that the goal should be to construct a COMS circuit at the lowest feasible cost.An artificial neural network with multiple layers was used to create the circuit in this work. In our study, we treat negative values as inverters and neurons as transistors, and we modify the value using weights.Additionally, we are creating Verilog-HdL code that will make it simple to use the Decoder to experiment with artificial neural networks and adjust weights to get the desired outcomes. The purpose of this project is to use an artificial neural network and a complementary metal oxide semiconductor (CMOS) to develop a decoder gate.We constantly keep in mind that the goal should be to construct a COMS circuit at the lowest feasible cost.An artificial neural network with multiple layers was used to create the circuit in this work. In our study, we treat negative values as inverters and neurons as transistors, and we modify the value using weights.Additionally, we are creating Verilog-HdL code that will make it simple to use the Decoder to experiment with artificial neural networks and adjust weights to get the desired outcomes. The purpose of this research is to use an artificial neural network and a complementary metal oxide semiconductor (CMOS) to produce a multiplexer gate.We always keep in mind that the lowest feasible cost should be the goal while designing any COMS circuit.This work used a multilayer artificial neural network to design the circuit. In our work, we treat neurons as transistors and negative values as inverters, and we use weights to adjust the value.In order to effortlessly apply the Multiplexer for experimenting with an artificial neural network and set weights to obtain the desired results, we are also building Verilog-HdL code.Keywords: Multiplexer, CMOS,ANN,Verilog-HDL. Keywords: Multiplexer De-multiplexer, Decoder, Encoder Verilog-HDL, CMOS, ANN, Verilog HDL

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Hwang, Dong Hyun, Chang Yeop Han, Hyun Woo Oh, and Seung Eun Lee. "ASimOV: A Framework for Simulation and Optimization of an Embedded AI Accelerator." Micromachines 12, no. 7 (2021): 838. http://dx.doi.org/10.3390/mi12070838.

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Artificial intelligence algorithms need an external computing device such as a graphics processing unit (GPU) due to computational complexity. For running artificial intelligence algorithms in an embedded device, many studies proposed light-weighted artificial intelligence algorithms and artificial intelligence accelerators. In this paper, we propose the ASimOV framework, which optimizes artificial intelligence algorithms and generates Verilog hardware description language (HDL) code for executing intelligence algorithms in field programmable gate array (FPGA). To verify ASimOV, we explore the performance space of k-NN algorithms and generate Verilog HDL code to demonstrate the k-NN accelerator in FPGA. Our contribution is to provide the artificial intelligence algorithm as an end-to-end pipeline and ensure that it is optimized to a specific dataset through simulation, and an artificial intelligence accelerator is generated in the end.

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J, Padmini, and V. Nanammal. "FPGA Implementation of Digital Modulation Schemes Using Verilog HDL." International Journal for Research in Applied Science and Engineering Technology 10, no. 9 (2022): 560–67. http://dx.doi.org/10.22214/ijraset.2022.46596.

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Abstract: This paper describes the design and development of an FPGA-based digital Modulation Scheme for high-resolution Communication Application. We are focusing on implementation of Verilog based code simulation for fundamental and widely used digital modulation techniques such as Binary Amplitude-shift keying (BASK), Binary Frequency-shift keying (BFSK), Binary Phase-shift keying (BPSK) and Quadrature Phase Shift Keying(QPSK). In this work the idea of sinusoidal signals that have been generated is plain sailing in nature and based on fundamentals of signal sampling and quantization. Such concept of sinusoidal signals generation is not unfamiliar but somehow simplified using sampling and quantization in time and amplitude domain, respectively. The whole simulation is done on Modelsim and Xilinx-ISE using VERILOG Hardware descriptive language. The work has been accomplished on Thirty two bit serial data transmission with self-adjustable carrier frequency and bit duration length.

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Sardar1, Rupam, Sudip Ghosh2, and Bimal Datta3. "Full Adder Circuit Design with CMOS Technology Implementing with Artificial Neural Network with Verilog HDL Code for Output." INTERANTIONAL JOURNAL OF SCIENTIFIC RESEARCH IN ENGINEERING AND MANAGEMENT 08, no. 03 (2024): 1–11. http://dx.doi.org/10.55041/ijsrem29060.

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The goal of this research is to create Full-Adder gate using a Complementary Metal Oxide Semiconductor (CMOS) and an Artificial Neural Network.We constantly bear in mind that any COMS circuit we design should be as inexpensive as possible.Multilayer ANN was employed in this work to create the circuit. Weights are employed to modify the value in our study, treating neurons as transistors and treating negative values as inverters.We are also designing Verilog-HdL Code to simply apply the full adder for experimenting an artificial neural network assigning weights to get appropriate results. Keywords: Full Adder, CMOS,ANN,Verilog-HDL

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Ballo, Andrea, Michele Bottaro, Alfio Dario Grasso, and Gaetano Palumbo. "Regulated Charge Pumps: A Comparative Study by Means of Verilog-AMS." Electronics 9, no. 6 (2020): 998. http://dx.doi.org/10.3390/electronics9060998.

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This paper proposes a comparative study of regulation schemes for charge-pump-based voltage generators using behavioral models in Verilog- Analog Mixed Signal (AMS) code. An accurate and simple model of the charge pump is first introduced. It allows reducing the simulation time of complex electronic systems made up by both analog and digital circuits while maintaining a good agreement with transistor-level simulations. Finally, a comprehensive comparative study of the different regulation schemes for charge pumps is reported which allows the designer to choose the most suitable topology for a given application and Charge Pump (CP) operative zone.

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Xu, Mei Hua, Qin Yu, and Ai Ying Guo. "Design and Realization of Efficient Verification Platform Based on System Verilog." Advanced Materials Research 945-949 (June 2014): 1903–7. http://dx.doi.org/10.4028/www.scientific.net/amr.945-949.1903.

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Adopting the Verification Methodology Manual’s (VMM) hierarchical structure, this paper presents a design of available verification platform based on System Verilog adopted. The platform completed can implement constrained-random test, directed test, and error stimulus test with high efficiency; moreover, gain maximum code reuse. Using Direct Programming Interface (DPI), the verification platform can conveniently link C++ with the model that realized the function of Design Under Test (DUT), and then to test it. At last the paper shows the experiment results to prove the effectiveness and practicality of the platform by verification sample of HOG chip.

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Li, Guo Hong, Wei Yan Lang, Xu Bai, and Hui Hu. "Design of FIR Digital Filter Based on CSD Code." Applied Mechanics and Materials 462-463 (November 2013): 619–22. http://dx.doi.org/10.4028/www.scientific.net/amm.462-463.619.

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A high precision FIR digital filter is achieved based on CSD code. The characteristic of CSD coding is described and the structure of the FIR filter based on time division multiplex is given. FIR filter coefficients is generated by fadtool of MATLAB . The digital filter module is designed by Verilog HDL and simulated under QUARTUS II and MATLAB environment. The results show that the design can improve the accuracy of data acquisition significantly and reduce the use of FPGA resource.

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Somashekhar, Vikas Maheshwari, and R. P. Singh. "FPGA Implementation of Fault Tolerant Adder using Verilog for High Speed VLSI Architectures." International Journal of Engineering and Advanced Technology 9, no. 4 (2020): 549–51. http://dx.doi.org/10.35940/ijeat.d7062.049420.

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The main objective is to detect and reduce the faults in full adder design using self checking and self repairing adder block. The rate of chip failure is directly proportional to chip density. This fault tolerant adder has high speed (Delay is 6.236ns) & implemented on FPGA Spartan 3 using XC3S50 device. The source code is written in verilog. In this design faults are identified and repaired using self checking and self repairing full adder methodologies.

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Somashekhar, Maheshwari Vikas, and P. Singh R. "FPGA Implementation of Fault Tolerant Adder using Verilog for High Speed VLSI Architectures." International Journal of Engineering and Advanced Technology (IJEAT) 9, no. 4 (2020): 549–51. https://doi.org/10.35940/ijeat.D7062.049420.

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M S, Harish M. S., and Jayadevappa D. "Design & Simulation Of 64-Bit Hybrid Processor Instruction Set Using Verilog." International Journal of Engineering & Technology 7, no. 4.36 (2018): 373. http://dx.doi.org/10.14419/ijet.v7i4.36.23809.

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As a part of my ongoing research on implementation of multi core hybrid processor on FPGA, I have developed data flow designs for most popularly used 20 processor instructions. I have made digital design, wrote code in Verilog HDL and simulated all the 20 instructions using Xilinx ISE 14.5. The data flow designs, symbolic representation and simulation results are explained in detail in this technical paper. This is partial implementation of Hybrid Processor & the other sub modules implementation on Xilinx FPGA will be published in my subsequent technical paper.

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Li, Zhen. "Design and implementation of 4-bit absolute value detector based on verilog HDL." Applied and Computational Engineering 19, no. 1 (2023): 190–96. http://dx.doi.org/10.54254/2755-2721/19/20231031.

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Absolute value detectors are widely utilized in many disciplines, such as image processing, speech recognition, and control systems, due to the advancement of digital signal processing and computer vision technologies. This paper presents a 4-bit absolute value detector based on the Verilog HDL programming language. Absolute value detectors are extensively used in signal processing, computer vision, and other fields to determine if the absolute value of the input signal meets specific conditions. This paper describes in detail the design process, including module analysis, the drawing of state transfer diagrams, the writing of Verilog HDL code, and simulation verification with a focus on practical applications. The results demonstrate that the absolute value detector is accurate and reliable in determining whether the absolute value of the input signal is greater than or equal to the threshold value.

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Ge, Yue Tao, Xiao Ming Liu, and Xiao Tong Yin. "Study on the Decoder for Reed-Solomon (255, 239) Code." Applied Mechanics and Materials 482 (December 2013): 390–93. http://dx.doi.org/10.4028/www.scientific.net/amm.482.390.

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Reed Solomon code is described as a theoretical decoder that corrected errors by finding the most popular message polynomial. The Verilog language is applied to descript decoding algorithm. Cyclone series FPGA EP1C6Q240C8 is adopted as a core of hardware platform and a serial port communication part is used to receive input error correction data. The results show that it can successfully correct eight errors, which is the limitation of error correction. With the RS decoder, it can ensure that the strong error correction capability and fast speed.

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Gurmeet, Kaur Arora. "Design of VLSI Architecture for a Flexible Testbed of Artificial Neural Network for Training and Testing on FPGA." International Journal of Innovative Science and Research Technology 8, no. 5 (2023): 2605–11. https://doi.org/10.5281/zenodo.8099424.

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General-Purpose Processors (GPP)-based computers and Application Specific Integrated Circuits (ASICs) are the typical computing platforms used to develop the back propagation (BP) algorithm-based Artificial Neural Network (ANN) systems, but these computing devices constitute a hurdle for further advanced improvements due to a high requirement for sustaining a balance between performance and flexibility. In this work, architecture for BP learning algorithm using a 16-bit fixed- point representation is designed for the classification of handwritten digits on a field- programmable gate array (FPGA). The proposed design is directly coded and optimized for resource utilization and frequency in Verilog Hardware Description Language (HDL) and synthesized on the ML-605 Virtex 6 evaluation board. Experimental results show 10 times speedup and reduced hardware utilization when compared with existing implementations from literature. The architecture is expandable to other specifications in terms of number of layers, number of neurons in each layer, and the activation function for each neuron. The correctness of the proposed design is authenticated by comparing parameters obtained through Python code and Verilog.

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Roy, K. Sripath, K. Abhiram, M. Arun Sumanth, et al. "Development of graphical user interface for open source VLSI digital synthesis tool Qflow." International Journal of Engineering & Technology 7, no. 2 (2018): 710. http://dx.doi.org/10.14419/ijet.v7i1.1.12649.

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There are many tools that are used for simulation in the domain of VLSI technology but none of them are easily accessible. There is a need for Free and open source tools in this stream so as to make them accessible to everyone. There are efficient tools that already exist in open source in VLSI stream but are not used widely because of their command line user interface. Hence, creating a user friendly interface will help many developers and users to work easily. This paper deals with the idea to solve the above issue by creating a Graphical User Interface for the open source VLSI tool called QFlow. Qflow is a tool used in synthesizing a VLSI circuit from the Verilog source code. There are multiple tools integrated with this tool to assure the simulation process. It is a combination of many dependencies that are used for synthesis, placement, layout viewing and routing in a fabrication process. All the independent tools used for the Verilog code simulation are integrated onto a single platform. Qt is used for creating the cross-stage application.

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Krishnaiah, V. V. Jaya Rama, P. G. K. Sirisha, S. Parvathi Vallabhaneni, et al. "AI-Driven WSN for Precise Aquatic Pollution Detection Using an Intelligent Monitoring Approach." PROOF 4 (December 10, 2024): 114–22. https://doi.org/10.37394/232020.2024.4.11.

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The proliferation of digital devices, sensors, and interconnected systems has led to an explosion of data. Simple sensors like pH, conductivity, and Turbidity sensors can be used for the classification of gasoline and diesel in water. These sensors are easy to set up and deploy, so they can be installed in vast numbers and can get real-time data from the site. FPGAs are very fast in processing complex data and have low latency time compared to other traditional microcontrollers. But FPGA accepts coding in Hardware Description Languages like Verilog or VHDL, which can be very complex to code complex models that are trained in other high-level languages like Python and C++. Simple classification models in machine learning are implemented using High-Level Synthesis tools, which accept codes written in languages like C, C++, or SystemC, and translate them into hardware-implementable RTL (Register- Transfer Level) code. The data from two major components of oil, gasoline, and petrol are used to train various classification models with widely used libraries in Python. The trained parameters are extracted from the trained model. The parameters are then assembled and then coded in C++ as currently most of the tools support C++. Some modifications need to be made to the original code to make it compatible with the synthesis tool.

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B. Ravi kumar, Kunta Nikhitha, Punnami Manogna, and Begampeta Nanda kishore. "Implement I2C Protocol for Secure Data Transfer Using Verilog." International Research Journal on Advanced Science Hub 7, no. 01 (2025): 51–59. https://doi.org/10.47392/irjash.2025.007.

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Digital The I2C (Inter-Integrated Circuit) protocol is widely used in embedded systems for enabling communication between various devices such as sensors, microcontrollers, and other peripherals. However, early implementations of the I2C protocol focused primarily on data transfer efficiency rather than security This project aims to implement a secure data transfer mechanism for the I2C protocol using Verilog, a hardware description language widely used for designing and modelling electronic systems. Our implementation enhances the traditional I2C protocol by integrating security features that protect data from unauthorized access during transmission. By using encryption and authentication techniques, the project ensures that data integrity and confidentiality are maintained throughout the communication process. The Xilinx Vivado Design Suite is utilized for the synthesis, simulation, and testing of the secure I2C protocol. Xilinx software provides a robust environment for designing hardware-based systems, offering features such as timing analysis, design optimization, and resource management. The secure I2C protocol was implemented and simulated using Verilog code within this software, enabling thorough testing and debugging prior to hardware deployment. The hardware component of the project is based on the Zybo Z7 development board. The Zybo Z7 kit provides an ideal platform for prototyping and testing the secure I2C protocol, as it allows for real-time interaction between the FPGA and peripheral devices connected through I2C communication. By running the implemented design on this hardware, we were able to evaluate the real-world performance and security of the system. The results demonstrate that the secure I2C protocol operates efficiently on the Zybo Z7 kit, with minimal impact on system performance. The integration of security features did not introduce significant latency or resource overhead, indicating that secure communication can be achieved without compromising speed or functionality. This successful implementation highlights the feasibility of deploying secure I2C protocols in hardware systems where data protection is a priority.

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Tran, Thang Viet, Giao N. Pham, Anh N. Bui, et al. "Hardware Designs of Cyclic Redundancy Check Code with Calculation Time Trade-Off Strategy." International Journal of Emerging Technology and Advanced Engineering 12, no. 6 (2022): 170–76. http://dx.doi.org/10.46338/ijetae0622_06.

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This paper will discuss the design of cyclic redundancy check code (CRC), a most popular error detecting scheme in intelligent communication. At first, the concepts of CRC are given in detail with mathematical model and software simulation in python scripts. And mainly, with calculation time trade-off strategy, we provide the CRC hardware design with three architecture models serial, parallel, hybrid serial and parallel. Keywords: Error Detection Scheme; Cyclic Redundancy Check; Python; Verilog HDL; Digital System Design

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Noras, James M. "Protecting CAD Files During Development: The Sunos SCCS System." International Journal of Electrical Engineering & Education 32, no. 3 (1995): 256–64. http://dx.doi.org/10.1177/002072099503200306.

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Protecting CAD files during development: the SunOS SCCS system This is a practical introduction to the Source Code Control System (SCCS) for the development and protection of text-files. Familiar in software projects, it can be a valuable aid for CAD using textual hardware description. A Verilog example illustrates the method, and then the system's most useful features are explained.

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Suhaili, Shamsiah binti, and Takahiro Watanabe. "High-Throughput of SHA-256 Hash Function with Unfolding Transformation." Global Journal of Engineering and Technology Review Vol.4 (4) October-December. 2019 4, no. 4 (2019): 73–81. http://dx.doi.org/10.35609/gjetr.2019.4.4(1).

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Hash Function in cryptography algorithms is used to encrypt the message by giving the appropriate output based on the structure of the hash function itself. This algorithm is important for security applications such as Keyed-Hash Message Authentication Code (HMAC), digital signature, and others. There are different types of hash functions such as MD5, SHA-1, RIPEMD-160, SHA-256, SHA-224, SHA-384, SHA-512, and others. In this paper, the unfolding transformation method was proposed to improve the throughput of the SHA-256 hash function. Three types of SHA-256 hash function were designed namely SHA-256 design, SHA-256 design inner pipelining with unfolding factor 2, and SHA-256 design inner pipelining with unfolding factor 4. The designs were written in Verilog code and the output simulations were verified using ModelSim. The simulation results showed that the proposed SHA-256 inner pipelining unfolding with factor 4 provided the highest throughput which is 4196.30 Mbps, and factor 2 was superior in terms of maximum frequency and was better than the conventional SHA-256 design. Type of Paper: other. Keywords: Cryptography algorithm; FPGA; SHA-256 Hash Function; Unfolding transformation, Verilog

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Noorbasha, Fazal, and K. Suresh. "FPGA implementation of RGB image encryption and decryption using DNA cryptography." International Journal of Engineering & Technology 7, no. 2.8 (2018): 397. http://dx.doi.org/10.14419/ijet.v7i2.8.10469.

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The rapid growth in digitization transmission of information in the form of RGB image. During the process transmission of the image in a channel, some data may be degraded due to noise. At receiver side error in data has to be detected and corrected. Hamming code is one of the popular techniques for error detection and correction. In this paper new algorithm proposed for encryption and decryption of RGB image with DNA cryptography and hamming code for secure transmission, and correction. this algorithm first encodes data to hamming code and encrypted to DNA code. Two-bit error detection and correction for each pixel of the image can be performed.DNA code improves security and use of the Hamming code for error detection and correction. For the image of size 256*256 pixel image, it corrects up to 2*256*256 bits in RGB image. The RGB image encryption and decryption design using Verilog and implemented using FPGA (Field Programmable Gate Array).

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Lee, Yonghun, and Daejin Park. "Fast Verilog Simulation using Tcl-based verification code generation for Dynamically Reloading from Pre-Simulation Snapshot." Journal of the Korea Institute of Information and Communication Engineering 27, no. 4 (2023): 545–51. http://dx.doi.org/10.6109/jkiice.2023.27.4.545.

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Ibrahimy, Muhammad Ibn. "FPGA Implementation of Multiplier for Floating-Point Numbers Based on IEEE 754-2008 Standard." Journal of Communications Technology, Electronics and Computer Science 1 (October 22, 2015): 1. http://dx.doi.org/10.22385/jctecs.v1i0.2.

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This paper illustrates designing and implementation process of floating point multiplier on Field Programmable Gate Array (FPGA). Floating-point operations are used in many fields like, digital signal processing, digital image processing, multimedia data analysis etc. Implementation of floating-point multiplication is handy and easy for high level language. However it is a challenging task to implement a floating-point multiplication in hardware level/low level language due to the complexity of algorithm. A top-down approach has been applied for the prototyping of IEEE 754-2008 standard floating-point multiplier module using Verilog Hardware Description Language (HDL). Electronic Design Automation (EDA) tool of Altera Quartus II has been used for floating-point multiplier. The hardware implementation has been done by downloading the Verilog code onto Altera DE2 FPGA development board and found a satisfactory performance.

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Sakthivel, R., Ch Vijayalakshmi, M. Vanitha, et al. "Hardware optimization for effective switching power reduction during data compression in GOLOMB rice coding." PLOS ONE 19, no. 9 (2024): e0308796. http://dx.doi.org/10.1371/journal.pone.0308796.

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Loss-less data compression becomes the need of the hour for effective data compression and computation in VLSI test vector generation and testing in addition to hardware AI/ML computations. Golomb code is one of the effective technique for lossless data compression and it becomes valid only when the divisor can be expressed as power of two. This work aims to increase compression ratio by further encoding the unary part of the Golomb Rice (GR) code so as to decrease the amount of bits used, it mainly focuses on optimizing the hardware for encoding side. The algorithm was developed and coded in Verilog and simulated using Modelsim. This code was then synthesised in Cadence Encounter RTL Synthesiser. The modifications carried out show around 6% to 19% reduction in bits used for a linearly distributed data set. Worst-case delays have been reduced by 3% to 8%. Area reduction varies from 22% to 36% for different methods. Simulation for Power consumption shows nearly 7% reduction in switching power. This ideally suggest the usage of Golomb Rice coding technique for test vector compression and data computation for multiple data types, which should ideally have a geometrical distribution.

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Jiang, Wangye. "Explanation of the principles of the Booth algorithm, Verilog implementation and simulation." Highlights in Science, Engineering and Technology 119 (December 11, 2024): 892–98. https://doi.org/10.54097/w2trr971.

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In an era marked by heightened constraints on computer processing speed and storage capacity, optimizing computational efficiency and space utilization assumes paramount importance. Consequently, the deployment of proficient algorithmic tools holds significant significance within the realm of computing. The principal categories of multipliers encompass conventional multipliers, shift-and-add multipliers, Look-Up Table (LUT) multipliers, and Booth algorithm multipliers. Among these, the Booth algorithm substantially influences multiplier performance enhancement. This paper investigation commences with a comprehensive elucidation of the mathematical underpinnings of the Booth algorithm. Subsequently, it involves the development of code corresponding to the mathematical expressions, which is executed within the VIVADO environment. Given the inherent simplicity of the experiment, virtual simulation is directly conducted in VIVADO. The analysis is grounded in the examination of data waveforms. Ultimately, the output waveform is correlated with the BOOTH mathematical formula, culminating in the successful implementation of the BOOTH algorithm. This paper aims to effectively curtail the presence of '1's in computer data, thereby reducing the computational steps and conserving operational space. This, in turn, leads to a notable acceleration in the computational speed, accomplishing the objective of enhancing computational efficiency.

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Lagadapati, Naresh, Manoj Karri, Tejaswini Vaddineni, Sk Mahaboob Subhani, and K. Hari Kishore. "A VLSI implementation of elevator control based on finite state machine using Verilog HDL." International Journal of Engineering & Technology 7, no. 2.8 (2018): 92. http://dx.doi.org/10.14419/ijet.v7i2.8.10337.

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In this cutting edge period, lifts have turned into a basic piece of any business or open complex. It encourages the quicker development of individuals and gear between floors. The lift control framework is a standout amongst the most critical perspectives in hardware control module that are utilized as a part of car application. Normally lifts are intended for a particular building considering the fundamental factors, for example, the tallness of the building, the quantity of individuals venturing out to each floor and the normal times of high utilization. The lift framework is composed with various control procedures. This usage depends on FPGA, which can be utilized for a working with any number of floors, with the predetermined sources of info and yields. This controller can be executed for a lift with the required number of floors by just changing a control variable in the HDL code. This approach depends on a calculation which decreases the measure of calculation required, by concentrating just on the pertinent guidelines that enhances the execution of the gathering of lift framework.

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Wang, Jie, Zhanfei Chen, Shuzhen You, Benoit Bakeroot, Jun Liu, and Stefaan Decoutere. "Surface-Potential-Based Compact Modeling of p-GaN Gate HEMTs." Micromachines 12, no. 2 (2021): 199. http://dx.doi.org/10.3390/mi12020199.

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We propose a surface potential (SP)-based compact model of p-GaN gate high electron mobility transistors (HEMTs) which solves the Poisson equation. The model includes all possible charges in the GaN channel layer, including the unintended Mg doping density caused by out-diffusion. The SP equation and its analytical approximate solution provide a high degree of accuracy for the SP calculation, from which the closed-form I–V equations are derived. The proposed model uses physical parameters only and is implemented in Verilog-A code.

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Mazurkiewicz, Tomasz. "An efficient hardware implementation of a combinations generator." Technical Sciences 4, no. 20 (2017): 405–13. http://dx.doi.org/10.31648/ts.5436.

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In this paper an area-efficient hardware implementation of a Bincombgen algorithm was presented. This algorithm generates all (n,k) combinations in the form of binary vectors. The generator was implemented using Verilog language and synthesized using Xilinx and Intel-Altera software. Some changes were applied to the original code, which allows our FPGA implementation to be more efficient than in the previously published papers. The usage of chip resources and maximum clock frequency for different values of n and k parameters are presented.

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Kamkin, Alexander Sergeevich, Mikhail Mikhaylovich Chupilko, Mikhail Sergeevich Lebedev, Sergey Aleksandrovich Smolov, and Georgi Gaydadjiev. "Comparison of High-Level Synthesis and Hardware Construction Tools." Proceedings of the Institute for System Programming of the RAS 34, no. 5 (2022): 7–22. http://dx.doi.org/10.15514/ispras-2022-34(5)-1.

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Application-specific systems with FPGA accelerators are often designed using high-level synthesis or hardware construction tools. Nowadays, there are many frameworks available, both open-source and commercial. In this work, we attempt to fairly compare several existing solutions (languages and tools), including Verilog (our baseline), Chisel, Bluespec SystemVerilog (Bluespec Compiler), DSLX (XLS), MaxJ (MaxCompiler), and C (Bambu and Vivado HLS). Our analysis has been carried out using a representative example of 8×8 inverse discrete cosine transform (IDCT), a widely used algorithm engaged in, among others, JPEG and MPEG decoders. The metrics under consideration include: (a) the degree of automation (how much less code is required compared to Verilog), (b) the controllability (possibility to achieve given design characteristics, namely a given ratio of the performance and area), and (c) the flexibility (ease of design modification to achieve certain characteristics). Rather than focusing on computational kernels only, we have developed AXI-Stream wrappers for the synthesized implementations, which allows adequately evaluating characteristics of the designs when they are used as parts of real computer systems. Our study shows clear examples of what impact specific optimizations (tool settings and source code modifications) have on the overall system performance and area. It emphasizes how important is to be able to control the balance between the communication interface utilization and the computational kernel performance and delivers clear guidelines for the next generation tools for designing FPGA accelerator based systems.

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Amirtha, Sneha Sri, and S. Sumathi. "Design of 32 bit synchronous RISC-V reversible gates processor using verilog." International Journal of Engineering, Science and Technology 17, no. 1 (2025): 111–32. https://doi.org/10.4314/ijest.v17i1.8.

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One of the key components of computer hardware is the design of processor that comes under the domain of Electronic Engineering. To design a microprocessor, first an instruction set is chosen and a microarchitecture is defined and the entire module can be described by means of Hardware Description Language. After the processor is designed it is subjected into design verification and validation and then it is fabricated. The design of the RISC-V processor is too simple as the architecture is open source and consists of load/store architecture. The main aim of the paper is to design the synchronous RISC-V reversible gates processor using VerilogHDL and to figure out performance issues such as area, power dissipation and execution time. The synchronous processors reduce crosstalk thereby integrating multi rate circuits easily along with component reusability and less power dissipation. The processor with reversible logic gates have an advantage that the data stored cannot be erased as it has one to one mapping. In this paper, the 32 bit synchronous processor is designed with RISC-V architecture and several modules like jump adder, Program Counter Adder, Arithmetic and Logic Unit, Arithmetic and Logic Control Unit, Program Counter Mux, Control Unit, Instruction Memory, Register, Write Data Mux, ALU Decoder, Data Memory, Immediate Generation, Program Counter Assign are designed using Verilog HDL and Simulation results are obtained using testbench code collected from GitHub repository titled VLSI System Design. The analogy between Synchronous Processor and Asynchronous Processor, RISC-V and MIPS architecture, Reversible and Irreversible Logic Gates are analysed and performance metrics like execution time, power consumption and area are significantly reduced as the synchronous processor is designed with one to one mapping logic which can be used in quantum applications.

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Feng, Lang, Jeff Huang, Jiang Hu, and Abhijith Reddy. "FastCFI: Real-time Control-Flow Integrity Using FPGA without Code Instrumentation." ACM Transactions on Design Automation of Electronic Systems 26, no. 5 (2021): 1–39. http://dx.doi.org/10.1145/3458471.

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Control-Flow Integrity (CFI) is an effective defense technique against a variety of memory-based cyber attacks. CFI is usually enforced through software methods, which entail considerable performance overhead. Hardware-based CFI techniques can largely avoid performance overhead, but typically rely on code instrumentation, forming a non-trivial hurdle to the application of CFI. Taking advantage of the tradeoff between computing efficiency and flexibility of FPGA, we develop FastCFI, an FPGA-based CFI system that can perform fine-grained and stateful checking without code instrumentation. We also propose an automated Verilog generation technique that facilitates fast deployment of FastCFI, and a compression algorithm for reducing the hardware expense. Experiments on popular benchmarks confirm that FastCFI can detect fine-grained CFI violations over unmodified binaries. When using FastCFI on prevalent benchmarks, we demonstrate its capability to detect fine-grained CFI violations in unmodified binaries, while incurring an average of 0.36% overhead and a maximum of 2.93% overhead.

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