Relevant bibliographies by topics / Von Neumann bottleneck

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  1. Journal articles
  2. Dissertations / Theses
  3. Book chapters
  4. Conference papers

Academic literature on the topic 'Von Neumann bottleneck'

Author: Grafiati
Published: 4 June 2025
Last updated: 15 July 2025

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Journal articles on the topic "Von Neumann bottleneck"

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Kumbhar, Gaurang. "Synaptic AI: Bridging Neural Dynamics and Deep Learning for Next- Generation Computation." International Scientific Journal of Engineering and Management 04, no. 04 (2025): 1–7. https://doi.org/10.55041/isjem02829.

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The escalating computational and power demands of deep learning algorithms challenge traditional von Neumann architectures, which separate memory and processing units. This structural bottleneck, often referred to as the "von Neumann bottleneck," hampers data throughput and energy efficiency—especially in real-time, data-intensive AI applications. Neuromorphic computing, inspired by the human brain's architecture and function, offers a promising alternative. Unlike conventional systems, neuromorphic models integrate processing and memory, enabling highly parallel, event-driven computation. This design drastically reduces latency and power consumption. The brain's remarkable ability to process complex patterns using minimal energy motivates the development of neuromorphic hardware. Such systems emulate neural dynamics through spiking neural networks (SNNs), asynchronous data handling, and adaptive learning mechanisms. Deep learning excels at extracting rich features from massive datasets but suffers from high training costs and scalability concerns. Neuromorphic systems, with their real- time responsiveness and efficiency, can serve as ideal platforms to deploy and potentially train these models at the edge.The fusion of deep learning's representational power with neuromorphic computing's efficiency could pave the way for the next generation of intelligent systems. These hybrid models hold potential for real-time, adaptive learning in resource- constrained environments—enabling smarter edge devices, autonomous systems, and brain-inspired AI. Together, they could overcome existing hardware bottlenecks, offering transformative advancements in AI's reach, performance, and sustainability. Keywords: Deep Learning, Neuromorphic Computing, Artificial Intelligence, Machine Learning, Efficient Computing, Edge Computing.
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Lin, Zhiting, Zhongzhen Tong, Jin Zhang, et al. "A review on SRAM-based computing in-memory: Circuits, functions, and applications." Journal of Semiconductors 43, no. 3 (2022): 031401. http://dx.doi.org/10.1088/1674-4926/43/3/031401.

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Abstract Artificial intelligence (AI) processes data-centric applications with minimal effort. However, it poses new challenges to system design in terms of computational speed and energy efficiency. The traditional von Neumann architecture cannot meet the requirements of heavily data-centric applications due to the separation of computation and storage. The emergence of computing in-memory (CIM) is significant in circumventing the von Neumann bottleneck. A commercialized memory architecture, static random-access memory (SRAM), is fast and robust, consumes less power, and is compatible with state-of-the-art technology. This study investigates the research progress of SRAM-based CIM technology in three levels: circuit, function, and application. It also outlines the problems, challenges, and prospects of SRAM-based CIM macros.
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KIM, Yonghun, Jung-Dae KWON, and Jongwon YOON. "2D Materials-based Neuromorphic Computing Electronic Device." Physics and High Technology 32, no. 11 (2023): 10–16. http://dx.doi.org/10.3938/phit.32.029.

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Nowadays, with the rapid information explosion connected to all devices, there is a huge demand for effectively processing big data. In particular, conventional von Neumann computing system with physically separated processing and memory units face significant problems in dealing with massive unstructured data such as sound, images, and video because of a von Neumann bottleneck. As a key feature of parallel operations, neuromorphic computing systems can analyze massive unstructured data in a time and energy efficient manner. However, critical issues related to reliability and variability of nonlinearity and asymmetric weight update, have been great challenges in the implementation of artificial synaptic device in practical neuromorphic hardware system. Also, hardware systems enabling artificial neural networks in-situ personal data are essential for adaptive wearable neuromorphic edge computing.
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Ou, Qiao-Feng, Bang-Shu Xiong, Lei Yu, Jing Wen, Lei Wang, and Yi Tong. "In-Memory Logic Operations and Neuromorphic Computing in Non-Volatile Random Access Memory." Materials 13, no. 16 (2020): 3532. http://dx.doi.org/10.3390/ma13163532.

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Recent progress in the development of artificial intelligence technologies, aided by deep learning algorithms, has led to an unprecedented revolution in neuromorphic circuits, bringing us ever closer to brain-like computers. However, the vast majority of advanced algorithms still have to run on conventional computers. Thus, their capacities are limited by what is known as the von-Neumann bottleneck, where the central processing unit for data computation and the main memory for data storage are separated. Emerging forms of non-volatile random access memory, such as ferroelectric random access memory, phase-change random access memory, magnetic random access memory, and resistive random access memory, are widely considered to offer the best prospect of circumventing the von-Neumann bottleneck. This is due to their ability to merge storage and computational operations, such as Boolean logic. This paper reviews the most common kinds of non-volatile random access memory and their physical principles, together with their relative pros and cons when compared with conventional CMOS-based circuits (Complementary Metal Oxide Semiconductor). Their potential application to Boolean logic computation is then considered in terms of their working mechanism, circuit design and performance metrics. The paper concludes by envisaging the prospects offered by non-volatile devices for future brain-inspired and neuromorphic computation.
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Lu, Chun Hsien, Chih Sheng Lin, Hung Lin Chao, Jih g. Shen, and Pao Ann Hsiung. "Reconfigurable multi-core architecture - a plausible solution to the von Neumann performance bottleneck." International Journal of Adaptive and Innovative Systems 2, no. 3 (2015): 217. http://dx.doi.org/10.1504/ijais.2015.074399.

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Sheng, Huayi, and Muhammad Shemyal Nisar. "Simulating an Integrated Photonic Image Classifier for Diffractive Neural Networks." Micromachines 15, no. 1 (2023): 50. http://dx.doi.org/10.3390/mi15010050.

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The slowdown of Moore’s law and the existence of the “von Neumann bottleneck” has led to electronic-based computing systems under von Neumann’s architecture being unable to meet the fast-growing demand for artificial intelligence computing. However, all-optical diffractive neural networks provide a possible solution to this challenge. They can outperform conventional silicon-based electronic neural networks due to the significantly higher speed of the propagation of optical signals (≈108 m.s−1) compared to electrical signals (≈105 m.s−1), their parallelism in nature, and their low power consumption. The integrated diffractive deep neural network (ID2NN) uses an on-chip fully passive photonic approach to achieve the functionality of neural networks (matrix–vector operations) and can be fabricated via the CMOS process, which is technologically more amenable to implementing an artificial intelligence processor. In this paper, we present a detailed design framework for the integrated diffractive deep neural network and corresponding silicon-on-insulator integration implementation through Python-based simulations. The performance of our proposed ID2NN was evaluated by solving image classification problems using the MNIST dataset.
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Ringwood, G. A. "Metalogic machines: a retrospective rationale for the Japanese Fifth Generation." Knowledge Engineering Review 3, no. 4 (1988): 303–20. http://dx.doi.org/10.1017/s0269888900004604.

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AbstractThe oft quoted inadequacy of von Neumann architectures for AI applications has regularly been used to justify the design of special purpose parallel machines. In particular, the von Neumann computational model has been criticized as being unsuitable for parallelism because of the memory access bottleneck. For the design of a new machine both top-down and bottom-up methodologies have drawbacks. The middle-out strategy, working both up and down from an intrinsically concurrent high-level programming language as a means of both representing and processing knowledge provides an attractive way of providing a symbiosis between software and hardware. The longest established and most well-founded symbolic method for the representation and manipulation of knowledge is logic. A notable result of the last decade, work on mechanical theorem proving was that a subset of predicate logic, Horn Clauses, can form the foundation of a computational model. The execution model of Prolog, the first popular language based on Horn Clauses, was designed for efficient evaluation on von Neumann architectures. An alternative computational model, more suitable for expressing reactive systems but retaining Prolog's affinity for metaprogramming, has given rise to a new class of languages, concurrent logic languages. One among many of these languages, FGHC (flat Guarded Horn Clauses), was developed by the Japanese as the kernel of their Fifth Generation initiative. A background familiarity with Prolog would be helpful in understanding this article.
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Wang, Yi Da. "Selection of Switching Layer Materials for Memristive Devices: from Traditional Oxide to 2D Materials." Materials Science Forum 1027 (April 2021): 107–14. http://dx.doi.org/10.4028/www.scientific.net/msf.1027.107.

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Redox-based resistive switching devices (ReRAM) provide new hardware concepts which make it possible to break the von Neumann bottleneck and build a new computing system in the information. However, the materials for switching layers are various and mechanisms are quite different, these will block the further exploration for practical applications. This review tends to demonstrate different kinds of memristors fabricated with various materials, such as oxide, nitride and 2D materials. The electrical properties of those based on different materials are compared and the advantages of each are listed. It would give a guidance to the selection of materials of memristors.
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Niu, Xuezhong, Bobo Tian, Qiuxiang Zhu, Brahim Dkhil, and Chungang Duan. "Ferroelectric polymers for neuromorphic computing." Applied Physics Reviews 9, no. 2 (2022): 021309. http://dx.doi.org/10.1063/5.0073085.

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The last few decades have witnessed the rapid development of electronic computers relying on von Neumann architecture. However, due to the spatial separation of the memory unit from the computing processor, continuous data movements between them result in intensive time and energy consumptions, which unfortunately hinder the further development of modern computers. Inspired by biological brain, the in situ computing of memristor architectures, which has long been considered to hold unprecedented potential to solve the von Neumann bottleneck, provides an alternative network paradigm for the next-generation electronics. Among the materials for designing memristors, i.e., nonvolatile memories with multistate tunable resistances, ferroelectric polymers have drawn much research interest due to intrinsic analog switching property and excellent flexibility. In this review, recent advances on artificial synapses based on solution-processed ferroelectric polymers are discussed. The relationship between materials' properties, structural design, switching mechanisms, and systematic applications is revealed. We first introduce the commonly used ferroelectric polymers. Afterward, device structures and the switching mechanisms underlying ferroelectric synapse are discussed. The current applications of organic ferroelectric synapses in advanced neuromorphic systems are also summarized. Eventually, the remaining challenges and some strategies to eliminate non-ideality of synaptic devices are analyzed.
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Blair, Enrique, and Craig Lent. "Clock Topologies for Molecular Quantum-Dot Cellular Automata." Journal of Low Power Electronics and Applications 8, no. 3 (2018): 31. http://dx.doi.org/10.3390/jlpea8030031.

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Quantum-dot cellular automata (QCA) is a low-power, non-von-Neumann, general-purpose paradigm for classical computing using transistor-free logic. Here, classical bits are encoded on the charge configuration of individual computing primitives known as “cells.” A cell is a system of quantum dots with a few mobile charges. Device switching occurs through quantum mechanical inter-dot charge tunneling, and devices are interconnected via the electrostatic field. QCA devices are implemented using arrays of QCA cells. A molecular implementation of QCA may support THz-scale clocking or better at room temperature. Molecular QCA may be clocked using an applied electric field, known as a clocking field. A time-varying clocking field may be established using an array of conductors. The clocking field determines the flow of data and calculations. Various arrangements of clocking conductors are laid out, and the resulting electric field is simulated. It is shown that that control of molecular QCA can enable feedback loops, memories, planar circuit crossings, and versatile circuit grids that support feedback and memory, as well as data flow in any of the ordinal grid directions. Logic, interconnect and memory now become indistinguishable, and the von Neumann bottleneck is avoided.
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Dissertations / Theses on the topic "Von Neumann bottleneck"

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Karasenko, Vitali [Verfasser], and Johannes [Akademischer Betreuer] Schemmel. "Von Neumann bottlenecks in non-von Neumann computing architectures / Vitali Karasenko ; Betreuer: Johannes Schemmel." Heidelberg : Universitätsbibliothek Heidelberg, 2020. http://d-nb.info/1215187505/34.

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Book chapters on the topic "Von Neumann bottleneck"

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Talati, Nishil, Rotem Ben-Hur, Nimrod Wald, Ameer Haj-Ali, John Reuben, and Shahar Kvatinsky. "mMPU—A Real Processing-in-Memory Architecture to Combat the von Neumann Bottleneck." In Applications of Emerging Memory Technology. Springer Singapore, 2019. http://dx.doi.org/10.1007/978-981-13-8379-3_8.

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Carboni, Roberto. "Characterization and Modeling of Spin-Transfer Torque (STT) Magnetic Memory for Computing Applications." In Special Topics in Information Technology. Springer International Publishing, 2021. http://dx.doi.org/10.1007/978-3-030-62476-7_5.

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AbstractWith the ubiquitous diffusion of mobile computing and Internet of Things (IoT), the amount of data exchanged and processed over the internet is increasing every day, demanding secure data communication/storage and new computing primitives. Although computing systems based on microelectronics steadily improved over the past 50 years thanks to the aggressive technological scaling, their improvement is now hindered by excessive power consumption and inherent performance limitation associated to the conventional computer architecture (von Neumann bottleneck). In this scenario, emerging memory technologies are gaining interest thanks to their non-volatility and low power/fast operation. In this chapter, experimental characterization and modeling of spin-transfer torque magnetic memory (STT-MRAM) are presented, with particular focus on cycling endurance and switching variability, which both present a challenge towards STT-based memory applications. Then, the switching variability in STT-MRAM is exploited for hardware security and computing primitives, such as true-random number generator (TRNG) and stochastic spiking neuron for neuromorphic and stochastic computing.
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Tate, Naoya. "Quantum-Dot-Based Photonic Reservoir Computing." In Photonic Neural Networks with Spatiotemporal Dynamics. Springer Nature Singapore, 2023. http://dx.doi.org/10.1007/978-981-99-5072-0_4.

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AbstractReservoir computing is a novel computational framework based on the characteristic behavior of recurrent neural networks. In particular, a recurrent neural network for reservoir computing is defined as a reservoir, which is implemented as a fixed and nonlinear system. Recently, to overcome the limitation of data throughput between processors and storage devices in conventional computer systems during processing, known as the Von Neumann bottleneck, physical implementations of reservoirs have been actively investigated in various research fields. The author’s group has been currently studying a quantum dot reservoir, which consists of coupled structures of randomly dispersed quantum dots, as a physical reservoir. The quantum dot reservoir is driven by sequential signal inputs using radiation with laser pulses, and the characteristic dynamics of the excited energy in the network are exhibited with the corresponding spatiotemporal fluorescence outputs. We have presented the fundamental physics of a quantum dot reservoir. Subsequently, experimental methods have been introduced to prepare a practical quantum dot reservoir. Next, we have presented the experimental input/output properties of our quantum dot reservoir. Here, we experimentally focused on the relaxation of fluorescence outputs, which indicates the characteristics of optical energy dynamics in the reservoir, and qualitatively discussed the usability of quantum dot reservoirs based on their properties. Finally, we have presented experimental reservoir computing based on spatiotemporal fluorescence outputs from a quantum dot reservoir. We consider that the achievements of quantum dot reservoirs can be effectively utilized for advanced reservoir computing.
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Khanna, Vinod Kumar. "Central processing unit, and the von Neumann bottleneck." In AI-Processor Electronics. IOP Publishing, 2025. https://doi.org/10.1088/978-0-7503-6259-7ch3.

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Jin, Hui, Sijia Liu, Xiaoyang Xu, et al. "Boolean Logic Operations Based on Four-Terminal Magnetic Tunnel Junction for Computing in Memory." In Advances in Transdisciplinary Engineering. IOS Press, 2024. http://dx.doi.org/10.3233/atde240736.

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The Von Neumann architecture urgently needs to overcome the bottleneck of the storage wall issue, which can be effectively addressed by the emerging Magnetic Random Access Memory (MRAM) due to its high speed, non-volatility, low power consumption, high integration, durability, and compatibility with CMOS. This makes magnetic storage an optimal solution for overcoming the bottleneck of the Von Neumann architecture. However, pure magnetic storage devices for storage and computation are not yet available. Therefore, the optimization of novel MRAM structures has become a new choice for future computing in memory. This paper proposes a four-terminal magnetic tunnel junction (MTJ) device structure basic principle of Spin-Orbit Torque (SOT), which has multi-bit and capable of performing logical operations such as AND, OR, and XOR with ultra-high computational efficiency. The proposed device structure is verified to perform Boolean logic operations in one cycle by Cadence simulation, which providing a new method for in-memory computing in our solution.
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Chen, Long. "Mxenes for Wearable Multifunctional Sensing and Artificial Intelligence Devices." In MXenes - Cutting-Edge Materials for Next-Generation Applications [Working Title]. IntechOpen, 2025. https://doi.org/10.5772/intechopen.1009614.

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The exponential growth of artificial intelligence (AI) has led to an escalating demand for energy-efficient, data-intensive computing solutions. Conventional von Neumann architectures, constrained by inherent memory-processor bottlenecks, struggle to meet these requirements. Neuromorphic devices enable energy-efficient, scalable, and high-speed neuromorphic computing, potentially addressing the von Neumann bottleneck and the limits of Moore’s Law. Two-dimensional MXene materials, with their excellent mechanical and electrical properties, have become a transformative platform for developing neuromorphic devices, providing unparalleled advantages in sensing, nonvolatile memory, and bio-inspired computation. This chapter systematically summarizes recent advances in MXene-based flexible neuromorphic memristor devices. First, we delineate materials engineering strategies for synthesizing MXene thin films with tailored electronic and mechanical properties. Next, we classify MXene-derived neuromorphic materials and elucidate their switching mechanisms, including ion migration and charge trapping. A critical analysis of MXene-enabled devices highlights breakthroughs in-memory, artificial synapses, neuromorphic circuits, and multimodal in-sensor computing. Finally, we discuss persistent challenges in stability, scalability, and interfacial engineering, while projecting future directions for MXene-integrated sensing-memory-processing systems. This chapter provides a potential pathway for leveraging MXenes to transcend the limitations of conventional computing paradigms.
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Sterling Thomas, Brodowicz Maciej, Kogler Danny, and Anderson Matthew. "Asymptotic Computing – Undoing the Damage." In Advances in Parallel Computing. IOS Press, 2017. https://doi.org/10.3233/978-1-61499-816-7-55.

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While the very far future well beyond exaflops computing may encompass such paradigm shifts as quantum computing or neuromorphic computing, a critical window of change exists within the domain of semiconductor digital logic technology but beyond conventional practices of architecture, system software, and programming. As key parameters such as Dennard scaling, nano-scale component densities, clock rates, pin I/O, and voltage represent asymptotic operational regimes, one major area of untapped opportunity is computer architecture which has been severely limited by conventional practices of organization and control semantics. Mainstream computer architecture in HPC has been inhibited in innovation by the original von Neumann architecture of seven decades ago. Although notably diverse in form of parallelism exploited, six major epochs of computer architecture through to the present are all von Neumann derivatives. At their core is the use of single instruction issue and the prioritization of Floating Point ALU (FPU) utilization. However, in the modern age, FPUs consume only a small part of die real estate while the plethora of mechanisms to achieve maximum floating point efficiency take up the majority of the chip. The von Neumann bottleneck, the separation of memory and processor, is also retained. A revolution in computer architecture design is possible by undoing the damage of the von Neumann heritage and emphasizing the key challenges of data movement latency and bandwidth which are the true precious resources along with operation/instruction issue control. This paper discusses key tradeoffs that should drive computer architecture in what might be called the “Neo-Digital Age”.
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Pereira, M. E., E. Carlos, E. Fortunato, R. Martins, P. Barquinha, and A. Kiazadeh. "Amorphous Oxide Semiconductor Memristors: Brain-inspired Computation." In Advanced Memory Technology. Royal Society of Chemistry, 2023. http://dx.doi.org/10.1039/bk9781839169946-00431.

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Memristors in crossbar arrays can accomplish computing operations while storing data at the same physical location, enabling a cost-efficient latency-free solution to the von Neumann bottleneck. Amorphous oxide semiconductor (AOS)-based memristors can be engineered to perform filamentary- and/or interface-type resistive switching. Their superior characteristics such as high flexibility compatible with low-temperature and easy manufacturing evidence their potential for embedded flexible neuromorphic technologies. In this chapter, the state-of-the-art on AOS-based resistive switching devices is analysed, along with their suitability for specific neuromorphic applications such as in-memory computation and deep and spiking neural networks. Currently, crosstalk is the main obstacle to large-scale crossbar integration and, therefore, the proposed main approaches to overcome this obstacle are discussed. Here, given the high level of behaviour control offered by AOS-based memristors, self-rectifying characteristics or optoelectronic features can be established. Moreover, the compatibility of AOS films with both memristors and thin-film transistors provides the necessary means for active crossbars to be developed in a cost-efficient, simple and higher-interconnectivity manner.
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Wang, Dingchen, Shuhui Shi, Yi Zhang, et al. "Stochastic Emerging Resistive Memories for Unconventional Computing." In Advanced Memory Technology. Royal Society of Chemistry, 2023. http://dx.doi.org/10.1039/bk9781839169946-00240.

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Stochasticity plays a critical role in biological neural systems, which also inspires various statistical learning approaches. However, conventional digital electronics on silicon-based transistors practice deterministic Boolean logic, making it less favorable for solving problems involving stochasticity. This is further intensified by the von Neumann bottleneck of digital systems and the slowdowns of Moore’s law. Emerging resistive memory, such as those based on redox reactions and phase transitions, features intrinsic stochasticity due to their underlying physical mechanisms. In addition, such devices integrate storage and computing functions, like that of the brain. They are also endowed with superior scalability and stack-ability due to their simple and low-cost structures. In this chapter, we will survey the broad spectrum of unconventional computing applications of stochastic emerging resistive memories (RMs) from their physics origin to system-level applications. Firstly, we review the mainstream resistive memories and the origin of stochasticity in both programming and charge transport. Secondly, we explore how the stochasticity of RMs benefits bio-inspired computing, including artificial neural networks, spiking neural networks, and reservoir computing. Thirdly, we discuss how stochasticity benefits energy-based networks, such as Hopfield networks, in solving optimization problems. Fourthly, we survey the applications to cybersecurity, including how the cycle-to-cycle (C2C) variation is leveraged for random number generation and how the device-to-device (D2D) variation contributes to hardware identities. Last but not least, we introduce RM-based probability bit generation and bit stream decorrelation for probabilistic computing, with applications to Bayesian neural networks and Markov chain Monte Carlo algorithms.
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Conference papers on the topic "Von Neumann bottleneck"

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Schwartz, Russell L. T., Hangbo Yang, Nicola Peserico, and Volker J. Sorger. "The Von Neumann Bottleneck in Photonic Tensor Core Systems." In 2024 IEEE Photonics Society Summer Topicals Meeting Series (SUM). IEEE, 2024. http://dx.doi.org/10.1109/sum60964.2024.10614519.

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Dickinson, Alex. "An Optical Respite from the Von Neumann Bottleneck." In Optical Computing. Optica Publishing Group, 1991. http://dx.doi.org/10.1364/optcomp.1991.tuc4.

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The high end of microprocessor performance is currently dominated by Reduced Instruction Set Computer (RISC) architectures. These machines execute one or more instructions per clock cycle. A processor such as the i8601 [1] runs with a 40MHz clock - requiring that on average an instruction must be delivered to the CPU every 25nS. With DRAM access times currently at around 100nS, timely instruction delivery has become a critical constraint on processor speed.
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Edwards, Jonathan, and Simon O'Keefe. "Eager recirculating memory to alleviate the von Neumann Bottleneck." In 2016 IEEE Symposium Series on Computational Intelligence (SSCI). IEEE, 2016. http://dx.doi.org/10.1109/ssci.2016.7850155.

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Kanamoto, Toshiki, Masami Fukushima, Koichi Kitagishi, et al. "A Single-Stage RISC-V Processor to Mitigate the Von Neumann Bottleneck." In 2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS). IEEE, 2019. http://dx.doi.org/10.1109/mwscas.2019.8884919.

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Lu, Chun-Hsien, Chih-Sheng Lin, Hung-Lin Chao, Jih-Sheng Shen, and Pao-Ann Hsiung. "Reconfigurable Multi-core Architecture -- A Plausible Solution to the Von Neumann Performance Bottleneck." In 2013 IEEE 7th International Symposium on Embedded Multicore Socs (MCSoC). IEEE, 2013. http://dx.doi.org/10.1109/mcsoc.2013.32.

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