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1
Maamar, Ali Hussein. "A 32-bit self-checking RISC processor using Dong's Code". Thesis, University of Newcastle Upon Tyne, 1999. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.285335.
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2
Jönsson, Patricia. "Evaluation in which context a 32-bit, rather than an 8-bit processor may be appropriate to use, based on power consumption". Thesis, Malmö högskola, Fakulteten för teknik och samhälle (TS), 2017. http://urn.kb.se/resolve?urn=urn:nbn:se:mau:diva-20846.
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Uttrycket Internet of Things växer sig större och större och världen är på väg att ha 50miljarder uppkopplade enheter till 2020. IoT-enheter är beroende av att ha en låg effektförbrukningoch därför är en processor med låg effektförbrukning viktigt att ha. Denna studieutför tester på två strömsnåla processorer för att komma fram till vilken processor somär mest lämplig till vilken IoT-produkt. Testningen utgick från tre applikationer som i sintur baseras på verkliga IoT-situationer. De tre applikationerna har olika intesitetsnivåer. Iden första applikationen arbetar processorerna inte särskilt hårt, I den andra applikationenfår processorena arbeta mer och i den tredje applikationen får processorerna jobba somhårdast. Effektförbrukningen mäts med hjälp av Atmel Power debugger. Resultatet visaratt IoT-enheter som inte är särskilt aktiva har en lägre effektförbrukning med en 8-bitarsprocessor men en IoT-enhet som är mer aktiv har lägre effektförbrukning med Cortex-M0+baserad 32-bitars processor.The term Internet of Things grows bigger and bigger and the world is about to have 50 billionconnected devices. IoT devices are dependent on low power consumption and thereforea low power processor is important to have. This study performs tests on two power-savingprocessors to determine which processor is most suitable for an IoT product. The test wasbased on three applications, which in turn are based on actual IoT situations. The threeapplications have different levels of intency. In the first application, the processors do notwork very hard. In the second application, the processors get more work and in the thirdapplication, the processors get the hardest work. Power consumption is measured usingAtmel Power debugger The result shows that low-active IoT devices have a lower powerconsumption with an 8-bit processor, but an IoT device that is more active has lower powerconsumption with a Cortex-M0 + based 32-bit processor.
3
Fang, Gloria(Gloria Yu Liang). "Instruction-level power consumption simulator for modeling simple timing and power side channels in a 32-bit RISC-V micro-processor". Thesis, Massachusetts Institute of Technology, 2021. https://hdl.handle.net/1721.1/130686.
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Thesis: M. Eng., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, February, 2021Cataloged from the official PDF of thesis.
Includes bibliographical references (pages 139-140).
We create a Python based RISC-V simulator that is capable of simulating any assembly code written in RISC-V, and even perform simple power analysis of RISC-V designs. The power consumption of non-privileged RISC-V RV32IM instructions are measured experimentally, forming the basis for our simulator. These instructions include memory loads and stores, PC jumps and branches, as well as arithmetic instructions with register values. The object-oriented simulator also supports stepping and debugging. In the context of designing software for hardware use, the simulator helps assess vulnerability to side channel attacks by accepting input power consumption values. The power consumption graph of any disassembled RISC-V code can be obtained if the power consumption of each instruction is given as an input; then, from the output power consumption waveforms, we can assess how vulnerable a system is to side channel attacks. Because the power values can be customized based on what's experimentally measured, this means that our simulator can be applied to any disassembled code and to any system as long as the input power consumption of each instruction is supplied. Finally, we demonstrate an example application of the simulator on a pseudorandom function for simple side channel power analysis.
by Gloria (Yu Liang) Fang.
M. Eng.
M.Eng. Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science
4
Su, Chien-Chang y 蘇健彰. "Integrated Software Development Environment for a 32-bit / 16-bit Processor Family". Thesis, 2007. http://ndltd.ncl.edu.tw/handle/3gpzv5.
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碩士國立中山大學
資訊工程學系研究所
95
To the general purpose microprocessors, we often need to change microprocessors’ hardware architecture because of customized purpose. But already existing application program is incompatible to the new hardware architecture, and increase the product’s development period. In this thesis, we discuss the modification of two kinds of hardware architecture, include new instruction set extension and change the size of datapath to deal with specific application. To the former, our laboratory develop a 32-bit microprocessor SYS32-TM, increase MME instruction set to deal with multimedia application. The latter, based on Thumb instruction set , we develop 16-bit microprocessor SYS16-TM, we modify its’ datapath from 32-bit to 16-bit, we will show how to let already existing application program can execute on the new hardware architecture. In SYS32-TM, we use the way of inline assembly to embedded MME instruction set in C source code, we have to modify the assembler, define and parse the MME instruction set, so the assembler can recognize it. In SYS16-TM, we have sign extension and address offset problems, we have to modify the compiler backend’s machine description to solve the sign extension and address offset instruction set behavior, and modify the library. To build SYS16-TM software environment, we have to set C Run Time Environment in Thumb mode, not support exchange between ARM mode and Thumb mode, and write the correct linker script, to set the program start address in 0x0000, to solve ARM’s initial program start address in 0x8000. As a result, In SYS32-TM, we use assembler to identify the MME instruction set can embedded in existing C source code. In SYS16-TM, we execute the testbench include sorts, Hanoi, Fibonacci number etc, and use simulator to verify its’ correctness.
5
Darwish, Mohammad Mostafa. "Formal verification of a 32-bit pipelined RISC processor". Thesis, 1994. http://hdl.handle.net/2429/5260.
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Designing a microprocessor is a significant undertaking. Modern RISC processors are
no exception. Although RISC architectures originally were intended to be simpler than
CISC processors, modern RISC processors are often very complex, partially due to the
prominent use of pipelining. As a result, verifying the correctness of a RISC design is an
extremely difficult task. Thus, it has become of great importance to find more efficient
design verification techniques than traditional simulation. The objective of this thesis is
to show that symbolic trajectory evaluation is such a technique.
For demonstration purposes, we designed and implemented a 32-bit pipelined RISC
processor, called Oryx. It is a fairly generic first-generation RISC processor with a fivestage
pipeline and is similar to the MIPS-X and DLX processors. The Oryx processor
is designed down to a detailed gate-level and is described in VHDL. Altogether, the
processor consists of approximately 30,000 gates.
We also developed an abstract, non-pipelined, specification of the processor. This
specification is precise and is intended for a programmer. We made a special effort not
to over-specify the processor, so that a family of processors, ranging in complexity and
speed, could theoretically be implemented all satisfying the same specification.
We finally demonstrated how to use an implementation mapping and the Voss veri
fication system to verify important properties of the processor. For example, we verified
that in every sequence of valid instructions, the ALU instructions are implemented cor
rectly. This included both the actual operation performed as well as the control for
fetching the operands and storing the result back into the register file. Carrying out this
verification task required less than 30 minutes on an IBM RS6000 based workstation.
6
Li, Wen-jie y 李文傑. "A Scalable RSA Cryptographic Processor with 32-Bit Modular Multiplier". Thesis, 2006. http://ndltd.ncl.edu.tw/handle/26789610187671920567.
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碩士國立高雄大學
電機工程學系碩士班
94
With the popularity of the portable electronic devices, the chip area and power consumption must be reduced, and because of this, we propose a scalable RSA cryptosystem chip, which is implemented with a 32-bit core. Our design provides the trade-off between security and computation time. If the security is more important, we can choose longer key to get higher security. Otherwise, the shorter key could be chosen to reduce the computation time. To realize the chip of this design, we used Cadence, Synopsys and TSMC 0.35um cell library to simulate and implement. The RSA core takes 2.55M clocks to finish a 512-bit modular exponentiation in average and the critical path delay is only 3.2 ns. The chip area is 1.81mm x 1.81mm. Since a 32-bit core is adopted, our chip has smaller area.
7
XIE, REN-FA y 謝仁發. "A 32-bit hybrid floating-point binary and logarithmic number system processor". Thesis, 1990. http://ndltd.ncl.edu.tw/handle/10886867769518457164.
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Chen, Chien-Chih y 陳建志. "The Linux Porting and Integration Verification of An Academic 32-bit Processor". Thesis, 2012. http://ndltd.ncl.edu.tw/handle/32566192674843841485.
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碩士國立中山大學
資訊工程學系研究所
101
For improving the performance and application of microprocessor, it is necessary to integrate pipelined core, exception control unit, cache unit and memory management unit (MMU). The operating system is an effective way for microprocessor integration verification. However, it is not a feasible debugging methodology to detect the exact design bug while operating system booting crash. We found the main execution features of operating system are the data transfer and exception handling. We propose an integration verification methodology based on these execution features. The methodology is to verify concurrent cache transfer operation, consecutive cache transfer operation, external interrupt exception handling, page fault exception handling and multiple interrupt exception handling for microprocessor integration. We utilize ARM7-Like developed by our laboratory to do the experiment. It is effective to detect the design bugs in RTL simulation by the software-based verification methodology proposed by us. The modified ARM7-Like microprocessor is able to successfully boot Linux kernel and execute user applications in FPGA.
9
Peng, Yi Xiong y 彭義雄. "ASIC Design and Implementation of 32-Bit LNS Addition and Subtraction Processor". Thesis, 1994. http://ndltd.ncl.edu.tw/handle/17662755757560652760.
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Hsin, Wei-Kuo y 辛威虢. "Efficient MP3 Decoder System using a 32-bit Low-Power Embedded Processor Core". Thesis, 2009. http://ndltd.ncl.edu.tw/handle/61855656677322982581.
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碩士國立交通大學
電子工程系所
97
This thesis presents the research result of an efficient MP3 decoder system using a 32-bit low-power embedded processor core, named ACARM9 (ACademic ARM9). The ISA (Instruction Set Architecture) of ACARM9 adopts the ARM V5E architecture but owns more efficient multiplication instructions. Hence the ADS (ARM Develop Suite) can be directly used. ADS can first be used to compile the code of high level programming language (C, C++) written by users to the assembly code, and then can assemble the assembly code to the low level machine code for ACARM9 use. It indicates the high usability of ACARM9. Moreover, this thesis presents a methodology for platform-based design. The proposed processor is mapped onto the FPGA and integrated within the ARM926EJ-S Versatile Development Board. Then an MP3 decoder system, which is capable of providing high decoding rate and playing audio synchronously, is successfully implemented using the proposed platform.
11
Hsu, Je-Ling y 許哲霖. "Ultra Low-Power and High-Performance 32-Bit Embedded Processor with JPEG Decoder System". Thesis, 2007. http://ndltd.ncl.edu.tw/handle/33455761081632868123.
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碩士國立交通大學
電子工程系所
96
This thesis presents the research result of an ultra low-power and high-performance 32-bit embedded processor with JPEG decoder system. This processor is named ACARM7 (ACademic ARM7). The ISA (Instruction Set Architecture) of ACARM7 adopts the ARM V4 architecture. Hence the ADS (ARM Develop Suite) can be directly used. ADS can first be used to compile the high level programming language (C, C++) written by users to the assembly language, and then can assemble the assemble language to the low level machine code for ACARM7 use. It indicates the high usability of ACARM7. Compared with ARM7TDMI, the power consumed by the proposed processor is lower; the gate-count of the proposed one is less; and the performance is better. Meanwhile, this thesis also provides a thorough and rigorous verification flow which assures both the correctness of functional behavior of the proposed processor design after more than two billion simulation cycle comparisons and the synthesis correctness of synthesized gate-level netlist circuit. Moreover, the proposed processor is mapped onto the FPGA and integrated within the ARM926EJ-S Versatile Development Board to implement a JPEG decoder system. Based on the experiment result obtained by this research, the higher performance, the smaller area, and the lower power are all the advantages of the proposed processor compared with ARM7TDMI. The thesis also proposes a thorough and rigorous processor verification flow. Moreover, the high applicability of the proposed processor is demonstrated by mapping it into an FPGA for implementing a JPEG decoder system.
12
Liu, Hwang Lin y 劉皇麟. "An Implementation and Layout of a 32-Bit Arithmetic Co- processor (with Improvement of Accuracy for Logarithmic Conversion)". Thesis, 1994. http://ndltd.ncl.edu.tw/handle/79968939307844242470.
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碩士逢甲大學
資訊工程研究所
82
Logarithms have long been used as a tool in mathematics to simplify the process, e.g., they reduce multiplication and division problems to addition and subtraction. In this thesis, we have worked out for the VLSI layout of the Three Partition with Hybrid ROMs strategy. The CAD package MAGIC was used to implement and simulate the VLSI layout. Now we have passed the examination of the Chip Implementation Center, and produced the chips. Finally, we initialed a new method for the logarithmic conversion which may require larger ROM size, but increase the accuracy significantly. We believe that this scheme will be useful when the technique of the IC design process is improved.
13
Liu, Huang Lin y 劉皇麟. "An implementation and layout of a 32-bit arithmetic co-processor (with improvement of accuracy for logarithmic conversion)". Thesis, 1994. http://ndltd.ncl.edu.tw/handle/02453557392387793738.
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Chen, Yi-Hung Edward y 陳奕宏. "Improvement and Discussion of MFCC Algorithm on 32-bit Fixed-point Processors". Thesis, 2006. http://ndltd.ncl.edu.tw/handle/52339443995174628395.
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碩士國立清華大學
資訊系統與應用研究所
94
In this thesis, we investigate the possibility of porting the computation of floating-point MFCCs to fixed-point ones. In particular, we focus on the platform of 32-bit fixed-point processors. We have closely checked the scaling factors during each stage of the computation of MFCC by using a data-driven approach. These scaling factors are carefully chosen such that the highest precision is achieved with low probabilities of overflow. Moreover, we have proposed a binary-search-based table lookup such that the required table size is reduced. In summary, the proposed methodology can greatly reduce the memory requirement without degrading recognition rates.
15
Huang, Wu-Xian y 黃武顯. "A Study on Improving Spoken Mandarin Assessment over 32-bit Fixed-point processors". Thesis, 2007. http://ndltd.ncl.edu.tw/handle/64390866548487441755.
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碩士國立清華大學
資訊工程學系
95
This thesis explores the possibility of improving the performance of our Mandarin speech assessment systems on 32-bit fix-point platform. For improving efficiency, we have proposed several methods for reduce computation, such that the response time of the system can be as short as possible without degrading its performance. For improving effectiveness, we have also proposed four score-correction rules that can be used to give a more consistent scores of speech assessment. We have implemented these methods and rules on a PMP (personal media player) based Mandarin speech assessment system with satisfactory performance both in efficiency and effectiveness.