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Artículos de revistas

Literatura académica sobre el tema "Checking circuit"

Autor: Grafiati

Publicado: 4 de junio de 2021

Última modificación: 14 de febrero de 2022

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Artículos de revistas sobre el tema "Checking circuit"

1

Gavrilenkov, Sergey I., Elizaveta O. Petrenko, and Evgeny V. Arbuzov. "A Digital Device for Automatic Checking of Homework Assignments in the Digital Circuits Course." ITM Web of Conferences 35 (2020): 04009. http://dx.doi.org/10.1051/itmconf/20203504009.

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This paper considers a digital device for automatic checking of homework assignments in the digital circuits course. The assignment is to make a digital circuit corresponding to a given logical expression; the circuit is comprised of elementary logic gates. The process of manual testing the built circuit is very labor-intensive because checking a circuit with N inputs variables requires checking the correctness of the output variable for 2N cases. We propose automating this pro-cess with a special digital device. The device is comprised of a microcontroller connected to the circuit tested. The

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2

Gu, Yu Wan, Guo Dong Shi, Shi Yan Xie, and Yu Qiang Sun. "Sequential Circuit Equivalence Checking Method Based on Minimizing Automation." Advanced Materials Research 204-210 (February 2011): 251–54. http://dx.doi.org/10.4028/www.scientific.net/amr.204-210.251.

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A parallel checking method is proposed in the paper, in order to improve the speed of sequential circuit checking. The graph form of sequential circuits is isomorphic to finite state machine; a parallel sequential circuit equivalence checking method is designed using parallel minimization method of finite state machine. At last, the effectiveness and feasibility of the method is proved with an instance.

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3

Busaba, Fadi, and Parag K. Lala. "Techniques for Self-Checking Combinational Logic Synthesis." VLSI Design 2, no. 3 (1994): 209–21. http://dx.doi.org/10.1155/1994/29238.

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This paper presents techniques for designing arbitrary combinational circuits so that any single stuck-at fault will result in either single bit error or unidirectional multibit error at the output. If the outputs are encoded using Berger code or m-out-of-n code, then the proposed technique will enable on-line detection of faults in the circuit. An algorithm for indicating whether a certain fault at an input will create bidirectional error at the output is presented. An input encoding algorithm and an output encoding algorithm that ensure that every fault will either produce single bit error o

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4

Fan, Quan Run, Feng Pan, and Xin Dong Duan. "Using Logic Synthesis and Circuit Reasoning for Equivalence Checking." Advanced Materials Research 201-203 (February 2011): 836–40. http://dx.doi.org/10.4028/www.scientific.net/amr.201-203.836.

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The existing SAT based algorithms combines two circuits into a miter, and then convert the miter into a CNF formula. After that, a SAT solver is invoked to check the satisfiability of the CNF formula. However, when a miter is converted into CNF formula, the structure information of the circuit is lost. Therefore,we are motivated to solve the problem of miter satisfiability using circuit reasoning. We use logic synthesis first to simplify the circuit, and then use a backtracking method to check the satisfiability of the miter. The preliminary experimental result sindicate that our approach is e

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5

Morosow, A., V. V. Saposhnikov, Vl V. Saposhnikov, and M. Goessel. "Self-Checking Combinational Circuits with Unidirectionally Independent Outputs." VLSI Design 5, no. 4 (1998): 333–45. http://dx.doi.org/10.1155/1998/20389.

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In this paper we propose a structure dependent method for the systematic design of a self-checking circuit which is well adapted to the fault model of single gate faults and which can be used in test mode.According to the fault model considered, maximal groups of independent and unidirectionally independent outputs of an arbitrarily given combinational circuit are determined. A parity bit is added to every group of independent outputs. A few additional outputs are added to every group of unidirectionally independent outputs. In the error free case, these groups of unidirectional independent ou

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6

Khan, Wilayat, Farrukh Aslam Khan, Abdelouahid Derhab, and Adi Alhudhaif. "CoCEC: An Automatic Combinational Circuit Equivalence Checker Based on the Interactive Theorem Prover." Complexity 2021 (May 25, 2021): 1–12. http://dx.doi.org/10.1155/2021/5525539.

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Checking the equivalence of two Boolean functions, or combinational circuits modeled as Boolean functions, is often desired when reliable and correct hardware components are required. The most common approaches to equivalence checking are based on simulation and model checking, which are constrained due to the popular memory and state explosion problems. Furthermore, such tools are often not user-friendly, thereby making it tedious to check the equivalence of large formulas or circuits. An alternative is to use mathematical tools, called interactive theorem provers, to prove the equivalence of

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7

Burch, J. R., E. M. Clarke, D. E. Long, K. L. McMillan, and D. L. Dill. "Symbolic model checking for sequential circuit verification." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 13, no. 4 (1994): 401–24. http://dx.doi.org/10.1109/43.275352.

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8

Busaba, Fadi, Parag K. Lala, and Alvernon Walker. "On Self-Checking Design of CMOS Circuits for Multiple Faults." VLSI Design 7, no. 2 (1998): 151–61. http://dx.doi.org/10.1155/1998/37237.

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A technique for designing totally self-checking (TSC) FCMOS (Fully Complementary MOS) designs for multiple faults is presented in this paper. The existing techniques for self checking design consider only single faults, and suffer from high silicon area overhead. The multiple faults considered in this paper are multiple breaks, multiple transistors stuck-offs and multiple transistors stuck-ons. Starting from FCMOS design, small modifications (addition of two-weak transistors) make the original circuit totally self-checking. Experiemntal results show the overhead, delay and power consumption fo

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9

Kini, MVittal, MarkS Myers, and Sunil Shenoy. "4821271 Methods and circuits for checking integrated circuit chips having programmable outputs." Microelectronics Reliability 29, no. 6 (1989): iii—iv. http://dx.doi.org/10.1016/0026-2714(89)90153-4.

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10

Pan, Zhong Liang, and Ling Chen. "A New Verification Method of Digital Circuits Based on Cone-Oriented Partitioning and Decision Diagrams." Applied Mechanics and Materials 29-32 (August 2010): 1040–45. http://dx.doi.org/10.4028/www.scientific.net/amm.29-32.1040.

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The formal verification is able to check whether the implementation of a circuit design is functionally equivalent to an earlier version described at the same level of abstraction, it can show the correctness of a circuit design. A new circuit verification method based on cone-oriented circuit partitioning and decision diagrams is presented in this paper. First of all, the structure level of every signal line in a circuit is computed. Secondly, the circuit is partitioned into a lot of cone structures. The multiple-valued decision diagram corresponding to every cone structure is generated. The

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