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Artículos de revistas sobre el tema "D latch"

Autor: Grafiati

Publicado: 4 de junio de 2021

Última modificación: 10 de febrero de 2022

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1

Hatefinasab, Seyedehsomayeh, Noel Rodriguez, Antonio García y Encarnacion Castillo. "Low-Cost Soft Error Robust Hardened D-Latch for CMOS Technology Circuit". Electronics 10, n.º 11 (25 de mayo de 2021): 1256. http://dx.doi.org/10.3390/electronics10111256.

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In this paper, a Soft Error Hardened D-latch with improved performance is proposed, also featuring Single Event Upset (SEU) and Single Event Transient (SET) immunity. This novel D-latch can tolerate particles as charge injection in different internal nodes, as well as the input and output nodes. The performance of the new circuit has been assessed through different key parameters, such as power consumption, delay, Power-Delay Product (PDP) at various frequencies, voltage, temperature, and process variations. A set of simulations has been set up to benchmark the new proposed D-latch in comparison to previous D-latches, such as the Static D-latch, TPDICE-based D-latch, LSEH-1 and DICE D-latches. A comparison between these simulations proves that the proposed D-latch not only has a better immunity, but also features lower power consumption, delay, PDP, and area footprint. Moreover, the impact of temperature and process variations, such as aspect ratio (W/L) and threshold voltage transistor variability, on the proposed D-latch with regard to previous D-latches is investigated. Specifically, the delay and PDP of the proposed D-latch improves by 60.3% and 3.67%, respectively, when compared to the reference Static D-latch. Furthermore, the standard deviation of the threshold voltage transistor variability impact on the delay improved by 3.2%, while its impact on the power consumption improves by 9.1%. Finally, it is shown that the standard deviation of the (W/L) transistor variability on the power consumption is improved by 56.2%.

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2

Gupta, Kirti, Neeta Pandey y Maneesha Gupta. "MCML D-Latch Using Triple-Tail Cells: Analysis and Design". Active and Passive Electronic Components 2013 (2013): 1–9. http://dx.doi.org/10.1155/2013/217674.

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A new low-voltage MOS current mode logic (MCML) topology for D-latch is proposed. The new topology employs a triple-tail cell to lower the supply voltage requirement in comparison to traditional MCML D-latch. The design of the proposed MCML D-latch is carried out through analytical modeling of its static parameters. The delay is expressed in terms of the bias current and the voltage swing so that it can be traded off with the power consumption. The proposed low-voltage MCML D-latch is analyzed for the two design cases, namely, high-speed and power-efficient, and the performance is compared with the traditional MCML D-latch for each design case. The theoretical propositions are validated through extensive SPICE simulations using TSMC 0.18 µm CMOS technology parameters.

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3

Talebipoor, Neda, Peiman Keshavarzian y Behzad Irannejad. "Low Power and High Speed D-Latch Circuit Designs Based on Carbon Nanotube FET". International Journal of Engineering & Technology 2, n.º 1 (16 de noviembre de 2012): 12. http://dx.doi.org/10.14419/ijet.v2i1.483.

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In this paper we propose low power and high speed D-latche circuits base on carbon nanotube field effect transistor. D-latches are the important state-holding elements and systems performance enhancement will be achieved by improving the flip-flop latches structure. The circuit designs are simulated by Hspice .In this paper the consumption result of the circuit parameters such as delay, power and PDP for our three different D-latch circuit design in various voltages and different temperatures.

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4

Liu Po Ching y Ong Geok Ling. "Low-power and low-voltage D-latch". Electronics Letters 34, n.º 7 (1998): 641. http://dx.doi.org/10.1049/el:19980447.

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5

Vanak, Amin y Reza Sabbaghi-Nadooshan. "Improvement of Power and Performance in NAND and D-Latch Gates Using CNFET Technology". Journal of Nano Research 33 (junio de 2015): 126–36. http://dx.doi.org/10.4028/www.scientific.net/jnanor.33.126.

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In this paper, low power and high speed D-latch and nand gates (as sample of combinational and sequential circuits) are designed based on cnfet and cmos technology. The performance of D-latch and nand is compared in two technologies of 65nm and 90nm in cmos and cnfet technology. The circuit designs are simulated using hspice. Finally, the power consumption and delay and pdp as well as rise and fall time are compared in various voltages and frequencies. The results show that cnfetD-latch and nand gates have better delay and power consumption in comparison to cmos technology.

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6

Ong, Geok Ling y Po-Ching Liu. "Technique for lower power dissipation in D-latch". Electronics Letters 34, n.º 18 (1998): 1733. http://dx.doi.org/10.1049/el:19981207.

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7

Banerjee, Anirban, Vikash Prasad y Debaprasad Das. "Design and Analysis of Ternary D-Latch Using CNTFETs". Journal of Nano- and Electronic Physics 11, n.º 4 (2019): 04011–1. http://dx.doi.org/10.21272/jnep.11(4).04011.

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8

K.G.Sharma, Abhilasha. "Optimum Design of D-Latch for Low power Applications". IOSR Journal of Engineering 02, n.º 04 (abril de 2012): 604–8. http://dx.doi.org/10.9790/3021-0204604608.

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9

Pandey, Neeta, Kirti Gupta y Maneesha Gupta. "An efficient triple-tail cell based PFSCL D latch". Microelectronics Journal 45, n.º 8 (agosto de 2014): 1001–7. http://dx.doi.org/10.1016/j.mejo.2014.05.002.

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10

Singar, Sumitra y P. K. Ghosh. "Fault-Free D-Latch Configurations for Low Power Applications". Journal of Nanoelectronics and Optoelectronics 13, n.º 5 (1 de mayo de 2018): 701–7. http://dx.doi.org/10.1166/jno.2018.2264.

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11

Seo, Duck-Kyu y Jun-Cheol Jeon. "Loop-Based QCA RAM Cell Design Using Multilayer-Based D Latch". Journal of Korean Institute of Information Technology 18, n.º 6 (30 de junio de 2020): 25–31. http://dx.doi.org/10.14801/jkiit.2020.18.6.25.

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12

Alioto, M., R. Mita y G. Palumbo. "Performance evaluation of the low-voltage CML D-latch topology". Integration 36, n.º 4 (noviembre de 2003): 191–209. http://dx.doi.org/10.1016/j.vlsi.2003.09.001.

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13

Prasanth, Chaluvadi, Mante Anil, Kolla Sahithi y K. Vijay Raviteja. "Design of Low-Power Reversible Carry Select Adder using D-Latch". IJIREEICE 5, n.º 4 (15 de abril de 2017): 52–57. http://dx.doi.org/10.17148/ijireeice.2017.5410.

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14

Alioto, M. y G. Palumbo. "Power-delay optimization of D-latch/MUX source coupled logic gates". International Journal of Circuit Theory and Applications 33, n.º 1 (enero de 2005): 65–86. http://dx.doi.org/10.1002/cta.305.

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15

Majeed, Ali, Esam Alkaldy, Mohd Zainal y Danial Nor. "Novel Memory Structures in QCA Nano Technology". 3D SCEEER Conference sceeer, n.º 3d (1 de julio de 2020): 119–24. http://dx.doi.org/10.37917/ijeee.sceeer.3rd.17.

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Quantum-dot Cellular Automata (QCA) is a new emerging technology for designing electronic circuits in nanoscale. QCA technology comes to overcome the CMOS limitation and to be a good alternative as it can work in ultra-high-speed. QCA brought researchers attention due to many features such as low power consumption, small feature size in addition to high frequency. Designing circuits in QCA technology with minimum costs such as cells count and the area is very important. This paper presents novel structures of D-latch and D-Flip Flop with the lower area and cell count. The proposed Flip-Flop has SET and RESET ability. The proposed latch and Flip-Flop have lower complexity compared with counterparts in terms of cell counts by 32% and 26% respectively. The proposed circuits are designed and simulated in QCADesigner software.

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16

PRASAD, M., U. B. MAHADEVASWAMY y DANDAVATIMATH PRASHANT. "SQUARE ROOT CARRY SELECT ADDER USING MTTSPC D-LATCH IN 90nm TECHNOLOGY". i-manager’s Journal on Electronics Engineering 9, n.º 3 (2019): 14. http://dx.doi.org/10.26634/jele.9.3.15267.

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17

Safipoor, Fatemeh, Reza Faghih Mirzaee y Mahdi Zare. "High-performance quaternary latch and D-Type flip-flop with selective outputs". Microelectronics Journal 113 (julio de 2021): 105079. http://dx.doi.org/10.1016/j.mejo.2021.105079.

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18

Al-Humidi, Abdullah Ali y Abdulraqib Abdo Asaad. "Ternary Electronic Logic Systems Automation: A Novel Study Based on VHDL Language Third Part: Ternary Non-Combinational (Sequential) Logic Components". Journal of Science and Technology 24, n.º 2 (3 de junio de 2020): 47–75. http://dx.doi.org/10.20428/jst.24.2.3.

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In this scientific paper, the third part of the software library for the Ternary non-combinational (Sequential) logic components (the components that store information) will be built based on VHDL language starting by the Ternary D Latch (TDL) and ending by the Ternary RAM (TRAM).

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19

Jagadeesan, Neeraja, B. Saman, M. Lingalugari, P. Gogna y F. Jain. "Sequential Logic Circuits Using Spatial Wavefunction Switched (SWS) FETs". International Journal of High Speed Electronics and Systems 24, n.º 03n04 (septiembre de 2015): 1550011. http://dx.doi.org/10.1142/s0129156415500111.

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The spatial wavefunction-switched field-effect transistor (SWSFET) is one of the promising quantum well devices that transfers electrons from one quantum well channel to the other channel based on the applied gate voltage. This eliminates the use of more transistors as we have coupled channels in the same device operating at different threshold voltages. This feature can be exploited in many digital integrated circuits thus reducing the count of transistors which translates to less die area. The simulations of basic sequential circuits like SR latch, D latch and flip flop are presented here using SWSFET based logic gates. The circuit model of a SWSFET was developed using Berkeley short channel IGFET model (BSIM 3).

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20

JUNG, INHWA, MOO-YOUNG KIM y CHULWOO KIM. "SPTPL: A NEW PULSED LATCH TYPE FLIP-FLOP IN HIGH-PERFORMANCE SYSTEM-ON-A-CHIP (SoC)". Journal of Circuits, Systems and Computers 16, n.º 02 (abril de 2007): 169–79. http://dx.doi.org/10.1142/s0218126607003472.

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In many VLSI chips, the power dissipation of the clocking system that includes clock distribution network and flip-flops is often the largest portion of total chip power consumption. In the near future, this portion is likely to dominate total chip power consumption due to higher clock frequency and deeper pipeline design trend. Traditionally, two approaches have been used: (1) to reduce power consumption in the clock tree, several low-swing clock flip-flops and double-edge flip-flops have been introduced; (2) to reduce power consumption in flip-flops, conditional capture, clock-on-demand, data-transition look-ahead techniques have been developed. Recently, pulsed latch type flip-flops are introduced in several high-performance microprocessors to reduce E × D. In this paper, these flip-flops are described with their pros and cons. Then, a new circuit technique is described along with simulation results. The proposed pulsed latch reduces E × D by 82.6% to 95.4% compared to conventional flip-flops.

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21

CHANG, ROBERT C., L. C. HSU y M. C. SUN. "A LOW-POWER AND HIGH-SPEED D FLIP-FLOP USING A SINGLE LATCH". Journal of Circuits, Systems and Computers 11, n.º 01 (febrero de 2002): 51–55. http://dx.doi.org/10.1142/s0218126602000239.

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A novel low-power and high-speed D flip-flop is presented in this letter. The flip-flop consists of a single low-power latch, which is controlled by a positive narrow pulse. Hence, fewer transistors are used and lower power consumption is achieved. HSPICE simulation results show that power dissipation of the proposed D flip-flop has been reduced up to 76%. The operating frequency of the flip-flop is also greatly increased.

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22

Jang, Young-Min, Ying He, Sang-Bok Cho, Ji-Hoon Kim y Sung Min Park. "A Modified 2-D Vernier Time-to-digital Converter Using Resettable T-latch". JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE 19, n.º 5 (31 de octubre de 2019): 477–84. http://dx.doi.org/10.5573/jsts.2019.19.5.477.

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23

QIAO, FEI, HUAZHONG YANG, DINGLI WEI y HUI WANG. "MODIFIED CONDITIONAL-PRECHARGE SENSE-AMPLIFIER-BASED FLIP-FLOP WITH IMPROVED SPEED". Journal of Circuits, Systems and Computers 16, n.º 02 (abril de 2007): 199–210. http://dx.doi.org/10.1142/s0218126607003654.

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A modified version of conditional-precharge sense-amplifier-based flip-flop (mCP-SAFF) is proposed. By using the differential clocked CMOS (C2MOS) latch with one shared output holder and the conditional-precharge modules to simplify the sense-amplifier latch, the mCP-SAFF can achieve a much shorter input to output delay (D-to-Q delay) and more symmetrical rising/falling delays than those of the original conditional-precharge sense-amplifier-based flip-flops (CP-SAFF). Post-layout simulation results show that the mCP-SAFF, compared with the widely used conventional DFF, does not suffer neither timing nor area penalties and have achieved up to 34% of power reduction ratio and 33% of power-delay-product (PDP) reduction ratio, respectively. And the mCP-SAFF is comparable to the prevailing DFFs with regard to noise immunity performance.

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24

Dimitrov, D. P. y T. K. Vasileva. "Eight-Bit Semiflash A/D Converter". VLSI Design 2007 (12 de julio de 2007): 1–7. http://dx.doi.org/10.1155/2007/80389.

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An 8-bit semiflash ADC is reported that uses a single array of 15 comparators for both the coarse and the fine conversion. Conversion is implemented in two steps. First, an estimate is made of the 4 most significant bits, which are then memorized in the output latch. Next, the remaining 4 bits are evaluated by the same array of comparators. The auto-zeroed comparators also perform the function of a sample-and-hold circuit. In the proposed 8-bit semiflash ADC, there are no sample-and-hold circuit, no DAC, no subtraction circuit, and no residue amplifier. As a result, a moderate conversion speed has been combined with a drastically reduced power consumption. The ADC was fabricated in a standard 0.6 μm double-poly, double-metal CMOS process. Experimental results show monotonic conversion with very low integral and differential nonlinearities. These features, combined with the ultra-low power consumption, make the proposed circuit very suitable for low-power mixed-signal applications.

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25

Karimlee, M. y HRSM Naeini. "Comparison of D-Latch based on CNTFET & DLatch based on MOSFET using HSPICE". Journal of Fundamental and Applied Sciences 8, n.º 4 (18 de agosto de 2016): 2118. http://dx.doi.org/10.4314/jfas.v8i2s.171.

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26

Reis, C., A. Maziotis, C. Kouloumentas, C. Stamatiadis, M. Bougioukos, N. Calabretta, P. André et al. "All-optical clocked D flip-flop memory using a hybrid integrated S-R latch". Microwave and Optical Technology Letters 53, n.º 6 (25 de marzo de 2011): 1201–4. http://dx.doi.org/10.1002/mop.25998.

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27

Seyedi, Saeid, Mehdi Darbandi y Nima Jafari Navimipour. "Designing an efficient fault tolerance D-latch based on quantum-dot cellular automata nanotechnology". Optik 185 (mayo de 2019): 827–37. http://dx.doi.org/10.1016/j.ijleo.2019.03.029.

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28

Wang, Zhi Ping, Ai Dong Xu, Yan Song y Bing Jun Yan. "Design and Develop of Functional Safety Temperature Transmitter for Fault Status". Applied Mechanics and Materials 385-386 (agosto de 2013): 1272–77. http://dx.doi.org/10.4028/www.scientific.net/amm.385-386.1272.

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According to the requirements of the functional safety temperature transmitter high reliability, this paper selects the micro-power voltage reference, the reset monitor, the D-type flip-flop and the OR gate to design the functional safety temperature transmitter protection circuit for fault status. The protection circuit takes power from the data line of HART fieldbus by micro-power voltage references. According to the control signal of the functional safety transmitter, the protection circuit utilizes the state latch of D-type flip-flop, and realizes the functional safety temperature transmitter protection circuit for fault status.

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29

Singh, Rupali y Devendra Kumar Sharma. "QCA-Based RAM Design Using a Resilient Reversible Gate with Improved Performance". Journal of Circuits, Systems and Computers 29, n.º 13 (20 de marzo de 2020): 2050209. http://dx.doi.org/10.1142/s0218126620502096.

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Reversible logic and Quantum dot cellular automata are the prospective pillars of quantum computing. These paradigms can potentially reduce the size and power of the future chips while simultaneously maintaining the high speed. RAM cell is a crucial component of computing devices. Design of a RAM cell using a blend of reversible logic and QCA technology will surpass the limitations of conventional RAM structure. This motivates us to explore the design of a RAM cell using reversible logic in QCA framework. The performance of a reversible circuit can be improved by utilizing a resilient reversible gate. This paper presents the design of QCA-based reversible RAM cell using an efficient, fault-tolerant and low power reversible gate. Initially, a novel reversible gate is proposed and implemented in QCA. The QCA layout of the proposed reversible gate is designed using a unique multiplexer circuit. Further, a comprehensive analysis of the gate is carried out for standard Boolean functions, cost function and power dissipation and it has been found that the proposed gate is 75.43% more cost-effective and 58.54% more energy-efficient than the existing reversible gates. To prove the inherent testability of the proposed gate, its rigorous testing is carried out against various faults and the proposed gate is found to be 69.2% fault-tolerant. For all the performance parameters, the proposed gate has performed considerably better than the existing ones. Furthermore, the proposed gate is explicitly used for designing reversible D latch and RAM cell, which are crucial modules of sequential logic circuits. The proposed latch is 45.4% more cost effective than the formerly reported D latch. The design of QCA-based RAM cell using reversible logic is novel and not reported earlier in the literature.

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30

Singh, Rupali y Devendra Kumar Sharma. "Fault Tolerant Reversible Gate Based Sequential Quantum Dot Cellular Automata Circuits: Design and Contemplation". Journal of Nanoelectronics and Optoelectronics 15, n.º 3 (1 de marzo de 2020): 331–44. http://dx.doi.org/10.1166/jno.2020.2745.

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In the era of quantum computing, Quantum Dot Cellular Automata (QCA) is a phenomenal technology which can produce low power, high speed and area efficient circuits. On the other hand, reversible logic is a promising paradigm which is used to construct low power circuits. This paper presents a design of a unique reversible gate based on QCA. This gate can facilitate the design of complex, cost efficient sequential circuits. The proposed gate is examined for various performance parameters such as realization of standard Boolean functions, cost function, energy dissipation and fault characterization. It is observed that the proposed gate exhibits superior performance as compared to the previously reported cost efficient designs in all the performance parameters. Furthermore, to evaluate the efficacy of the proposed QCA gate, reversible sequential latches are designed. The proposed structures of latches excel over the similar existing designs and have shown 50% improvement in latency, 58% improvement in effective cell area and around 70% improvement in cost function. The proposed latches are further investigated for temperature alterations to find the operating range of temperature for the circuits. The reversible QCA gate, proposed in this paper can be effectively used to design D latch, T latch, JK latch with improved performance. Hence, the proposed gate can find extensive scope in designing cost effective, low power, reversible sequential and combinational circuits.

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31

Hourcade, Dennis E. y Lynne M. Mitchell. "Access to the Complement Factor B Scissile Bond Is Facilitated by Association of Factor B with C3b Protein". Journal of Biological Chemistry 286, n.º 41 (23 de agosto de 2011): 35725–32. http://dx.doi.org/10.1074/jbc.m111.263418.

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Factor B is a zymogen that carries the catalytic site of the complement alternative pathway C3 convertase. During convertase assembly, factor B associates with C3b and Mg2+ forming a pro-convertase C3bB(Mg2+) that is cleaved at a single factor B site by factor D. In free factor B, a pair of salt bridges binds the Arg234 side chain to Glu446 and to Glu207, forming a double latch structure that sequesters the scissile bond (between Arg234 and Lys235) and minimizes its unproductive cleavage. It is unknown how the double latch is released in the pro-convertase. Here, we introduce single amino acid substitutions into factor B that preclude one or both of the Arg234 salt bridges, and we examine their impact on several different pro-convertase complexes. Our results indicate that loss of the Arg234-Glu446 salt bridge partially stabilizes C3bB(Mg2+). Loss of the Arg234-Glu207 salt bridge has lesser effects. We propose that when factor B first associates with C3b, it bears two intact Arg234 salt bridges. The complex rapidly dissociates unless the Arg234-Glu446 salt bridge is released whereupon conformational changes occur that activate the metal ion-dependent adhesion site and partially stabilize the complex. The remaining salt bridge is then released, exposing the scissile bond and permitting factor D cleavage.

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32

Wang, Ye, Yong Sheng Yin, Lang Wang y Hong Hui Deng. "Design of the High-Speed High-Resolution Latched Comparator". Advanced Materials Research 748 (agosto de 2013): 853–58. http://dx.doi.org/10.4028/www.scientific.net/amr.748.853.

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Based on the latch and comparison theory, a high-speed high-resolution latched comparator is designed in this paper by using a standard 0.18μm/1.8V CMOS process. With the sampling frequency of 400MHz, the Cadence Spectre simulation results show that the regeneration time is around 230ps and only 11.83mV offset voltage, power consumption is 2.12mW, the minimum voltage resolution is 0.2mV without any input offset error. The circuit is applicable for the design of a high-speed high-resolution A/D converter.

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33

Ashis Kumar Mandal. "All-optical Frequency Divider using TOAD based D-Flip-Flop". January 2021 7, n.º 01 (29 de enero de 2021): 152–57. http://dx.doi.org/10.46501/ijmtst070133.

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From the last few decades the optical communication has been established as much easier process than electrical communication. Many optical proposed circuits have already been suggested in many fields in support of this. The optical communication circuits demand frequency dividers capable of operating well above 10 GHz. Here, an all-optical frequency divider using terahertz optical asymmetric demultiplexer (TOAD) based D-flip-flop is proposed in the optical domain in a configuration exactly like the standard electronic setup. It presents a high-speed flip-flop-based frequency divider incorporating a new high-speed latch topology with satisfactory performance. The proposed all-optical frequency division scheme has been theoretically demonstrated in this paper. In this scheme the input and output binary digits are expressed as the presence (1) and the absence (0) of the light pulses. The performance of this proposed optical realization is evaluated by numerical simulation that confirms its feasibility in terms of the choice of the critical parameters.

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34

Singh, Lalitesh y Surendra Bohra. "Design of Low Power High Speed D-Latch Using Stacked Inverter and Sleep Transistor at 32nm CMOS Technology". International Journal of Trend in Scientific Research and Development Volume-2, Issue-4 (30 de junio de 2018): 1414–18. http://dx.doi.org/10.31142/ijtsrd14138.

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35

Blaes, B. R., G. A. Soli y M. G. Buehler. "Bench-level characterization of a CMOS standard-cell D-latch using alpha-particle sensitive test circuits". IEEE Transactions on Nuclear Science 38, n.º 6 (1991): 1486–92. http://dx.doi.org/10.1109/23.124136.

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36

Aytar, Oktay. "Design of A 5-Bit Fully Parallel Analog to Digital Converter Using Common Gate Differrential Mos Pair-Based Comparator". Journal of Electrical Engineering 66, n.º 5 (1 de septiembre de 2015): 250–56. http://dx.doi.org/10.2478/jee-2015-0041.

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Abstract This paper presents a novel comparator structure based on the common gate differential MOS pair. The proposed comparator has been applied to fully parallel analog to digital converter (A/D converter). Furthermore, this article presents 5 bit fully parallel A/D Converter design using the cadence IC5141 design platform and NCSU(North Carolina State University) design kit with 0.18 μm CMOS technology library. The proposed fully parallel A/D converter consist of resistor array block, comparator block, 1-n decoder block and programmable logic array. The 1-n decoder block includes latch block and thermometer code circuit that is implemented using transmission gate based multiplexer circuit. Thus, sampling frequency and analog bandwidth are increased. The INL and DNL of the proposed fully parallel A/D converter are (0/ + 0.63) LSB and (−0.26/ + 0.31) LSB at a sampling frequency of 5 GS/s with an input signal of 50 MHz, respectively. The proposed fully parallel A/D Converter consumes 340 mW from 1.8 V supply.

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37

Philips, Elliot A., Antonio Garcia-España, Anna S. Tocheva, Ian M. Ahearn, Kieran R. Adam, Ruimin Pan, Adam Mor y Xiang-Peng Kong. "The structural features that distinguish PD-L2 from PD-L1 emerged in placental mammals". Journal of Biological Chemistry 295, n.º 14 (27 de diciembre de 2019): 4372–80. http://dx.doi.org/10.1074/jbc.ac119.011747.

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Programmed cell death protein 1 (PD-1) is an inhibitory receptor on T lymphocytes that is critical for modulating adaptive immunity. As such, it has been successfully exploited for cancer immunotherapy. Programmed death ligand 1 (PD-L1) and PD-L2 are ligands for PD-1; the former is ubiquitously expressed in inflamed tissues, whereas the latter is restricted to antigen-presenting cells. PD-L2 binds to PD-1 with 3-fold stronger affinity compared with PD-L1. To date, this affinity discrepancy has been attributed to a tryptophan (W110PD-L2) that is unique to PD-L2 and has been assumed to fit snuggly into a pocket on the PD-1 surface. Contrary to this model, using surface plasmon resonance to monitor real-time binding of recombinantly-expressed and -purified proteins, we found that W110PD-L2 acts as an “elbow” that helps shorten PD-L2 engagement with PD-1 and therefore lower affinity. Furthermore, we identified a “latch” between the C and D β-strands of the binding face as the source of the PD-L2 affinity advantage. We show that the 3-fold affinity advantage of PD-L2 is the consequence of these two opposing features, the W110PD-L2 “elbow” and a C–D region “latch.” Interestingly, using phylogenetic analysis, we found that these features evolved simultaneously upon the emergence of placental mammals, suggesting that PD-L2–affinity tuning was part of the alterations to the adaptive immune system required for placental gestation.

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38

Ma, Yong, Yongjian Yu, Jian Lu, Qiaoyun Zou y Huibin Zhang. "Effect of manufacturing technics on the microstructure and temperature-affected electrical performance of D-type latch devices". Microelectronics Journal 99 (mayo de 2020): 104757. http://dx.doi.org/10.1016/j.mejo.2020.104757.

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39

Fatkurocman, Andi y Ach Kusairi Samlawi. "ANALISA KEGAGALAN KOMPONEN DRIVE PINION GEAR PADA SWING MOTOR EXCAVATOR CATERPILLAR 349D". JTAM ROTARY 2, n.º 1 (20 de abril de 2020): 79. http://dx.doi.org/10.20527/jtam_rotary.v2i1.2006.

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Penelitian ini bertujuan untuk mengetahui alasan fraktur yang terjadi pada drive pinion gear unit motor swing Excavator Caterpillar 349 d. Dalam penelitian ini dilakukan beberapa tahapan yaitu pengamatan visual dan pengamatan makro, pengujian komposisi struktur logam, dan pemodelan load and latch menggunakan Autodesk Inventor 2014 sebelum mendapatkan hasil akhir. Hasil yang diperoleh dari penelitian ini adalah bahwa ada kurangnya presisi antara pinion drive dan planetary gear karena pin planet yang tidak dapat berfungsi sebagai pemegang planetary gear sehingga rotasi planet rentan terhadap tabrakan sebagai pemicu yang mengakibatkan cacat. Pada proses analisis tegangan menggunakan software autodesk inventor 2014 versi mahasiswa, hasil analisis nilai von misses adalah 9,798 Mpa jauh lebih kecil dari batas elastisitas material 790 MPa sehingga faktor pembebanan tidak menyebabkan sebuah kesalahan. This research is purpose to knowing the reason of the fracture that happen in drive pinion gear of the swing motor unit Excavator Caterpillar 349 d. In this research is doing by several stage it is visual observation and macro observation, testing of metal structure composition, and load and latch modeling using Autodesk Inventor 2014 before getting the final result. The results obtained from this study are that there is a lack of precision between drive pinion gear and planetary gear due to planetary pins that cannot function as planetary gear holders so that planetary rotations are prone to hilarious triggering collisions resulting in defects. In the process of stress analysis using the student version of autodesk inventor 2014 software, the results of the analysis of the value of von misses is 9.798 Mpa are much smaller than the limit of material elasticity of 790 MPa so that the loading factor does not cause a fault.

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40

ZHANG, YAJING, WENGAO LU, GUANNAN WANG, ZHONGJIAN CHEN y YACONG ZHANG. "A LOW POWER HIGH RESOLUTION ROIC DESIGN WITH 14-BIT COLUMN-LEVEL ADC FOR 384 × 288 IRFPA". Journal of Circuits, Systems and Computers 22, n.º 09 (octubre de 2013): 1340015. http://dx.doi.org/10.1142/s021812661340015x.

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A readout integrated circuit (ROIC) of infrared focal plane array (IRFPA) with low power and low noise is presented in this paper. It consists of a 384 × 288 pixel array and column-level A/D conversion circuits. The proposed system has high resolution because of the odd–even Analog to Digital Conversion (ADC) structure, containing correlated switches design, multi-Vth amplifier design and high speed high resolution comparator design including latch-stage. Designed and simulated in 0.35-μm CMOS process, this high performance ROIC achieves 81.24 dB SNR at 8.64 KS/s consuming 98 mW under 5 V voltage supply, resulting in an ENOB of 13.2-bit.

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41

Samel, Stefan A., Paul Czodrowski y Lars-Oliver Essen. "Structure of the epimerization domain of tyrocidine synthetase A". Acta Crystallographica Section D Biological Crystallography 70, n.º 5 (30 de abril de 2014): 1442–52. http://dx.doi.org/10.1107/s1399004714004398.

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Tyrocidine, a macrocyclic decapeptide fromBacillus brevis, is nonribosomally assembled by a set of multimodular peptide synthetases, which condense two D-amino acids and eight L-amino acids to produce this membrane-disturbing antibiotic. D-Phenylalanine, the first amino acid incorporated into tyrocidine, is catalytically derived from enzyme-bound L-Phe by the C-terminal epimerization (E) domain of tyrocidine synthetase A (TycA). The 1.5 Å resolution structure of the cofactor-independent TycA E domain reveals an intimate relationship to the condensation (C) domains of peptide synthetases. In contrast to the latter, the TycA E domain uses an enlarged bridge region to plug the active-site canyon from the acceptor side, whereas at the donor side a latch-like floor loop is suitably extended to accommodate the αIII helix of the preceding peptide-carrier domain. Additionally, E domains exclusively harbour a conserved glutamate residue, Glu882, that is opposite the active-site residue His743. This active-site topology implies Glu882 as a candidate acid–base catalyst, whereas His743 stabilizes in the protonated state a transient enolate intermediate of the L↔D isomerization.

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42

Pandey, Neeta, Bharat Choudhary, Kirti Gupta y Ankit Mittal. "New Sleep-Based PFSCL Tri-State Inverter/Buffer Topologies". Journal of Circuits, Systems and Computers 26, n.º 12 (agosto de 2017): 1750186. http://dx.doi.org/10.1142/s0218126617501869.

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This paper describes new sleep-based positive feedback source-coupled logic (PFSCL) tri-state inverter/buffer topologies. The tri-state behavior is obtained by disconnecting the circuit from both power supply and ground. This is achieved by placing additional transistors, driving the load transistor to cut off or disabling the current source. The combination of the three methods results in six new topologies. The functionality and performance of the proposed topologies is studied through SPICE simulations. A comparison with available sleep-based PFSCL tri-state buffer circuit shows a maximum reduction of 11% and 60% in the propagation delay and output enable time, respectively. The usefulness of the proposed topologies is illustrated through bus and D latch implementation.

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43

Fang, E. S., D. Hebert y T. Van Duzer. "A multi-gigahertz, Josephson flash A/D converter with a pipelined encoder using large-dynamic-range current-latch comparators". IEEE Transactions on Magnetics 27, n.º 2 (marzo de 1991): 2891–94. http://dx.doi.org/10.1109/20.133813.

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44

Andrews, Lauren B., Alec A. K. Nielsen y Christopher A. Voigt. "Cellular checkpoint control using programmable sequential logic". Science 361, n.º 6408 (20 de septiembre de 2018): eaap8987. http://dx.doi.org/10.1126/science.aap8987.

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Biological processes that require orderly progression, such as growth and differentiation, proceed via regulatory checkpoints where the cell waits for signals before continuing to the next state. Implementing such control would allow genetic engineers to divide complex tasks into stages. We present genetic circuits that encode sequential logic to instructEscherichia colito proceed through a linear or cyclical sequence of states. These are built with 11 set-reset latches, designed with repressor-based NOR gates, which can connect to each other and sensors. The performance of circuits with up to three latches and four sensors, including a gated D latch, closely match predictions made by using nonlinear dynamics. Checkpoint control is demonstrated by switching cells between multiple circuit states in response to external signals over days.

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45

Monga, Kanika, Nitin Chaturvedi y S. Gurunarayanan. "Energy-efficient data retention in D flip-flops using STT-MTJ". Circuit World 46, n.º 4 (20 de junio de 2020): 229–41. http://dx.doi.org/10.1108/cw-09-2018-0073.

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Purpose Emerging event-driven applications such as the internet-of-things requires an ultra-low power operation to prolong battery life. Shutting down non-functional block during standby mode is an efficient way to save power. However, it results in a loss of system state, and a considerable amount of energy is required to restore the system state. Conventional state retentive flip-flops have an “Always ON” circuitry, which results in large leakage power consumption, especially during long standby periods. Therefore, this paper aims to explore the emerging non-volatile memory element spin transfer torque-magnetic tunnel junction (STT-MTJ) as one the prospective candidate to obtain a low-power solution to state retention. Design/methodology/approach The conventional D flip-flop is modified by using STT-MTJ to incorporate non-volatility in slave latch. Two novel designs are proposed in this paper, which can store the data of a flip-flip into the MTJs before power off and restores after power on to resume the operation from pre-standby state. Findings A comparison of the proposed design with the conventional state retentive flip-flop shows 100 per cent reduction in leakage power during standby mode with 66-69 per cent active power and 55-64 per cent delay overhead. Also, a comparison with existing MTJ-based non-volatile flip-flop shows a reduction in energy consumption and area overhead. Furthermore, use of a fully depleted-silicon on insulator and fin field-effect transistor substituting a complementary metal oxide semiconductor results in 70-80 per cent reduction in the total power consumption. Originality/value Two novel state-retentive D flip-flops using STT-MTJ are proposed in this paper, which aims to obtain zero leakage power during standby mode.

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46

YAMAGUCHI, T., Y. KAWASE y T. ASANO. "Dynamic Analysis of Latch-in Relay Using 3-D Finite Element Method with Mesh Modification Method Employing Multi-Mesh and the Interpolation". Journal of the Japan Society of Applied Electromagnetics and Mechanics 21, n.º 3 (2013): 375–79. http://dx.doi.org/10.14243/jsaem.21.375.

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47

Singh, Rupali y Devendra Kumar Sharma. "Design of efficient multilayer RAM cell in QCA framework". Circuit World 47, n.º 1 (21 de mayo de 2020): 31–41. http://dx.doi.org/10.1108/cw-10-2019-0138.

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Purpose Quantum-dot cellular automata (QCA) is a promising technology, which seems to be the prospective substitute for complementary metal-oxide semiconductor (CMOS). It is a high speed, high density and low power paradigm producing efficient circuits. These days, most of the smart devices used for computing, make use of random access memory (RAM). To enhance the performance of a RAM cell, researchers are putting effort to minimize its area and access time. Multilayer structures in QCA framework are area efficient, fast and immune to the random interference. Unlike CMOS, QCA multilayer architectures can be designed using active components on different layers. Thus, using multilayer topology in the design of a RAM cell, which is not yet reported in the literature can improve the performance of RAM and hence, the computing device. This paper aims to present the modular design of RAM cell with multilayer structures in the QCA framework. The fundamental modules such as XOR gate, 2:1 multiplexer and D latch are proposed here using multilayer formations with the goal of designing a RAM cell with the provision of read, write, set and reset control. Design/methodology/approach All the modules used to design a RAM cell are designed using multilayer approach in QCA framework. Findings The proposed multilayer RAM cell is optimized and has shown an improvement of 20% in cell count, 30% in area, 25% in area latency product and 48.8% in cost function over the other efficient RAM designs with set/reset ability reported earlier. The proposed RAM cell is further analyzed for the fault tolerance and power dissipation. Research limitations/implications Due to the multilayer structure, the complexity of the circuit enhances which can be eliminated using simple architectures. Originality/value The performance metrics and results obtained establish that the multilayer approach can be implemented in the QCA circuit to produce area efficient and optimized sequential circuits such as a latch, flip flop and memory cells.

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48

Mauzé, Marie, Claude Meillassoux, Alain Testart, Dominique Legros y Serge Gruzinski. "Boas, les Kwagul et le pot latch. Éléments pour une réévaluation, suivi des commentaires de C. Meillassoux, A. Testart, D. Legros, S. Gruzinski, et d'une réponse de M. Mauzé". L'Homme 26, n.º 100 (1986): 21–63. http://dx.doi.org/10.3406/hom.1986.368658.

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49

Guo, Benqing, Jing Gong, Yao Wang y Jingwei Wu. "A 0.2–3.3 GHz 2.4 dB NF 45 dB gain CMOS current-mode receiver front-end". Modern Physics Letters B 34, n.º 22 (6 de junio de 2020): 2050226. http://dx.doi.org/10.1142/s0217984920502267.

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A CMOS fully differential current-mode front-end for SAW-less receivers is proposed. The noise-canceling LNTA has a main path of the common-gate (CG) stage and an auxiliary path of the inverter stage. A current mirror is used to combine the signals from the main and auxiliary paths in current mode. The stacked nMOS/pMOS configurations improve their power efficiency. The traditional stacked tri-state inverter as D-latch replaced by the discrete inverter and transmission gate enables a reduced supply voltage of divider core. LO generator based on the improved divider provides quarter LO signals to drive the proposed LNTA-shared receiver front-end. Simulation results in 180 nm CMOS indicate that the integrated receiver front-end provides an NF of 2.4 dB, and a maximum gain of 45 dB from 0.2 to 3.3 GHz. The in-band (IB) and out-of-band (OB) IIP3 of 2.5 dBm and 4 dBm, are obtained, respectively. With CMOS scaling down continuously, CMOS devices are providing increased transit frequency and reduced intrinsic parasitics which are important for radio frequency (RF) and millimeter-wave applications. As a promising solution, CMOS RF delivers comparable performance to silicon bipolar and GaAs devices but at a much lower cost and higher integration level. Supply voltage reduction with CMOS scaling down also poses a stringent linearity requirement. Avoiding the conventional trade-off between the supply voltage and linearity headroom, the proposed receiver front-end based on the current mode principle is with weak linearity dependency on the supply voltage and provides excellent anti-blocker interference capability.

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Xie, Longfei, Faris Rafi Almay Widagdo, Lihu Dong y Fengri Li. "Modeling Height–Diameter Relationships for Mixed-Species Plantations of Fraxinus mandshurica Rupr. and Larix olgensis Henry in Northeastern China". Forests 11, n.º 6 (28 de mayo de 2020): 610. http://dx.doi.org/10.3390/f11060610.

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The mixture of tree species has gradually become the focus of forest research, especially native species mixing. Mixed-species plantations of Manchurian ash (Fraxinus mandshurica Rupr.) and Changbai larch (Larix olgensis Henry) have successfully been cultivated in Northeast China. Height–diameter (H–D) models were found to be effective in designing the silvicultural planning for mixed-species plantations. Thus, this study aimed to develop a new system of H–D models for juvenile ash and larch mixed-species plantations, based on competition information and tree and stand attributes. The leave-one-out cross-validation was utilized for model validation. The result showed that the H–D relationship was affected not only by the tree attributes (i.e., tree size and competition information) but also by stand characteristics, such as site quality and species proportion of basal area. The best model explained more than 80% and 85% variation of the tree height of ash and larch, respectively. Moreover, model validation also confirmed the high accuracy of the newly developed model’s predictions. We also found that, in terms of total tree height, ash in middle rows were higher than those in side rows, while larch in the middle rows were higher in the early growth period but then became lower than those in the side rows, as the diameter increased. The newly established H–D models would be useful for forestry inventory practice and have the potential to aid decisions in mixed-species plantations of ash and larch.

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