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Artículos de revistas sobre el tema "Fan out"

Autor: Grafiati

Publicado: 4 de junio de 2021

Última modificación: 13 de febrero de 2022

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1

Goodman, Joseph W. "Fan-in and Fan-out with Optical Interconnections." Optica Acta: International Journal of Optics 32, no. 12 (1985): 1489–96. http://dx.doi.org/10.1080/713821684.

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2

Becker, Karl-Friedrich, Tanja Braun, S. Raatz, et al. "On the Way from Fan-out Wafer to Fan-out Panel Level Packaging." International Symposium on Microelectronics 2016, S2 (2016): S1—S23. http://dx.doi.org/10.4071/isom-2016-slide-4.

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Fan-out Wafer Level Packaging (FOWLP) is one of the latest packaging trends in microelectronics. The technology has a high potential in significant package miniaturization concerning package volume but also in thickness. Main advantages of FOWLP are the substrate-less package, lower thermal resistance, higher performance due to shorter interconnects together with direct IC connection by thin film metallization instead of wire bonds or flip chip bumps and lower parasitic effects. Especially the inductance of the FOWLP is much lower compared to FC-BGA packages. In addition the redistribution lay

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3

Palesko, Chet, and Amy Lujan. "Cost Comparison of Fan-out Wafer-Level Packaging to Fan-out Panel-Based Packaging." International Symposium on Microelectronics 2016, no. 1 (2016): 000180–84. http://dx.doi.org/10.4071/isom-2016-wa32.

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Abstract Fan-out wafer-level packaging (FOWLP) offers many significant benefits over other packaging technologies. It is one of the smallest packaging options, but unlike fan-in wafer-level packaging, the IO count of FOWLP is not limited to the area of the die. Given these advantages, FOWLP continues to grow in popularity. While the cost of FOWLP is usually reasonable, there are still opportunities for future cost reduction. Many FOWLP suppliers are exploring panel-based manufacturing instead of the current wafer-based approach. Since many more packages can fit on a large panel than on a wafer

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4

Johnson, Donald W., and Bin-Hong Tsai. "SUEX Laminates for Fan-In, Fan-Out and eWLB Development." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2011, DPC (2011): 000635–65. http://dx.doi.org/10.4071/2011dpc-ta31.

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The focus of this presentation is on the use of SUEX epoxy Thick Dry Film Sheets (TDFS) as a photoimagable dielectric layer in fan-in, fan-out and e-WLP applications. The sheets can be laminated over severe topography from under 2 μm to over 200 μm in height yielding void free coatings with 100% planarization over the entire substrate. The TDFS are available in a range of thicknesses and wafer or panel sizes. This new material is prepared under a highly controlled solvent-less process, which provides uniform coatings between two throw-away layers of protective polyester film. SUEX sheets of 10

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5

Schneider, M. L., and K. Segall. "Fan-out and fan-in properties of superconducting neuromorphic circuits." Journal of Applied Physics 128, no. 21 (2020): 214903. http://dx.doi.org/10.1063/5.0025168.

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6

Wang, Yu-ying, Qing-shan Li, Ping Chen, and Chun-de Ren. "Dynamic fan-in and fan-out metrics for program comprehension." Journal of Shanghai University (English Edition) 11, no. 5 (2007): 474–79. http://dx.doi.org/10.1007/s11741-007-0507-2.

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7

Asthana, Praveen, Gregory P. Nordin, Armand R. Tanguay, and B. Keith Jenkins. "Analysis of weighted fan-out/fan-in volume holographic optical interconnections." Applied Optics 32, no. 8 (1993): 1441. http://dx.doi.org/10.1364/ao.32.001441.

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8

Kuixian, CHEN, WANG Yu, HE Taotao, et al. "Metasurface fan-out diffractive optical elements." Journal of Applied Optics 40, no. 2 (2019): 119–25. http://dx.doi.org/10.5768/jao201940.0205001.

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9

Zwenger, Curtis, Ron Huemoeller, JinHan Kim, DongJean Kim, WonChul Do, and SeongMin Seo. "Silicon Wafer Integrated Fan-out Technology." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2015, DPC (2015): 000217–47. http://dx.doi.org/10.4071/2015dpc-ta22.

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The tremendous growth in the mobile handset, tablet, and networking markets has been fueled by consumer demand for increased mobility, functionality, and ease of use. This, in turn, has been driving an increase in functional convergence and 3D integration of IC devices, resulting in the need for more complex and sophisticated packaging techniques. A variety of advanced IC interconnect technologies are addressing this growing need. These include Thru Silicon Via (TSV), Chip-on Chip (CoC), and Package-on-Package (PoP) approaches. In particular, emerging Wafer Level Fan-Out (WLFO) technology prov

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10

Zwenger, Curtis, George Scott, Ron Huemoeller, WonChul Do, WonGeol Lee, and JiHun Yi. "Silicon Wafer Integrated Fan-out Technology." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2017, DPC (2017): 1–23. http://dx.doi.org/10.4071/2017dpc-tp2_presentation4.

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The tremendous growth in the mobile handset, tablet, and networking markets has been fueled by consumer demand for increased mobility, functionality, and ease of use. This, in turn, has been driving an increase in functional convergence and 3D integration of IC devices, resulting in the need for more complex and sophisticated packaging techniques. A variety of advanced IC interconnect technologies are addressing this growing need. These include Through Silicon Via (TSV), Chip-on Chip (CoC), and Package-on-Package (PoP) approaches. In particular, emerging Wafer Level Fan-Out (WLFO) technology p

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11

Kim, Kyung H., and Herbert M. Sauro. "Fan-out in gene regulatory networks." Journal of Biological Engineering 4, no. 1 (2010): 16. http://dx.doi.org/10.1186/1754-1611-4-16.

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12

Jan-Ming, Ho, and Ming-Tat Ko. "Bounded fan-out m-center problem." Information Processing Letters 63, no. 2 (1997): 103–8. http://dx.doi.org/10.1016/s0020-0190(97)00104-x.

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13

Hamam, Habib. "Array illuminator with arbitrary fan-out." Applied Optics 45, no. 25 (2006): 6525. http://dx.doi.org/10.1364/ao.45.006525.

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14

Hossack, W. J., P. McOwan, and R. E. Burge. "Computer generated optical fan-out element." Optics Communications 68, no. 2 (1988): 97–102. http://dx.doi.org/10.1016/0030-4018(88)90131-9.

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15

Aharonson, Eran, and Hagit Attiya. "Counting networks with arbitrary fan-out." Distributed Computing 8, no. 4 (1995): 163–69. http://dx.doi.org/10.1007/bf02242734.

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16

Murgia, Alessandro, Roberto Tonelli, Giulio Concas, Michele Marchesi, and Steve Counsell. "Parameter-based refactoring and the relationship with fan-in/fan-out coupling." Journal of Object Technology 11, no. 2 (2012): 7:1. http://dx.doi.org/10.5381/jot.2012.11.2.a7.

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17

Roy, S., U. Maulik, S. Bandyopadhyay, S. Basu, and B. K. Sikdar. "Fan-in- and fan-out-factor oriented BIST design for sequential machines." IEE Proceedings - Computers and Digital Techniques 150, no. 3 (2003): 183. http://dx.doi.org/10.1049/ip-cdt:20030421.

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18

Abe, Y., K. Shikama, H. Ono, S. Yanagi, and T. Takahashi. "Fan‐in/fan‐out device employing v‐groove substrate for multicore fibre." Electronics Letters 51, no. 17 (2015): 1347–48. http://dx.doi.org/10.1049/el.2015.1330.

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19

Azemar, Jerome. "Fan-Out Packaging: Technologies and market trends." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2017, DPC (2017): 1–35. http://dx.doi.org/10.4071/2017dpc-ta2_presentation1.

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The semiconductor industry is facing a new era in which device scaling and cost reduction will not continue on the path they followed for the past few decades, with Moore's law in its foundation. Advanced nodes do not bring the desired cost benefit anymore and R&D investments in new lithography solutions and devices below 10nm nodes are rising substantially. In order to answer market demands, the industry seeks further performance and functionality boosts in integration. While scaling options remain uncertain in the shorter term and continue to be investigated, the spotlight turns to advan

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20

Hunt, John. "Versatility of Fan Out – Simple 2D to Complex 3D." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2019, DPC (2019): 000165–94. http://dx.doi.org/10.4071/2380-4491-2019-dpc-presentation_ta2_034.

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Many mobile applications strive for the thinnest package possible, and therefore benefit from the high density of basic Fan Out technology. At the same time, Fan Out has evolved from a simple, single die packaging solution into a high-density solution enabling more complex 2D and 3D connectivity. Fan Out first went into volume manufacturing in 2009 with a simple, single die package using eWLB. For the next few years, it was only thought of in this context. Then in 2016, two packages came into production that broke this stereotype. The first was a hybrid, very high-density Fan Out combined with

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21

Mubarak, Asma, Steve Counsell, and Robert M. Hierons. "A Longitudinal Study of Fan-In and Fan-Out Coupling in Open-Source Systems." International Journal of Information System Modeling and Design 2, no. 4 (2011): 1–26. http://dx.doi.org/10.4018/jismd.2011100101.

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Excessive coupling between object-oriented classes is widely acknowledged as a maintenance problem that can result in a higher propensity for faults in systems and a ‘stored up’ future problem. This paper explores the relationship between ‘fan-in’ and ‘fan-out’ coupling metrics over multiple versions of open-source software. More specifically, the relationship between the two metrics is explored to determine patterns of growth in each over the course of time. The JHawk tool was used to extract the two metrics from five open-source systems. Results show a wide range of traits in the classes to

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22

Li, Ming, Qingqian Li, John Lau, et al. "Characterizations of Fan-out Wafer-Level Packaging." International Symposium on Microelectronics 2017, no. 1 (2017): 000557–62. http://dx.doi.org/10.4071/isom-2017-tha31_057.

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Abstract The calling for smaller form factor, higher I/O density, higher performance and lower cost has made fan-out wafer level packaging (FOWLP) technology the trend. Good control of die position accuracy and molded wafer warpage are some of the keys to achieve high-yield production for FOWLP. In this study, 10mm×10mm test chips were fabricated and attached (chip-first and die face-up) onto 12 inch glass wafer carriers using die-attach-film (DAF). These reconfigured wafers were compression-molded with selected epoxy molding compounds (EMC). Cu bumps (contact-pads) were revealed by grinding,

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23

Tooley, F. A. P. "Fan-out considerations of digital optical circuits." Applied Optics 26, no. 9 (1987): 1741. http://dx.doi.org/10.1364/ao.26.001741.

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24

Mahmoud, Abdulqader, Frederic Vanderveken, Christoph Adelmann, Florin Ciubotaru, Said Hamdioui, and Sorin Cotofana. "Fan-out enabled spin wave majority gate." AIP Advances 10, no. 3 (2020): 035119. http://dx.doi.org/10.1063/1.5134690.

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25

Tumbar, Remy, and David J. Brady. "Sampling field sensor with anisotropic fan-out." Applied Optics 41, no. 31 (2002): 6621. http://dx.doi.org/10.1364/ao.41.006621.

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26

VanderKlok, A., A. Stamm, and X. Xiao. "Fan-Blade-out Experiment at Small Scale." Experimental Techniques 40, no. 6 (2016): 1479–84. http://dx.doi.org/10.1007/s40799-016-0135-4.

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27

Daly, D., S. M. Hodson, and M. C. Hutley. "Fan-out gratings with a continuous profile." Optics Communications 82, no. 3-4 (1991): 183–87. http://dx.doi.org/10.1016/0030-4018(91)90441-f.

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28

Liebert, K., M. Rachon, A. Siemion, et al. "THz Beam Shaper Realizing Fan-Out Patterns." Journal of Infrared, Millimeter, and Terahertz Waves 38, no. 8 (2017): 1019–30. http://dx.doi.org/10.1007/s10762-017-0398-6.

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29

Takahashi, Yasuhiro, Seiichiro Tani, and Noboru Kunihiro. "Quantum addition circuits and unbounded fan-out." Quantum Information and Computation 10, no. 9&10 (2010): 872–90. http://dx.doi.org/10.26421/qic10.9-10-12.

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We first show how to construct an $O(n)$-depth $O(n)$-size quantum circuit for addition of two $n$-bit binary numbers with no ancillary qubits. The exact size is $7n-6$, which is smaller than that of any other quantum circuit ever constructed for addition with no ancillary qubits. Using the circuit, we then propose a method for constructing an $O(d(n))$-depth $O(n)$-size quantum circuit for addition with $O(n/d(n))$ ancillary qubits for any $d(n) = \Omega(\log n)$. If we are allowed to use unbounded fan-out gates with length $O(n^{\varepsilon})$ for an arbitrary small positive constant $\varep

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30

Lau, John, Ming Li, Yang Lei, et al. "Reliability of Fan-Out Wafer-Level Heterogeneous Integration." International Symposium on Microelectronics 2018, no. 1 (2018): 000224–32. http://dx.doi.org/10.4071/2380-4505-2018.1.000224.

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Abstract In this study, the reliability (thermal-cycling and shock) performances of a fan-out wafer-level system-in-package (SiP) or heterogeneous integration with one large chip (5mm×5mm), three small chips (3mm×3mm), and 4 capacitors (0402) embedded in an epoxy molding compound (EMC) package (10mm×10mm) with two RDLs (redistribution layers) are experimentally determined. Emphasis is placed on the estimation of the Weibull life distribution, characteristic life, and failure rate of the solder joint and RDL of this package. The fan-out wafer-level packaging (FOWLP) is assembled on a printed ci

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31

Lau, John, Ming Li, Yang Lei, et al. "Reliability of Fan-Out Wafer-Level Heterogeneous Integration." Journal of Microelectronics and Electronic Packaging 15, no. 4 (2018): 148–62. http://dx.doi.org/10.4071/imaps.728940.

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Abstract In this study, the reliability (thermal cycling and shock) performances of a fan-out wafer-level system-in-package (SiP) or heterogeneous integration with one large chip (5 × 5 mm), three small chips (3 ×3 mm), and four capacitors (0402) embedded in an epoxy molding compound package (10 × 10 mm) with two redistribution layers (RDLs) are experimentally determined. Emphasis is placed on the estimation of the Weibull life distribution, characteristic life, and failure rate of the solder joint and RDL of this package. The fan-out wafer-level packaging is assembled on a printed circuit boa

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32

Shih, Mengkai, Chih-Yi Huang, Tsan-Hsien Chen, Chen-Chao Wang, David Tarng, and C. P. Hung. "Electrical, Thermal, and Mechanical Characterization of eWLB, Fully Molded Fan-Out Package, and Fan-Out Chip Last Package." IEEE Transactions on Components, Packaging and Manufacturing Technology 9, no. 9 (2019): 1765–75. http://dx.doi.org/10.1109/tcpmt.2019.2935477.

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33

Ji, Lianhua, and V. P. Heuring. "Impact of gate fan-in and fan-out limits on optoelectronic digital circuits." Applied Optics 36, no. 17 (1997): 3927. http://dx.doi.org/10.1364/ao.36.003927.

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34

Ye, Feihong, Hirotaka Ono, Yoshiteru Abe, Makoto Yamada, and Toshio Morioka. "Novel Crosstalk Measurement Method for Multi-Core Fiber Fan-In/Fan-Out Devices." IEEE Photonics Technology Letters 28, no. 20 (2016): 2269–72. http://dx.doi.org/10.1109/lpt.2016.2591941.

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35

Watanabe, Tatsuhiko, and Yasuo Kokubun. "Stacked polymer waveguide type fan-in/fan-out device for dense multi-core fibre." IET Optoelectronics 9, no. 4 (2015): 158–62. http://dx.doi.org/10.1049/iet-opt.2014.0137.

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36

Shikama, Kota, Yoshiteru Abe, Toshiki Kishi, et al. "Multicore-Fiber Receptacle With Compact Fan-In/Fan-Out Device for SDM Transceiver Applications." Journal of Lightwave Technology 36, no. 24 (2018): 5815–22. http://dx.doi.org/10.1109/jlt.2018.2879100.

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37

Sayeed, Sk Yeahia Been, Daniel Wilding, Jose Solis Camara, Dieff Vital, Shubhendu Bhardwaj, and P. M. Raj. "Deformable Interconnects with Embedded Devices in Flexible Fan-Out Packages." International Symposium on Microelectronics 2019, no. 1 (2019): 000163–68. http://dx.doi.org/10.4071/2380-4505-2019.1.000163.

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Abstract A new class of interconnects that exhibit resilience to mechanical deformation are demonstrated with flexible fan-out or embedded-die packages. Active device embedding in flexible substrates is accomplished with direct printed interconnects onto die pads. Such a planar fan-out interconnect technology with a low-cost manufacturable process-flow results in the lowest electrical parasitics compared to flipchip with adhesives or printed-ramp interconnections with surface-assembled devices. The interconnects are made with conductive flexible silver-elastomer composites to sustain elastic d

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38

O'Toole, Eoin, Steffen Kroehnert, José Campos, Virgilio Barbosa, and Leonor Dias. "Package Thickness - Ultrathin WLFO (Wafer-Level Fan-Out)." International Symposium on Microelectronics 2016, no. 1 (2016): 000305–8. http://dx.doi.org/10.4071/isom-2016-wp31.

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Abstract NANIUM's Fan-Out Wafer-Level Packaging technology WLFO (Wafer-Level Fan-Out) is based on embedded Wafer-Level Ball Grid Array technology eWLB of Infineon Technologies [1]. Since it′s invention almost 10 years ago, it became the leading technology for Fan-Out Wafer-Level packages. The WLFO technology is based upon the reconstitution of KGD (known good die) from incoming device wafer, independent of wafer diameter and material, to recon wafer format of active semiconductor dies or other active/passive components separated by mold compound applied through compression molding on a tempora

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39

Byrne, Aidan J., and Samantha Fleming. "Sex Sells (Out): Neoliberalism and Erotic Fan Fiction." Journal of Popular Culture 51, no. 3 (2018): 693–715. http://dx.doi.org/10.1111/jpcu.12680.

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40

Xu, Cheng, Z. W. Zhong, and W. K. Choi. "Evaluation of fan-out wafer level package strength." Microelectronics International 36, no. 2 (2019): 54–61. http://dx.doi.org/10.1108/mi-06-2018-0040.

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Purpose The fan-out wafer level package (FOWLP) becomes more and more attractive and popular because of its flexibility to integrate diverse devices into a very small form factor. The strength of ultrathin FOWLP is low, and the low package strength often leads to crack issues. This paper aims to study the strength of thin FOWLP because the low package strength may lead to the reliability issue of package crack. Design/methodology/approach This paper uses the experimental method (three-point bending test) and finite element method (ANSYS simulation software) to evaluate the FOWLP strength. Two

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41

Lau, John H., Ming Li, Margie Li Qingqian, et al. "Fan-Out Wafer-Level Packaging for Heterogeneous Integration." IEEE Transactions on Components, Packaging and Manufacturing Technology 8, no. 9 (2018): 1544–60. http://dx.doi.org/10.1109/tcpmt.2018.2848649.

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42

Bonelli, Nicola, Fabio Del Vigna, Stefano Giordano, and Gregorio Procissi. "Packet Fan-Out Extension for the pcap Library." IEEE Transactions on Network and Service Management 15, no. 3 (2018): 976–90. http://dx.doi.org/10.1109/tnsm.2018.2828939.

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43

Weible, K. J., and H. P. Herzig. "Optical optimization of binary phase fan-out elements." Optics Communications 113, no. 1-3 (1994): 9–14. http://dx.doi.org/10.1016/0030-4018(94)90584-3.

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44

Lujan, Amy. "Cost Comparison of Fan-out Wafer Level Packaging and Flip Chip Packaging." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2017, DPC (2017): 1–37. http://dx.doi.org/10.4071/2017dpc-ta2_presentation3.

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In recent years, there has been increased focus on fan-out wafer level packaging with the growing inclusion of a variety of fan-out wafer level packages in mobile products. While fan-out wafer level packaging may be the right solution for many designs, it is not always the lowest cost solution. The right packaging choice is the packaging technology that meets design requirements at the lowest cost. Flip chip packaging, a more mature technology, continues to be an alternative to fan-out wafer level packaging. It is important for many in the electronic packaging industry to be able to determine

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45

Kelkar, Amit, Vivek Sridharan, Khanh Tran, et al. "Novel Mold-free Fan-out Wafer Level Package using Silicon Wafer." International Symposium on Microelectronics 2016, no. 1 (2016): 000410–14. http://dx.doi.org/10.4071/isom-2016-tha23.

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Abstract The ever increasing demand for high levels of integration and miniaturization has created new transistor nodes, shrunk redistribution line width/space, and driven a reduction in solder bump pitch. This has created the need for Fan-out packaging. This paper presents a novel Fan-out Wafer level package which does not require use of molding process or materials used typically in such packages. In this technique, silicon is used as the carrier material instead of molding compound. Advantages of silicon include good reliability, high thermal stability, and low cost. This novel Mold-free Fa

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46

Mahajan, A. L. "The ‘fingers fan out’ sign: stick out your palmaris longus even better!" British Journal of Plastic Surgery 58, no. 2 (2005): 278–79. http://dx.doi.org/10.1016/j.bjps.2004.09.001.

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47

Palesko, Alan, and Jan Vardaman. "Cost Comparison of Fan-Out WLP vs. Embedded Die." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2011, DPC (2011): 001003–18. http://dx.doi.org/10.4071/2011dpc-tp31.

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Fabricating the package after the die is placed can result in smaller form factors, increased performance, and improved supply chain logistics for OEMs. There are many different approaches for this packaging technique, but two of the most prominent are Fan-Out WLP and Embedded Die. Fan-Out WLP leverages existing semiconductor technology for a cost effective approach to achieve relatively tight package design rules. The Embedded Die strategy leverages existing PCB lamination technology for cost-reduction through scale: fabricating many small packages on large production panels. We will examine

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48

Fang, David, Michael Hsu, CC Chang, et al. "Fine line panel level fan out changes the SiP landscape." International Symposium on Microelectronics 2018, no. 1 (2018): 000349–54. http://dx.doi.org/10.4071/2380-4505-2018.1.000349.

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Abstract Moore's Law has been through many challenges in the last few years. The transistors continued to shrink to smaller sizes but the benefit of better performance and lower cost that comes along with shrinking is facing difficulties. Semiconductor industries are trying to come up with new ways to keep the Moore's Law going on two different fronts: where foundries are working on more Moore solutions and packaging houses are working on more than Moore solutions. Recently the industry has been considering the chip splitting and re-constitution in the form of SiP which has relatively shorter

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49

Plante, Courtney N., Stephen Reysen, Daniel Chadborn, Sharon E. Roberts, and Kathleen C. Gerbasi. "‘Get out of my fandom, newbie’: A cross-fandom study of elitism and gatekeeping in fans." Journal of Fandom Studies 8, no. 2 (2020): 123–46. http://dx.doi.org/10.1386/jfs_00013_1.

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In the present article we discuss three studies aimed at better understanding elitism in the context of fan groups. The studies assess different facets of elitism, predictors of elitism and the potential outcomes associated with holding elitist beliefs. The survey studies were conducted on members of three distinct fan groups: furries (fans of media featuring anthropomorphized animal characters), bronies (adult fans of the television series My Little Pony) and anime fans (fans of Japanese animation). Elitism was found to include both self-inflation and other-derogation and is predicted by two

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50

Azémar, Jérôme. "Fan-Out Wafer-Level-Packaging: Market and Technology Trends." International Symposium on Microelectronics 2016, no. 1 (2016): 000176–79. http://dx.doi.org/10.4071/isom-2016-wa31.

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Abstract The semiconductor industry is facing a new era in which device scaling and cost reduction will not continue on the path they followed for the past few decades, with Moore's law in its foundation. Advanced nodes do not bring the desired cost benefit anymore and R&D investments in new lithography solutions and devices below 10nm nodes are rising substantially. In order to answer market demands, the industry seeks further performance and functionality boosts in integration. While scaling options remain uncertain in the shorter term and continue to be investigated, the spotlight turns

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