Bibliografías temáticas / Floating point / Tesis
Siga este enlace para ver otros tipos de publicaciones sobre el tema: Floating point.

Tesis sobre el tema "Floating point"

Autor: Grafiati
Publicado: 4 de junio de 2021
Última modificación: 25 de julio de 2025

Crea una cita precisa en los estilos APA, MLA, Chicago, Harvard y otros

Elija tipo de fuente:

Consulte los 50 mejores tesis para su investigación sobre el tema "Floating point".

Junto a cada fuente en la lista de referencias hay un botón "Agregar a la bibliografía". Pulsa este botón, y generaremos automáticamente la referencia bibliográfica para la obra elegida en el estilo de cita que necesites: APA, MLA, Harvard, Vancouver, Chicago, etc.

También puede descargar el texto completo de la publicación académica en formato pdf y leer en línea su resumen siempre que esté disponible en los metadatos.

Explore tesis sobre una amplia variedad de disciplinas y organice su bibliografía correctamente.

1

Skogstrøm, Kristian. "Implementation of Floating-point Coprocessor." Thesis, Norwegian University of Science and Technology, Department of Computer and Information Science, 2005. http://urn.kb.se/resolve?urn=urn:nbn:no:ntnu:diva-9202.

Texto completo
Resumen
<p>This thesis presents the architecture and implementation of a high-performance floating-point coprocessor for Atmel's new microcontroller. The coprocessor architecture is based on a fused multiply-add pipeline developed in the specialization project, TDT4720. This pipeline has been optimized significantly and extended to support negation of all operands and single-precision input and output. New hardware has been designed for the decode/fetch unit, the register file, the compare/convert pipeline and the approximation tables. Division and square root is performed in software using Newton-Ra
Los estilos APA, Harvard, Vancouver, ISO, etc.
2

Zhang, Yiwei. "Biophysically accurate floating point neuroprocessors." Thesis, University of Bristol, 2011. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.544427.

Texto completo
Los estilos APA, Harvard, Vancouver, ISO, etc.
3

Baidas, Zaher Abdulkarim. "High-level floating-point synthesis." Thesis, University of Southampton, 2000. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.325049.

Texto completo
Los estilos APA, Harvard, Vancouver, ISO, etc.
4

Duracz, Jan Andrzej. "Verification of floating point programs." Thesis, Aston University, 2010. http://publications.aston.ac.uk/15778/.

Texto completo
Resumen
In this thesis we present an approach to automated verification of floating point programs. Existing techniques for automated generation of correctness theorems are extended to produce proof obligations for accuracy guarantees and absence of floating point exceptions. A prototype automated real number theorem prover is presented, demonstrating a novel application of function interval arithmetic in the context of subdivision-based numerical theorem proving. The prototype is tested on correctness theorems for two simple yet nontrivial programs, proving exception freedom and tight accuracy guaran
Los estilos APA, Harvard, Vancouver, ISO, etc.
5

Ross, Johan, and Hans Engström. "Voice Codec for Floating Point Processor." Thesis, Linköping University, Department of Electrical Engineering, 2008. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-15763.

Texto completo
Resumen
<p>As part of an ongoing project at the department of electrical engineering, ISY, at Linköping University, a voice decoder using floating point formats has been the focus of this master thesis. Previous work has been done developing an mp3-decoder using the floating point formats. All is expected to be implemented on a single DSP.The ever present desire to make things smaller, more efficient and less power consuming are the main reasons for this master thesis regarding the use of a floating point format instead of the traditional integer format in a GSM codec. The idea with the low precision
Los estilos APA, Harvard, Vancouver, ISO, etc.
6

Englund, Madeleine. "Hybrid Floating-point Units in FPGAs." Thesis, Linköpings universitet, Datorteknik, 2012. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-86587.

Texto completo
Resumen
Floating point numbers are used in many applications that  would be well suited to a higher parallelism than that offered in a CPU. In  these cases, an FPGA, with its ability to handle multiple calculations  simultaneously, could be the solution. Unfortunately, floating point  operations which are implemented in an FPGA is often resource intensive,  which means that many developers avoid floating point solutions in FPGAs or  using FPGAs for floating point applications. Here the potential to get less expensive floating point operations by using ahigher radix for the floating point numbers and u
Los estilos APA, Harvard, Vancouver, ISO, etc.
7

Xiao, Yancheng. "Two floating point LLL reduction algorithms." Thesis, McGill University, 2013. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=114503.

Texto completo
Resumen
The Lenstra, Lenstra and Lov\'sz (LLL) reduction is the most popular lattice reduction and is a powerful tool for solving many complex problems in mathematics and computer science. The blocking technique casts matrix algorithms in terms of matrix-matrix operations to permit efficient reuse of data in the algorithms. In this thesis, we use the blocking technique to develop two floating point block LLL reduction algorithms, the left-to-right block LLL (LRBLLL) reduction algorithm and the alternating partition block LLL (APBLLL) reduction algorithm, and give the complexity analysis of these two a
Los estilos APA, Harvard, Vancouver, ISO, etc.
8

Kupriianova, Olga. "Towards a modern floating-point environment." Thesis, Paris 6, 2015. http://www.theses.fr/2015PA066584/document.

Texto completo
Resumen
Cette thèse fait une étude sur deux moyens d'enrichir l'environnement flottant courant : le premier est d'obtenir plusieurs versions d'implantation pour chaque fonction mathématique, le deuxième est de fournir des opérations de la norme IEEE754, qui permettent de mélanger les entrées et la sortie dans les bases différentes. Comme la quantité de versions différentes pour chaque fonction mathématique est énorme, ce travail se concentre sur la génération du code. Notre générateur de code adresse une large variété de fonctions: il produit les implantations paramétrées pour les fonctions définies p
Los estilos APA, Harvard, Vancouver, ISO, etc.
9

Kupriianova, Olga. "Towards a modern floating-point environment." Electronic Thesis or Diss., Paris 6, 2015. http://www.theses.fr/2015PA066584.

Texto completo
Resumen
Cette thèse fait une étude sur deux moyens d'enrichir l'environnement flottant courant : le premier est d'obtenir plusieurs versions d'implantation pour chaque fonction mathématique, le deuxième est de fournir des opérations de la norme IEEE754, qui permettent de mélanger les entrées et la sortie dans les bases différentes. Comme la quantité de versions différentes pour chaque fonction mathématique est énorme, ce travail se concentre sur la génération du code. Notre générateur de code adresse une large variété de fonctions: il produit les implantations paramétrées pour les fonctions définies p
Los estilos APA, Harvard, Vancouver, ISO, etc.
10

Aamodt, Tor. "Floating-point to fixed-point compilation and embedded architectural support." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 2001. http://www.collectionscanada.ca/obj/s4/f2/dsk3/ftp04/MQ58787.pdf.

Texto completo
Los estilos APA, Harvard, Vancouver, ISO, etc.
11

Shen, Shumin. "A floating-point analog-to-digital converter." Thesis, University of Ottawa (Canada), 2004. http://hdl.handle.net/10393/26772.

Texto completo
Resumen
This thesis studies the floating-point analog-to-digital converter (FP-ADC). The first attempt is to analyze the parallel architecture of the floating-point converter, which is our research base. The characteristics and specifications of the floating-point AID converter are described. Simulations of the parallel architecture of the floating-point A/D converter were conceived, run and presented here to support the theoretically derived FP-ADC transfer characteristics. After analyzing the parallel architecture of the floating-point A/D converter, the following work is to provide a way of minimiz
Los estilos APA, Harvard, Vancouver, ISO, etc.
12

Panisset, Jean François. "A double precision floating point convolution processor /." Thesis, McGill University, 1994. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=68047.

Texto completo
Resumen
Two-dimensional convolution is one of the basic operations in image processing, where it is used as a filtering tool. A kernel of values corresponding to the spatial-domain impulse response of the filter is applied to the original image in order to perform desired operations such as low-pass filtering or edge enhancement.<br>Since convolution is basically a two-dimensional multiply and accumulate operation, it is computationally intensive. General-purpose computer architectures are often ill-suited to perform two-dimensional convolutions, since they lack the required processing speed or memory
Los estilos APA, Harvard, Vancouver, ISO, etc.
13

Zhang, Michael Ruogu 1977. "Software floating-point computation on parallel mahcines." Thesis, Massachusetts Institute of Technology, 1999. http://hdl.handle.net/1721.1/80133.

Texto completo
Resumen
Thesis (M.Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1999.<br>Includes bibliographical references (p. 71).<br>by Michael Ruogu Zhang.<br>M.Eng.
Los estilos APA, Harvard, Vancouver, ISO, etc.
14

Havermark, Joel. "Bit-Vector Approximations of Floating-Point Arithmetic." Thesis, Uppsala universitet, Institutionen för informationsteknologi, 2018. http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-372077.

Texto completo
Resumen
The use of floating-point numbers in safety-critical applications shows a need to efficiently and automatically reason about them. One approach is to use Satisfiability modulo theories (SMT). The naive approach to using SMT does not scale well. Previous work suggests approximations as a scalable solution. Zeljic, Backeman, Wintersteiger, and Rümmer have created a framework called UppSAT for iterative approximations. The approximations created with UppSAT use a precision to indicate how approximate the formula is. Floating-point can be approximated by the simpler fixed-point format. This provi
Los estilos APA, Harvard, Vancouver, ISO, etc.
15

Kolumban, Gaspar. "Low Cost Floating-Point Extensions to a Fixed-Point SIMD Datapath." Thesis, Linköpings universitet, Datorteknik, 2013. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-101586.

Texto completo
Resumen
The ePUMA architecture is a novel master-multi-SIMD DSP platform aimed at low-power computing, like for embedded or hand-held devices for example. It is both a configurable and scalable platform, designed for multimedia and communications. Numbers with both integer and fractional parts are often used in computers because many important algorithms make use of them, like signal and image processing for example. A good way of representing these types of numbers is with a floating-point representation. The ePUMA platform currently supports a fixed-point representation, so the goal of this thesis w
Los estilos APA, Harvard, Vancouver, ISO, etc.
16

Debski, Michal. "Self-calibrating floating-point analog-to-digital converter." Thesis, University of Ottawa (Canada), 2005. http://hdl.handle.net/10393/26884.

Texto completo
Resumen
The Floating-Point Analog-to-Digital Converter (FPADC) is an extended version of the Fixed-Point ADC. It is designed to deal with a broader dynamic range of signals while exhibiting a smaller relative quantization error. The traditional implementation of the FPADC is characterized by a high relative precision, but it requires high-precision high-speed components in order to achieve that. The high precision of the high-speed components comes at a greater cost. This constraint limits the availability of FPADCs to high-priced designs. The thesis addresses a low-speed and a low-cost calibration ap
Los estilos APA, Harvard, Vancouver, ISO, etc.
17

Pillai, Rajan V. K. "On low power floating point data path architectures." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 2000. http://www.collectionscanada.ca/obj/s4/f2/dsk1/tape4/PQDD_0021/NQ47712.pdf.

Texto completo
Los estilos APA, Harvard, Vancouver, ISO, etc.
18

Shah, Syed Yawar Ali. "On synthesis and optimization of floating point units." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 2001. http://www.collectionscanada.ca/obj/s4/f2/dsk3/ftp04/MQ59309.pdf.

Texto completo
Los estilos APA, Harvard, Vancouver, ISO, etc.
19

Drolet, Jean. "The design of a floating-point convolution system /." Thesis, McGill University, 1992. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=56813.

Texto completo
Resumen
Convolution is the basic operation behind many image processing algorithms. However, it is a computationally intensive operation. Dedicated hardware exists to implement the fixed-point version of this operation. But recent developments such as laser range data processing now require floating-point arithmetic which is often performed by software.<br>This thesis presents the design of a specialized convolution processor that operates on double precision floating-point data. This convolver is based on an array of systolic cells and may be configured to process both images and unidimensional signa
Los estilos APA, Harvard, Vancouver, ISO, etc.
20

Jain, Sheetal A. 1980. "Low-power single-precision IEEE Floating-point unit." Thesis, Massachusetts Institute of Technology, 2003. http://hdl.handle.net/1721.1/87426.

Texto completo
Los estilos APA, Harvard, Vancouver, ISO, etc.
21

Hellman, Noah. "Mitchell-Based Approximate Operations on Floating-Point Numbers." Thesis, Linköpings universitet, Datorteknik, 2021. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-178882.

Texto completo
Resumen
By adapting Mitchell's algorithm for floating-point numbers, one can efficiently perform arithmetic floating-point operations in an approximate logarithmic domain in order to perform approximate computations of functions such as multiplication, division, square root and others. This work examines how this algorithm can be improved in terms of accuracy and hardware complexity by applying a set of various methods that are parametrized and offer a large design space. Optimal coefficients for a large portion of this space is determined and used to synthesize circuits for both ASIC and FPGA circuit
Los estilos APA, Harvard, Vancouver, ISO, etc.
22

Mishra, Biswajit. "Investigation into a Floating Point Geometric Algebra Processor." Thesis, University of Southampton, 2007. https://eprints.soton.ac.uk/266009/.

Texto completo
Resumen
The widespread use of Computer Graphics and Computer Vision applications has led to a plethora of hardware implementations that are usually expressed using linear algebraic methods. There are two drawbacks with this approach that are posing fundamental challenges to engineers developing hardware and software applications in this area. The first is the complexity and size of the hardware blocks required to practically realize such applications – particularly multiplication, addition and accumulation operations. Whether the platform is Field Programmable Gate Arrays (FPGA) or Application Specifi
Los estilos APA, Harvard, Vancouver, ISO, etc.
23

Raina, Saurabh-Kumar. "FLIP, a floating-point library for integer processors." Lyon, École normale supérieure (sciences), 2006. http://www.theses.fr/2006ENSL0369.

Texto completo
Los estilos APA, Harvard, Vancouver, ISO, etc.
24

Collingbourne, Peter Cyrus. "Symbolic crosschecking of data-parallel floating point code." Thesis, Imperial College London, 2013. http://hdl.handle.net/10044/1/10936.

Texto completo
Resumen
In this thesis we present a symbolic execution-based technique for cross-checking programs accelerated using SIMD or OpenCL against an unaccelerated version, as well as a technique for detecting data races in OpenCL programs. Our techniques are implemented in KLEE-CL, a symbolic execution engine based on KLEE that supports symbolic reasoning on the equivalence between expressions involving both integer and floating-point operations. While the current generation of constraint solvers provide good support for integer arithmetic, there is little support available for floating-point arithmetic, du
Los estilos APA, Harvard, Vancouver, ISO, etc.
25

Brown, Ashley W. "Profile-directed specialisation of custom floating-point hardware." Thesis, Imperial College London, 2010. http://hdl.handle.net/10044/1/5604.

Texto completo
Resumen
We present a methodology for generating floating-point arithmetic hardware designs which are, for suitable applications, much reduced in size, while still retaining performance and IEEE-754 compliance. Our system uses three key parts: a profiling tool, a set of customisable floating-point units and a selection of system integration methods. We use a profiling tool for floating-point behaviour to identify arithmetic operations where fundamental elements of IEEE-754 floating-point may be compromised, without generating erroneous results in the common case. In the uncommon case, we use simple det
Los estilos APA, Harvard, Vancouver, ISO, etc.
26

DeLorimier, Michael DeHon André. "Floating-point sparse matrix-vector multiply for FPGAs /." Diss., Pasadena, Calif. : California Institute of Technology, 2005. http://resolver.caltech.edu/CaltechETD:etd-05132005-144347.

Texto completo
Los estilos APA, Harvard, Vancouver, ISO, etc.
27

McCleeary, Ryan. "Lazy exact real arithmetic using floating point operations." Diss., University of Iowa, 2019. https://ir.uiowa.edu/etd/6991.

Texto completo
Resumen
Exact real arithmetic systems can specify any amount of precision on the output of the computations. They are used in a wide variety of applications when a high degree of precision is necessary. Some of these applications include: differential equation solvers, linear equation solvers, large scale mathematical models, and SMT solvers. This dissertation proposes a new exact real arithmetic system which uses lazy list of floating point numbers to represent the real numbers. It proposes algorithms for basic arithmetic computations on these structures and proves their correctness. This proposed sy
Los estilos APA, Harvard, Vancouver, ISO, etc.
28

De, Blasio Simone, and Karpers Fredrik Ekstedt. "Comparing the precision in matrix multiplication between Posits and IEEE 754 floating-points : Assessing precision improvement with emerging floating-point formats." Thesis, KTH, Skolan för elektroteknik och datavetenskap (EECS), 2020. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-280036.

Texto completo
Resumen
IEEE 754 floating-points are the current standard way to represent real values in computers, but there are alternative formats emerging. One of these emerging formats are Posits. The main characteristic of Posit is that the format allows for higher precision than IEEE 754 floats of the same bit size for numbers of magnitude close to 1, but lower precision for numbers of much smaller or bigger magnitude. This study compared the precision between IEEE 754 floating-point and Posit when it comes to matrix multiplication. Different sizes of matrices are compared, combined with different intervals w
Los estilos APA, Harvard, Vancouver, ISO, etc.
29

Robe, Edward D. "SIMULINK modules that emulate digital controllers realized with fixed-point or floating-point arithmetic." Ohio : Ohio University, 1994. http://www.ohiolink.edu/etd/view.cgi?ohiou1180120138.

Texto completo
Los estilos APA, Harvard, Vancouver, ISO, etc.
30

Catanzaro, Bryan C. "Higher radix floating-point representations for FPGA-based arithmetic /." Diss., CLICK HERE for online access, 2005. http://contentdm.lib.byu.edu/ETD/image/etd808.pdf.

Texto completo
Los estilos APA, Harvard, Vancouver, ISO, etc.
31

Dahlberg, Anders. "Evaluation of a Floating Point Acoustic Echo Canceller Implementation." Thesis, Linköping University, Department of Electrical Engineering, 2007. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-8938.

Texto completo
Resumen
<p>This master thesis consists of implementation and evaluation of an AEC, Acoustic Echo Canceller, algorithm in a floating-point architecture. The most important question this thesis will try to answer is to determine benefits or drawbacks of using a floating-point architecture, relative a fixed-point architecture, to do AEC. In a telephony system there is two common forms of echo, line echo and acoustic echo. Acoustic echo is introduced by sound emanating from a loudspeaker, e.g. in a handsfree or speakerphone, being picked up by a microphone and then sent back to the source. The problem wit
Los estilos APA, Harvard, Vancouver, ISO, etc.
32

Costello, Joseph Patrick. "Behavioural synthesis of low-power floating point CORDIC processors." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 2000. http://www.collectionscanada.ca/obj/s4/f2/dsk1/tape4/PQDD_0032/MQ65854.pdf.

Texto completo
Los estilos APA, Harvard, Vancouver, ISO, etc.
33

Lyu, Chung-nan. "Pipelined floating point divider with built-in testing circuits." Ohio : Ohio University, 1988. http://www.ohiolink.edu/etd/view.cgi?ohiou1182864748.

Texto completo
Los estilos APA, Harvard, Vancouver, ISO, etc.
34

Côté, Jean-François 1966. "The design of a testable floating point convolution processor /." Thesis, McGill University, 1990. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=60002.

Texto completo
Resumen
This thesis describes the design of a pipeline architecture double precision floating point systolic cell for convolution. The arithmetic operations are distributed into three pipeline stages, enabling the cell to process each set of operands within 16 clock cycles. While offering the same precision obtained on a standard computers, the systolic cell reduces the convolution time expenditure by as much as three orders of magnitude.
Los estilos APA, Harvard, Vancouver, ISO, etc.
35

Hok, Ho Chun. "Customisable and reconfigurable platform for optimising floating point computations." Thesis, Imperial College London, 2010. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.509798.

Texto completo
Los estilos APA, Harvard, Vancouver, ISO, etc.
36

Liew, Daniel Simon. "Symbolic execution of verification languages and floating-point code." Thesis, Imperial College London, 2017. http://hdl.handle.net/10044/1/59705.

Texto completo
Resumen
The focus of this thesis is a program analysis technique named symbolic execution. We present three main contributions to this field. First, an investigation into comparing several state-of-the-art program analysis tools at the level of an intermediate verification language over a large set of benchmarks, and improvements to the state-of-the-art of symbolic execution for this language. This is explored via a new tool, Symbooglix, that operates on the Boogie intermediate verification language. Second, an investigation into performing symbolic execution of floating-point programs via a standardi
Los estilos APA, Harvard, Vancouver, ISO, etc.
37

Wittman, Susan Jean. "Servo compensation using a floating point digital signal processor." Thesis, Massachusetts Institute of Technology, 1989. http://hdl.handle.net/1721.1/39018.

Texto completo
Los estilos APA, Harvard, Vancouver, ISO, etc.
38

Lyu, Chuang-nan. "Pipelined floating point divider with built-in testing circuits." Ohio University / OhioLINK, 1988. http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1182864748.

Texto completo
Los estilos APA, Harvard, Vancouver, ISO, etc.
39

Ratan, Amrita. "Hardware Modules for Safe Integer and Floating-Point Arithmetic." University of Cincinnati / OhioLINK, 2013. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1383812316.

Texto completo
Los estilos APA, Harvard, Vancouver, ISO, etc.
40

Lugo, Martinez Jose E. "Strategies for sharing a floating point unit between SPEs." Diss., [La Jolla] : University of California, San Diego, 2010. http://wwwlib.umi.com/cr/ucsd/fullcit?p1470744.

Texto completo
Resumen
Thesis (M.S.)--University of California, San Diego, 2010.<br>Title from first page of PDF file (viewed February 17, 2010). Available via ProQuest Digital Dissertations. Includes bibliographical references (p. 55-57).
Los estilos APA, Harvard, Vancouver, ISO, etc.
41

Costello, Joseph Patrick. "Behavioural synthesis of low-power floating point CORDIC processors." Ottawa : National Library of Canada = Bibliothèque nationale du Canada, 2002. http://www.nlc-bnc.ca/obj/s4/f2/dsk1/tape4/PQDD%5F0032/MQ65854.pdf.

Texto completo
Los estilos APA, Harvard, Vancouver, ISO, etc.
42

Catanzaro, Bryan Christopher. "Higher Radix Floating-Point Representations for FPGA-Based Arithmetic." BYU ScholarsArchive, 2005. https://scholarsarchive.byu.edu/etd/311.

Texto completo
Resumen
Field Programmable Gate Arrays (FPGAs) are increasingly being used for high-throughput floating-point computation. It is forecasted that by 2009, FPGAs will provide an order of magnitude greater sustained floating-point throughput than conventional processors. FPGA implementations of floating-point operators have historically been designed to use binary floating-point representations, as do general purpose processors. Binary representations were chosen as the standard over three decades ago because they provide maximal numerical accuracy per bit of floating-point data. However, the unique natu
Los estilos APA, Harvard, Vancouver, ISO, etc.
43

Coors, Martin. "A floating-point to fixed-point design flow for high performance digital signal processors /." Aachen : Shaker, 2005. http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&doc_number=013834304&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA.

Texto completo
Los estilos APA, Harvard, Vancouver, ISO, etc.
44

Stenersen, Espen. "Vectorized 128-bit Input FP16/FP32/FP64 Floating-Point Multiplier." Thesis, Norwegian University of Science and Technology, Department of Electronics and Telecommunications, 2008. http://urn.kb.se/resolve?urn=urn:nbn:no:ntnu:diva-8876.

Texto completo
Resumen
<p>3D graphic accelerators are often limited by their floating-point performance. A Graphic Processing Unit (GPU) has several specialized floating-point units to achieve high throughput and performance. The floating-point units consume a large part of total area, and power consumption, and hence architectural choices are important to evaluate when implementing the design. GPUs are specially tuned for performing a set of operations on large sets of data. The task of a 3D graphic solution is to render a image or a scene. The scene contains geometric primitives as well as descriptions of the ligh
Los estilos APA, Harvard, Vancouver, ISO, etc.
45

Lu, Chung-Kuei. "A design of floating point FFT using Genesil Silicon Compiler." Thesis, Monterey, California. Naval Postgraduate School, 1991. http://hdl.handle.net/10945/30956.

Texto completo
Resumen
The hardware of floating-point MULTIPLY, ADD, and SUBTRACT units are designed to support the multiplication, addition, and subtraction operation necessary in the Fast Fourier Transform (FFT). In this thesis, the IEEE floating-point standard is adopted and scaled down to 16 bits, but the exponent is an excess-8 number represented using radix-2. A 16 bit reduced word size floating-point arithematic unit for high speed signal analysis was implemented. The layout verification, functional simulation, and timing analysis of these units have been performed on the Genesil Silicon Compiler (GSC) system
Los estilos APA, Harvard, Vancouver, ISO, etc.
46

Dutta, Sumit Ph D. Massachusetts Institute of Technology. "Floating-point unit (FPU) designs with nano-electromechanical (NEM) relays." Thesis, Massachusetts Institute of Technology, 2013. http://hdl.handle.net/1721.1/84724.

Texto completo
Resumen
Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2013.<br>This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.<br>Includes bibliographical references (pages 71-74).<br>Nano-electromechanical (NEM) relays are an alternative to CMOS transistors as the fabric of digital circuits. Circuits with NEM relays offer energy-efficiency benefits over CMOS since they have zero leakage power and are strategically designed to maintain throughput that is comp
Los estilos APA, Harvard, Vancouver, ISO, etc.
47

Peterson, Scott Thomas. "Experimental response and analysis of the Evergreen Point Floating Bridge." Connect to this title online, 2002. http://www.dissertations.wsu.edu/dissertations/Fall2002/s%5Fpeterson%5F102102.pdf.

Texto completo
Los estilos APA, Harvard, Vancouver, ISO, etc.
48

Plet, Antoine. "Contribution to error analysis of algorithms in floating-point arithmetic." Thesis, Lyon, 2017. http://www.theses.fr/2017LYSEN038/document.

Texto completo
Resumen
L’arithmétique virgule flottante est une approximation de l’arithmétique réelle dans laquelle chaque opération peut introduire une erreur. La norme IEEE 754 requiert que les opérations élémentaires soient aussi précises que possible, mais au cours d’un calcul, les erreurs d’arrondi s’accumulent et peuvent conduire à des résultats totalement faussés. Cela arrive avec une expression aussi simple que ab + cd, pour laquelle l’algorithme naïf retourne parfois un résultat aberrant, avec une erreur relative largement supérieure à 1. Il est donc important d’analyser les algorithmes utilisés pour contr
Los estilos APA, Harvard, Vancouver, ISO, etc.
49

El, Moussawi Ali Hassan. "SIMD-aware word length optimization for floating-point to fixed-point conversion targeting embedded processors." Thesis, Rennes 1, 2016. http://www.theses.fr/2016REN1S150/document.

Texto completo
Resumen
Afin de limiter leur coût et/ou leur consommation électrique, certains processeurs embarqués sacrifient le support matériel de l'arithmétique à virgule flottante. Pourtant, pour des raisons de simplicité, les applications sont généralement spécifiées en utilisant l'arithmétique à virgule flottante. Porter ces applications sur des processeurs embarqués de ce genre nécessite une émulation logicielle de l'arithmétique à virgule flottante, qui peut sévèrement dégrader la performance. Pour éviter cela, l'application est converti pour utiliser l'arithmétique à virgule fixe, qui a l'avantage d'être p
Los estilos APA, Harvard, Vancouver, ISO, etc.
50

Coors, Martin [Verfasser]. "A Floating-Point to Fixed-Point Design Flow for High Performance Digital Signal Processors / Martin Coors." Aachen : Shaker, 2005. http://d-nb.info/1181610834/34.

Texto completo
Los estilos APA, Harvard, Vancouver, ISO, etc.
También puede estar interesado en las bibliografías sobre el tema "Floating point" para otros tipos de fuentes:
Artículos de revistas Libros
Ofrecemos descuentos en todos los planes premium para autores cuyas obras están incluidas en selecciones literarias temáticas. ¡Contáctenos para obtener un código promocional único!

Pasar a la bibliografía