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Artículos de revistas sobre el tema "FPGA - System-on-Chip"

Autor: Grafiati

Publicado: 4 de junio de 2021

Última modificación: 1 de febrero de 2022

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1

SUNITHA A, SUNITHA A. y RAGHU MC RAGHU MC. "Implementation of Can Bus Based System -on-Chip on Altera FPGA". International Journal of Scientific Research 3, n.º 5 (1 de junio de 2012): 268–70. http://dx.doi.org/10.15373/22778179/may2014/82.

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2

Baans, Omar Salem y Asral Bahari Jambek. "Implementation of an ARM-based system using a Xilinx ZYNQ SoC". Indonesian Journal of Electrical Engineering and Computer Science 13, n.º 2 (1 de febrero de 2019): 485. http://dx.doi.org/10.11591/ijeecs.v13.i2.pp485-491.

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<span>ARM processors are widely used in embedded systems. They are often implemented as microcontrollers, field-programmable gate arrays (FPGAs) or systems-on-chip. In this paper, a variety of ARM processor platform implementations are reviewed, such as implementation into a microcontroller, a system-on-chip and a hybrid ARM-FPGA platform. Furthermore, the implementation of a specific ARM processor, the Cortex-A9 processor, into a system-on-chip (SoC) on an FPGA is discussed using Xilinx’s Vivado and SDK software system and execution on a Xilinx Zynq Board.</span>

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3

Samsonov, Alexander N. y Khristina V. Samoilova. "High speed video recording system on a chip for detonation jet engine testing". MATEC Web of Conferences 158 (2018): 01028. http://dx.doi.org/10.1051/matecconf/201815801028.

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This article describes system on a chip development for high speed video recording purposes. Current research was started due to difficulties in selection of FPGAs and CPUs which include wide bandwidth, high speed and high number of multipliers for real time signal analysis implementation. Current trend of high density silicon device integration will result soon in a hybrid sensor-controller-memory circuit packed in a single chip. This research was the first step in a series of experiments in manufacturing of hybrid devices. The current task is high level syntheses of high speed logic and CPU core in an FPGA. The work resulted in FPGA-based prototype implementation and examination.

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4

Baklouti, M., Ph Marquet, J. L. Dekeyser y M. Abid. "FPGA-based many-core System-on-Chip design". Microprocessors and Microsystems 39, n.º 4-5 (junio de 2015): 302–12. http://dx.doi.org/10.1016/j.micpro.2015.03.007.

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5

Yu, Bing, Tian Hong Zhang y Dong Dong Liu. "Low Cost AFDX End System Based on System on a Programmable Chip". Applied Mechanics and Materials 29-32 (agosto de 2010): 2308–11. http://dx.doi.org/10.4028/www.scientific.net/amm.29-32.2308.

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AFDX (Avionics Full DupleX Switched Ethernet, ARINC 664) utilized in Airbus A380 and Boeing 787 represents a major upgrade in both bandwidth and capability; however some legacy systems are difficult to connect into the AFDX bus smoothly. A low cost AFDX end system based on SOPC (System On a Programmable Chip) is presented. A Xilinx Spartan 3AN FPGA is employed to build the whole system; and then a dedicated reduced Ethernet MAC controller for AFDX end system is designed; a MC8051 open core microcontroller is employed as the system controller and protocol processing unit. The whole design costs small FPGA resources and the experiments show that the designed AFDX end system works robustly and correctly.

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6

Zhu, Jun Chao, Yong Chen Li, Ying Kui Jiao y Zhi Jun Ma. "Image Acquisition System Design of Camera Based on FPGA". Applied Mechanics and Materials 668-669 (octubre de 2014): 836–39. http://dx.doi.org/10.4028/www.scientific.net/amm.668-669.836.

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It designs an image acquisition system of the camera based on FPGA. It uses a CMOS image sensor as the sensitive chip and controls the timing of image collection by designing the FPGA. FPGA transfers captured image into a PC to display. It uses the I2C bus to initiate CMOS sensor. A problem of cross-clock is solved by asynchronous FIFO. By the ping-pong operation based on two SDRAM chips to solve the problem of high speed data cache. The FPGA chip communicates signal data with PC by Ethernet port. The experiment proved that the system is able to collect 2048×1536 resolution images in a speed of 12fps.

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7

Liu, Wen Qiang. "Design of Fiber Data Transmission System Based on FPGA". Applied Mechanics and Materials 687-691 (noviembre de 2014): 3207–11. http://dx.doi.org/10.4028/www.scientific.net/amm.687-691.3207.

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Optical fiber data transmission system has advantages of long-distance transmission, low error rate, high speed data transmission, using FPGA chip NIOSII embedded processor and on chip peripheral constitute the core components, without changing the basic framework of the system, can be upgraded and functional changes to the FPGA internal hardware and software, improved design flexibility, reduced the development cost.

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8

Xu, Yubao. "FPGA Alarm System Based on Multi Temperature Sensor". International Journal of Online Engineering (iJOE) 13, n.º 05 (14 de mayo de 2017): 109. http://dx.doi.org/10.3991/ijoe.v13i05.7053.

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The purpose of this study is to achieve real-time acquisition and monitoring of temperature in large-scale industrial or agricultural production scene, and timely detect abnormal temperature. FPGA chip, multi temperature sensor and alarm control module three parts consist of FPGA alarm system obtained based on multi temperature sensor. Multi temperature sensor is used for the acquisition of relevant temperature signal in the production site, and the transmission of the collected data through the way of digital signal chip to the FPGA chip for further processing. The FPGA chip is responsible for the parameter setting, the temperature signal acquisition and the threshold comparison and so on, and according to the data processing result, it can send out the normal response control signal to the alarm module. The alarm module contains the pre-warning lights and the alarm device that it can receive the control signal and realize alarm response. The results showed that the test in planting flowers in greenhouse showed that the system is sensitive in response and small in error of temperature acquisition, in accordance with the requirements for use. As a result, the system can be widely used in the temperature monitoring in the production scene, suitable for being promoted in a variety of occasions needing for monitoring the temperature.

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9

Shimizu, Kenta. "FPGA AND SYSTEM ON CHIP EDUCATION FOR EMBEDDED ENGINEER". International Journal of E-Learning and Educational Technologies in the Digital Media 1, n.º 2 (2015): 68–80. http://dx.doi.org/10.17781/p001557.

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10

Nascimento, Jose M. P., Mario P. Vestias y Gabriel Martin. "Hyperspectral Compressive Sensing With a System-On-Chip FPGA". IEEE Journal of Selected Topics in Applied Earth Observations and Remote Sensing 13 (2020): 3701–10. http://dx.doi.org/10.1109/jstars.2020.2996679.

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11

Dorothy, R. y Sasilatha T. "System on Chip Based RTC in Power Electronics". Bulletin of Electrical Engineering and Informatics 6, n.º 4 (1 de diciembre de 2017): 358–63. http://dx.doi.org/10.11591/eei.v6i4.867.

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Current control systems and emulation systems (Hardware-in-the-Loop, HIL or Processor-in-the-Loop, PIL) for high-end power-electronic applications often consist of numerous components and interlinking busses: a micro controller for communication and high level control, a DSP for real-time control, an FPGA section for fast parallel actions and data acquisition, multiport RAM structures or bus systems as interconnecting structure. System-on-Chip (SoC) combines many of these functions on a single die. This gives the advantage of space reduction combined with cost reduction and very fast internal communication. Such systems become very relevant for research and also for industrial applications. The SoC used here as an example combines a Dual-Core ARM 9 hard processor system (HPS) and an FPGA, including fast interlinks between these components. SoC systems require careful software and firmware concepts to provide real-time control and emulation capability. This paper demonstrates an optimal way to use the resources of the SoC and discusses challenges caused by the internal structure of SoC. The key idea is to use asymmetric multiprocessing: One core uses a bare-metal operating system for hard real time. The other core runs a “real-time” Linux for service functions and communication. The FPGA is used for flexible process-oriented interfaces (A/D, D/A, switching signals), quasi-hard-wired protection and the precise timing of the real-time control cycle. This way of implementation is generally known and sometimes even suggested–but to the knowledge of the author’s seldomly implemented and documented in the context of demanding real-time control or emulation. The paper details the way of implementation, including process interfaces, and discusses the advantages and disadvantages of the chosen concept. Measurement results demonstrate the properties of the solution.

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12

Jumaa, Noor. "Survey: Internet of Thing Using FPGA". Iraqi Journal for Electrical and Electronic Engineering 13, n.º 1 (1 de junio de 2017): 38–45. http://dx.doi.org/10.37917/ijeee.13.1.5.

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Everything in its way to be computerized and most of the objects are coming to be smart in present days. Modern Internet of Thing (IoT) allows these objects to be on the network by using IoT platforms. IoT is a smart information society that consists of smart devices; these devices can communicate with each other without human's intervention. IoT systems require flexible platforms. Through the use of Field Programmable Gate Array (FPGA), IoT devices can interface with the outside world easily with low power consumption, low latency, and best determinism. FPGAs provide System on Chip (SoC) technique due to FPGAs scalability which enables the designer to implement and integrate large number of hardware clocks at single chip. FPGA can be deemed as a special purpose reprogrammable processor since it can process signals at its input pins, manipulate them, and give off signals on the output pins. In this paper, using FPGA for IoT is the limelight.

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13

Jumaa, Noor. "Survey: Internet of Thing Using FPGA". Iraqi Journal for Electrical and Electronic Engineering 13, n.º 1 (1 de junio de 2017): 38–45. http://dx.doi.org/10.37917/ijeee.13.5.

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Everything in its way to be computerized and most of the objects are coming to be smart in present days. Modern Internet of Thing (IoT) allows these objects to be on the network by using IoT platforms. IoT is a smart information society that consists of smart devices; these devices can communicate with each other without human's intervention. IoT systems require flexible platforms. Through the use of Field Programmable Gate Array (FPGA), IoT devices can interface with the outside world easily with low power consumption, low latency, and best determinism. FPGAs provide System on Chip (SoC) technique due to FPGAs scalability which enables the designer to implement and integrate large number of hardware clocks at single chip. FPGA can be deemed as a special purpose reprogrammable processor since it can process signals at its input pins, manipulate them, and give off signals on the output pins. In this paper, using FPGA for IoT is the limelight.

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14

Zhu, Dan Dan y Hong Wen Li. "Design of Control System of DC Motor Based on Fusion FPGA". Advanced Materials Research 328-330 (septiembre de 2011): 2185–89. http://dx.doi.org/10.4028/www.scientific.net/amr.328-330.2185.

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Along with the development of microelectronic process, it is possible to integrate a big system in one chip. A new way to implement system on a chip is provided by the advent of FPGA. Based on Verilog HDL and the Actel Fusion AFS600 FPGA chip, the speed closed-loop control system of DC motor was designed by using options of combining the top-down thinking and the bottom-up method. PID control algorithm, encoder signal processing and PWM waveform generation etc were realized by the system. The results show that the system structure is simplified and the stability and reliability are improved. A solution of system on a chip is realized to some extent. It has extensive application value in engineering practice.

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15

Li, Shuai, Kuangyuan Sun, Yukui Luo, Nandakishor Yadav y Ken Choi. "Novel CNN-Based AP2D-Net Accelerator: An Area and Power Efficient Solution for Real-Time Applications on Mobile FPGA". Electronics 9, n.º 5 (18 de mayo de 2020): 832. http://dx.doi.org/10.3390/electronics9050832.

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Standard convolutional neural networks (CNNs) have large amounts of data redundancy, and the same accuracy can be obtained even in lower bit weights instead of floating-point representation. Most CNNs have to be developed and executed on high-end GPU-based workstations, for which it is hard to transplant the existing implementations onto portable edge FPGAs because of the limitation of on-chip block memory storage size and battery capacity. In this paper, we present adaptive pointwise convolution and 2D convolution joint network (AP2D-Net), an ultra-low power and relatively high throughput system combined with dynamic precision weights and activation. Our system has high performance, and we make a trade-off between accuracy and power efficiency by adopting unmanned aerial vehicle (UAV) object detection scenarios. We evaluate our system on the Zynq UltraScale+ MPSoC Ultra96 mobile FPGA platform. The target board can get the real-time speed of 30 fps under 5.6 W, and the FPGA on-chip power is only 0.6 W. The power efficiency of our system is 2.8× better than the best system design on a Jetson TX2 GPU and 1.9× better than the design on a PYNQ-Z1 SoC FPGA.

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16

Hu, Peng Fei, Yu Xiang Yuan, Zhi Juan Qu y Xue Ping Jiang. "System on Chip Design for Multi-Principle of Relay Protection in the FPGA". Applied Mechanics and Materials 668-669 (octubre de 2014): 857–61. http://dx.doi.org/10.4028/www.scientific.net/amm.668-669.857.

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To improve the reliability and integration of relay protection devices in power, the system on chip design for multi-principle of relay protection on FPGA is proposed. The data acquisition, digital signal processing, hardware protection algorithm, FPGA and MCU process scheduling, MCU and peripheral devices communication are designed, the hardware compilation model is set up by QuartusII on FPGA, and the simulation and experimental verification are performed. The results show that the proposed system can improve the speed of hardware protection and reduce the volume of the device, and has reconstruction on architecture.

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17

Han, Xi, Zhe Ying Li, Yuan Sheng Liu y Wen Liang Niu. "Design of SoC Verification System Based on Multi-FPGA". Advanced Materials Research 532-533 (junio de 2012): 1110–14. http://dx.doi.org/10.4028/www.scientific.net/amr.532-533.1110.

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As one of the most advanced research field, the problem of SoC (System on a Chip) design is getting more and more attention. With the promotion of its theory and technique, SoC verification turns to one of the most significant part in the procedure of realizing a usable integrated circuit. And verification using FPGA (Field Programmable Gate Array) which must obey a set of strict technological process is a kind of general way. With the growing complexity and integrated scale of SoC design, a single FPGA chip could hardly satisfy the verification requirement. Then the method of verification using multi-FPGA is taken and expresses some advantages in some respects. Multi-FPGA verification is still in the initial step situation and has a broad developing space. The architecture of multi-FPGA verification platform is given in this paper, as well as some related key technical problem and solutions.

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18

Hwang, Jeong-Won, Seung-Ho Kim, Bin Yang, Cheon-Gi Lee y Seung-Yub Park. "Design of Space Vector Modulation PWM and Digital Control of System On Programmable-Chip Using FPGA". Transactions of the Korean Institute of Electrical Engineers 61, n.º 1 (1 de marzo de 2012): 47–54. http://dx.doi.org/10.5370/kieep.2012.61.1.047.

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19

Chen, Peng Fei, Yue Nan Zeng, Zu Qun Peng y Li Zhi Wu. "Design of Permanent Magnet Synchronous Motor Control Chip Based on SOPC". Applied Mechanics and Materials 654 (octubre de 2014): 203–7. http://dx.doi.org/10.4028/www.scientific.net/amm.654.203.

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This article presents a program for permanent magnet synchronous motor (PMSM) vector control chip design based on SOPC technology. Microprocessor NIOSII and hardware arithmetic unit such as CORDIC and SVPWM, were all integrated in a FPGA by using bus interconnect and IP reuse technology, so that became a dedicated control chip of PMSM. Using hardware and software co-design methods, the chip was designed on Altera's CycloneIII FPGA, chip design flexibility and use small resource. Finally, combined with the power driver board achieved the dual closed-loop control of PMSM. The results show that system have a good performance, which proved that system can be well controlled by the designed IC.

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20

Zhu, Hao, Mu Lan Wang, Wei Su y Hua Jun Liu. "Design of Servo System Intelligent Control Chip Based on FPGA". Advanced Materials Research 542-543 (junio de 2012): 949–52. http://dx.doi.org/10.4028/www.scientific.net/amr.542-543.949.

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According to the required functions of speed control and position control in Computer Numerical Control (CNC) system, the hardware control modules of speed and position are designed based on Field Programmable Gates Array (FPGA) of CYCLONE II family. The software hardening technology is used for speed control and position control. The servo intelligent control chip consists of reset unit, frequency division unit, speed processing unit, subdivision unit, phase discrimination unit, counter unit, compare unit, etc. Through analysis of waveform simulation, the correctness of design and the enhancement of transportability and reliability are achieved.

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21

Viejo, Julian, Jorge Juan-Chico, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, David Guerrero, Enrique Ostua y German Cano. "High-Performance Time Server Core for FPGA System-on-Chip". Electronics 8, n.º 5 (11 de mayo de 2019): 528. http://dx.doi.org/10.3390/electronics8050528.

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This paper presents the complete design and implementation of a low-cost, low-footprint, network time protocol server core for field programmable gate arrays. The core uses a carefully designed modular architecture, which is fully implemented in hardware using digital circuits and systems. Most remarkable novelties introduced are a hardware-optimized timekeeping algorithm implementation, and a full-hardware protocol stack and automatic network configuration. As a result, the core is able to achieve similar accuracy and performance to typical high-performance network time protocol server equipment. The core uses a standard global positioning system receiver as time reference, has a small footprint and can easily fit in a low-range field-programmable chip, greatly scaling down from previous system-on-chip time synchronization systems. Accuracy and performance results show that the core can serve hundreds of thousands of network time clients with negligible accuracy degradation, in contrast to state-of-the-art high-performance time server equipment. Therefore, this core provides a valuable time server solution for a wide range of emerging embedded and distributed network applications such as the Internet of Things and the smart grid, at a fraction of the cost and footprint of current discrete and embedded solutions.

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22

Prasad Acharya, G. y M. Asha Rani. "FPGA Prototyping of Micro-Blaze soft-processor based Multi-core System on Chip". International Journal of Engineering & Technology 7, n.º 2.16 (12 de abril de 2018): 57. http://dx.doi.org/10.14419/ijet.v7i2.16.11416.

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The increased demand for processor-level parallelism has many-folded the challenges for SoC designers to design, simulate and verify/validate today’s Multi-core System-On-Chip (SoC) due to the increased system complexity. There is also a need to reduce the design cycle time to produce a complex multi-core SOC system thereby the product can be brought into the market within an affordable time. The Computer-Aided Design (CAD) tools and Field Programmable Gate Arrays (FPGAs) provide a solution for rapidly prototyping and validating the system. This paper presents an implementation of multi-core SoC consisting of 6 Xilinx Micro-Blaze soft-core processors integrated to the Zynq Processing System (PS) using IP Integrator and these cores will be communicated through AXI bus. The functionality of the system is verified using Micro-Blaze system debugger. The hardware framework for the implemented system is implemented and verified on FPGA.

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23

Zhu, Juan y Yue Chen. "Step Motor Control Based on FPGA". Applied Mechanics and Materials 397-400 (septiembre de 2013): 1226–29. http://dx.doi.org/10.4028/www.scientific.net/amm.397-400.1226.

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Design a step motor control system based on Field Programmable Gate Array (FPGA). Give the hardware circuit of this system and the program based on very high speed integrated circuit hardware description language (VHDL). Compared to step motor control system based on single chip microcomputer, the processing speed of this system is faster.

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24

Wang, Jian Min, Jia Qing Liu, Chun Cheng Ban y Tai Long Gui. "Design of Video-Decoding System Based on the FPGA". Advanced Materials Research 740 (agosto de 2013): 140–45. http://dx.doi.org/10.4028/www.scientific.net/amr.740.140.

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The design and implementation of video-decoding system are analyzed. And then, the video decoding and data processing scheme based on the FPGA and video-decoding chip ADV7181B is proposed. The I2C interface, used to configurate the register parameters of video-decoding chip ADV7181B, and the decoder of ITU-656, the storage of YCrCb, conversion between YCrCb and RGB and the display of VGA are implemented using FPGA. The all sub modules were described using Verilog HDL in the design, and merged in a module after they were emulated successfully. The module was come through and verified. The experiments results show that the system designed in this paper performed well.

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25

Silva, Francisco de Assis Tavares Ferreira da, Magno Prudêncio de Almeida Filho, Antonio Macilio Pereira de Lucena y Alexandre Guirland Nowosad. "Pattern recognition on FPGA for aerospace applications". Research, Society and Development 10, n.º 12 (14 de septiembre de 2021): e83101219181. http://dx.doi.org/10.33448/rsd-v10i12.19181.

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This paper presents a low power near real-time pattern recognition technique based on Mathematical Morphology-MM implemented on FPGA (Field Programmable Gate Array). The key to the success of this approach concerns the advantages of machine learning paradigm applied to the translation invariant template-matching operators from MM. The paper shows that compositions of simple elementary operators from Mathematical Morphology based on ELUTs (Elementary Look-Up Tables) are very suitable to embed in FPGA hardware. The paper also shows the development techniques regarding all mathematical modeling for computer simulation and system generating models applied for hardware implementation using FPGA chip. In general, image processing on FPGAs requires low-level description of desired operations through Hardware Description Language-HDL, which uses high complexity to describe image operations at pixel level. However, this work presents a reconfiguring pattern recognition device implemented directly in FPGA from mathematical modeling simulation under Matlab/Simulink/System Generator environment. This strategy has reduced the hardware development complexity. The device will be useful mainly when applied on remote sensing tasks for aerospace missions using passive or active sensors.

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Gerlein, Eduardo A., Gabriel Díaz-Guevara, Henry Carrillo, Carlos Parra y Enrique Gonzalez. "Embbedded System-on-Chip 3D Localization and Mapping—eSoC-SLAM". Electronics 10, n.º 12 (9 de junio de 2021): 1378. http://dx.doi.org/10.3390/electronics10121378.

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This paper discusses a novel embedded system-on-chip 3D localization and mapping (eSoC-LAM) implementation, that followed a co-design approach with the primary aim of being deployed in a small system on a programmable chip (SoPC), the Intel’s (a.k.a Altera) Cyclone V 5CSEMA5F31C6N, available in the Terasic’s board DE1-SoC. This computer board incorporates an 800 MHz Dual-core ARM Cortex-A9 and a Cyclone V FPGA with 85k programmable logic elements and 4450 Kbits of embedded memory running at 50 MHz. We report experiments of the eSoC-LAM implementation using a Robosense’s 3D LiDAR RS-16 sensor in a Robotis’ TurtleBot2 differential robot, both controlled by a Terasic’s board DE1-SoC. This paper presents a comprehensive description of the designed architecture, design constraints, resource optimization, HPS-FPGA exchange of information, and co-design results. The eSoC-LAM implementation reached an average speed-up of 6.5× when compared with a version of the algorithm running in a the hard processor system of the Cyclone V device, and a performance of nearly 32 fps, while keeping high map accuracy.

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Lai, Chiu-Keng, Yaw-Ting Tsao, Shou-Liang Tsai y Wei-Nan Chien. "Development of an FPGA-Based Motion Control IC for Caving Machine". Advances in Mechanical Engineering 6 (1 de enero de 2014): 813204. http://dx.doi.org/10.1155/2014/813204.

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Since the Field Programmable Gate Arrays (FPGAs) with high density are available nowadays, systems with complex functions can thus be realized by FPGA in a single chip while they are traditionally implemented by several individual chips. In this research, the control of stepping motor drives as well as motion controller is integrated and implemented on Altera Cyclone III FPGA; the resulting system is evaluated by applying it to a 3-axis caving machine which is driven by stepping motors. Finally, the experimental results of current regulation and motion control integrated in FPGA IC are shown to prove the validness.

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Vucha, Mahendra y Arvind Rajawat. "Dynamic Task Distribution Model for On-Chip Reconfigurable High Speed Computing System". International Journal of Reconfigurable Computing 2015 (2015): 1–12. http://dx.doi.org/10.1155/2015/783237.

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Modern embedded systems are being modeled as Reconfigurable High Speed Computing System (RHSCS) where Reconfigurable Hardware, that is, Field Programmable Gate Array (FPGA), and softcore processors configured on FPGA act as computing elements. As system complexity increases, efficient task distribution methodologies are essential to obtain high performance. A dynamic task distribution methodology based on Minimum Laxity First (MLF) policy (DTD-MLF) distributes the tasks of an application dynamically onto RHSCS and utilizes available RHSCS resources effectively. The DTD-MLF methodology takes the advantage of runtime design parameters of an application represented as DAG and considers the attributes of tasks in DAG and computing resources to distribute the tasks of an application onto RHSCS. In this paper, we have described the DTD-MLF model and verified its effectiveness by distributing some of real life benchmark applications onto RHSCS configured on Virtex-5 FPGA device. Some benchmark applications are represented as DAG and are distributed to the resources of RHSCS based on DTD-MLF model. The performance of the MLF based dynamic task distribution methodology is compared with static task distribution methodology. The comparison shows that the dynamic task distribution model with MLF criteria outperforms the static task distribution techniques in terms of schedule length and effective utilization of available RHSCS resources.

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Lai, Chiu Keng y Kun Lin Ho. "To Develop a Parallel Processing System with the FPGA for Multi-Axis Motion Control Platform". Applied Mechanics and Materials 284-287 (enero de 2013): 2396–401. http://dx.doi.org/10.4028/www.scientific.net/amm.284-287.2396.

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It is known that the flexibility and programmable abilities have made the FPGA widely used as controllers to the electrical machines and systems. Above all, the high density of recent developed chip results in many of the CPU cores and complicated hardware can be programmed into the chip to be as controller. Thus, this topic is based on the currently available technologies of FPGA-based system design to the parallel processing. Software and hardware co-design are shown to reach the performance, and the system’s software stream data are processed with the hardware parallel technique. This analysis enables FPGA-based control system on the parallel computing platform to achieve the simultaneous operation for 3-axis motor motion and drive system control. In that way, we chose the high density FPGA, Altera Cyclone II EP2C8Q208C8N, as the chip to develop the hardware of microprocessor, motor drive and motion controller. The developed system was practically applied to a 3-axis motion platform driven by stepping motors to evaluate the system performance.

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30

Hu, Ju Fang, Chun Ru Xiong, Hao Hu y Run Yang Zhong. "Design of a DSP System Based on FPGA". Advanced Materials Research 317-319 (agosto de 2011): 1559–62. http://dx.doi.org/10.4028/www.scientific.net/amr.317-319.1559.

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This paper proposes an innovative methodology to design a DSP (Digital Signal Processing) system using FPGA (Field-programmable Gate Array). There are several main components in this system, including A/D sampling unit, FFT processing unit and control unit. A/D sampling and FFT processing units utilize the Nios processor in FPGA as controller. Control unit uses EP1C20 FPGA chip from ALTERA as FFT processing unit so as to manage the FIFO operations. This unit can handle 128 FFT operations. This system design approach is tested on Matlab. The results indicate that the calculation speed is much faster than common DSP manner.

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31

Guo, Jing Jing, Xiao Jing Xu y Jin Tao Kang. "A Design of Image Acquisition System Based on FPGA and USB2.0". Applied Mechanics and Materials 552 (junio de 2014): 155–60. http://dx.doi.org/10.4028/www.scientific.net/amm.552.155.

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The paper introduces a realization method of high-speed image acquisition system based on FPGA and USB2.0. After introducing the CMOS chip MT9T001 of Micron Technology, Inc. and the universal interface chip CY7C68013 of Cypress Semiconductor Corporation, we design the hardware platform of image acquisition system and the control program written by Verilog HDL language through which FPGA can simulate I2C bus to configure CMOS. Then we introduce the development of firmware, driver and application of the USB interface. This paper completed the design and the experiment of image acquisition system well. In the test, the system achieves the requirement of real-time display. The collected images are clear, which can satisfy design requests.

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32

Tong, Zhan Ying y Jing Kui Mao. "Design of the Power Parameter Measurement System Based on SOPC". Advanced Materials Research 503-504 (abril de 2012): 1338–42. http://dx.doi.org/10.4028/www.scientific.net/amr.503-504.1338.

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In this paper the SOPC technology is applied to the power parameter measurement in a FPGA chip. The Fast Fourier Transform (FFT) algorithm implemented in the FPGA is the theory basis of the system, and the 32 bit NiosⅡ soft CPU nuclear is embedded in the FPGA, which can realize the functions of power signals samping, data processing, storage, display and so on. The experimental result shows that processing precision meets expectations, and achieving requirements of the real-time system, with advantages of high integration and flexible reconstruction.

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33

Cui, Linhai, Yusen Qin, Fanyang Kong y Kaihong Yu. "Design of a Regular Expression Matching System Based on Network on Chip". Open Electrical & Electronic Engineering Journal 7, n.º 1 (14 de junio de 2013): 46–50. http://dx.doi.org/10.2174/1874129001307010046.

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This paper presents an efficient method for Regular Expression Matching (REM) by reusing Intellectual Property (IP) cores in a new architecture of Network on Chip (NoC). The method is to design a reusable IP core which consists of many engine cells for REM and to implement each engine cell on a Field Programmable Gate Array (FPGA) as a prototype. To make Finite State Machine (FSM) simpler, a new approach for partitioning a regular expression into several smaller parts is proposed. Each part of a regular expression was matched by an engine cell during matching, and each engine cell communicates with others by routers on a NoC topology. The proposed NoC architecture is a general-purpose design which is suitable for different rule libraries in deep packet inspection (DPI). It can deal with the problem that character self-deplete made the correct regular expression matching missing. A way to use both logic cell and RAM available on FPGA devices is described, and it can make it easier to change the rule library of regular expressions in the RAM. The implementation of the NoC architecture by employing application-specific integrated circuits (ASIC) is finally discussed.

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34

Zhang, Yue y Linwei Tao. "Multi-Channel Data Acquisition System Based on FPGA and STM32". Xibei Gongye Daxue Xuebao/Journal of Northwestern Polytechnical University 38, n.º 2 (abril de 2020): 351–58. http://dx.doi.org/10.1051/jnwpu/20203820351.

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In order to realize the acquisition and storage of underwater acoustic signals for aiming at the requirements of multi-channel, low power consumption and small volume for underwater receiver extension of sonar system, a multi-channel signal acquisition and storage system based on FPGA and STM32 with variable number of working channels and sampling frequency is designed, in which the system is consisted of 8 pieces, 8 channel and 24 bits high dynamic range Δ-Σ ADS1278 ADC chip to synchronous multi-channel analog signal acquisition. FPGA, as the acquisition sequence and logic control, reads and collates the ADC chip data and writes it into the internal high-capacity FIFO, and adds corresponding operations according to the characteristics of FIFO in an application. SMT32 single-chip microcomputer reads the FIFO data through the high-speed SPI interface with FPGA and writes the multi-channel data into the high-capacity SD card. The testing results have verified that the system has characteristics such as stable and reliable, easy configuration, low power consumption, can guarantee the multichannel data serial transmission, storage, accurate, up to 64 analog signals at the same time the real-time collection and storage, top 20 kHz sampling rate, the system total power of the system of about 3W, data rates up to 100 Mb/s, fully meet the needs of underwater sound acquisition system.

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35

Turki, Mariem, Zied Marrakchi, Habib Mehrez y Mohamed Abid. "Frequency Optimization Objective during System Prototyping on Multi-FPGA Platform". International Journal of Reconfigurable Computing 2013 (2013): 1–12. http://dx.doi.org/10.1155/2013/853510.

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Multi-FPGA hardware prototyping is becoming increasingly important in the system on chip design cycle. However, after partitioning the design on the multi-FPGA platform, the number of inter-FPGA signals is greater than the number of physical connections available on the prototyping board. Therefore, these signals should be time-multiplexed which lowers the system frequency. The way in which the design is partitioned affects the number of inter-FPGA signals. In this work, we propose a set of constraints to be taken into account during the partitioning task. Then, the resulting inter-FPGA signals are routed with an iterative routing algorithm in order to obtain the best multiplexing ratio. Indeed, signals are grouped and then routed using the intra-FPGA routing algorithm: Pathfinder. This algorithm is adapted to deal with the inter-FPGA routing problem. Many scenarios are proposed to obtain the most optimized results in terms of prototyping system frequency. Using this technique, the system frequency is improved by an average of 12.8% compared to constructive routing algorithm.

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36

Soh, Jeremy y Xiaofeng Wu. "An FPGA-Based Unscented Kalman Filter for System-On-Chip Applications". IEEE Transactions on Circuits and Systems II: Express Briefs 64, n.º 4 (abril de 2017): 447–51. http://dx.doi.org/10.1109/tcsii.2016.2565730.

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37

Rajmohan, M. y R. Madhusudhanan. "BIST for system-on-a-chip using an embedded FPGA core". International Journal of MC Square Scientific Research 1, n.º 1 (15 de junio de 2009): 15–19. http://dx.doi.org/10.20894/ijmsr.117.001.001.003.

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38

Wong, Ching-Chang y Yu-Han Lin. "DESIGN AND IMPLEMENTATION OF GA-BASED FUZZY SYSTEM ON FPGA CHIP". Cybernetics and Systems 39, n.º 1 (4 de diciembre de 2007): 79–107. http://dx.doi.org/10.1080/01969720701710220.

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39

Dong, Jian Jun y Tan Sheng Zhou. "Design of Multi-Signal Testing System Based on ARM & FPGA". Applied Mechanics and Materials 182-183 (junio de 2012): 1215–19. http://dx.doi.org/10.4028/www.scientific.net/amm.182-183.1215.

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This paper presents a multi-signal testing system based on ARM & FPGA, Paper discussed system structure design, including hardware and software design. The hardware uses FPGA to expand ports and USB2.0 interface chip CY7C68013 for signals data transmission; software including system firmware, driver, user applications the three-parts design. The design of the system meet requirements, its high performance, low cost and can be widely used in signal analysis, monitoring and other fields.

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40

Zhou, Zhimei, Yong Wan, Yin Liu, Xiaoyan Guo, Qilin Yin y Chen Feng. "The advancement of cluster based FPGA place & route technic". MATEC Web of Conferences 309 (2020): 01014. http://dx.doi.org/10.1051/matecconf/202030901014.

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As one of the core components of electronic hardware systems, Field Programmable Logic Array (FPGA) device design technology continues to advance under the guidance of electronic information technology policies, and has made information technology applications. huge contribution. However, with the advancement of chip technology and the continuous upgrading of information technology, the functions that FPGAs need to perform are more and more complicated. How to efficiently perform layout design and make full use of chip resources has become an important technology to be solved and optimized in FPGA design. The FPGA itself is not limited to a specific function. It contains internal functions such as memory, protocol module, clock module, high-speed interface module and digital signal processing. It can be programmed through logic modules such as programmable logic unit modules and interconnects. Blank FPGA devices are designed to be high performance system applications with complex functions. The layout and routing technology based on cluster logic unit blocks can combine the above resources to give full play to its performance advantages, and its importance is self-evident. Based on the traditional FPGA implementation, this paper analyzes several advantages based on cluster logic block layout and routing technology, and generalizes the design method and flow based on cluster logic block layout and routing technology.

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41

Lai, Chiu Keng, Yaw Ting Tsao, Shou Liang Tsai y Wei Nan Chen. "An Integrated Realization of Motion Control and Motor Drives with FPGA". Applied Mechanics and Materials 479-480 (diciembre de 2013): 607–11. http://dx.doi.org/10.4028/www.scientific.net/amm.479-480.607.

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Since the Field Programmable Gate Arrays (FPGAs) with high density are available nowadays, systems with complex functions can be realized by FPGA in a single chip while they are usually traditionally implemented by several individual chips. In this research, the drives as well as motion controller are integrated and implemented on Altera Cyclone III FPGA. The system is also evaluated by applying it to a 3-axis motion platform driven by stepping motors. Finally, experimental results of current regulator and motion controller are shown to prove the validness.

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42

Huang, Chao. "FPGA-Based Battery Management System". Applied Mechanics and Materials 543-547 (marzo de 2014): 792–95. http://dx.doi.org/10.4028/www.scientific.net/amm.543-547.792.

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This article introduces a battery management system of portable receiver or equipment based on a FPGA chip for control. This design can control the charge-discharge process and obtain the battery information through a SoPC, which can transfer the information to the upper computer for displaying and managing through the interface between the local and the network, or warn and deal with the abnormal condition according to the information. This design can be widely used in portable embedded system or digital system for power supply.

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43

Leng, Jian Wei y Ying Hui Wu. "CMOS Real-Time Image Acquisition and Display System Design Based on FPGA". Applied Mechanics and Materials 644-650 (septiembre de 2014): 4403–6. http://dx.doi.org/10.4028/www.scientific.net/amm.644-650.4403.

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Based on characteristics of image acquisition system of high-speed and large-capacity, this paper presents a CMOS Image sensor data acquisition system that is using FPGA Chip as its core processing devices. Data acquisition logic control unit is designed by FPGA. The modular structure of the system design, FIFO, ping-pong and other technology are used in the design process to ensure real-time data acquisition and transmission. FPGA implementation of video acquisition can improve system performance. It also has a strong adaptability and flexibility, and it is easy to design, debug and so on. Through the experiment, we can get a clear image.

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44

Zheng, Yong, Yan Chen y Ge Zhu. "Development of High-Speed Transmission Error Dynamic Detection System Based on NIOS-II and USB". Applied Mechanics and Materials 325-326 (junio de 2013): 883–86. http://dx.doi.org/10.4028/www.scientific.net/amm.325-326.883.

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This paper proposes a high-speed transmission error (TE) dynamic detection system based on NIOS-II and USB. The detection system is in the realization of data acquisition on a FPGA chip, and sends the collected data to specialized data transmission circuit by the chip NIOS-II CPU core, the data transmission circuit composed of USB2.0 main control chip and FIFO chip, which can realize the two-direction communication between data acquisition circuit and PC, so as to realize the TE detection of high-speed side.

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45

Zhou, Ming Yu, Xuan Zhou, Guang Yu Zheng y Shu Sheng Peng. "High-Speed Data Acquisition System Based on FPGA in Missile-Borne Test System". Applied Mechanics and Materials 333-335 (julio de 2013): 452–59. http://dx.doi.org/10.4028/www.scientific.net/amm.333-335.452.

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In this paper, a high-speed data acquisition system based on FPGA is introduced, which has three different channels with one 5Msps sampling rate and 3×256Mb NAND FLASH. This system is controlled by a large scale FPGA chip from Xilinx Inc., XC3S500E-4FG320C. The collected data are first stored in nonvolatile flash on this fuse in-orbit and imported into a USB disk after down-falling. The main hardware and software design of each module are introduced in detail. Experiment results are shown in the final chapter.

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46

Zhang, Jing Bo, Xiao Feng Wang y Shu Fang Zhang. "Audio Signal Processing Based on FPGA". Advanced Materials Research 1049-1050 (octubre de 2014): 1759–64. http://dx.doi.org/10.4028/www.scientific.net/amr.1049-1050.1759.

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This paper presents a system of audio signal processing based on FPGA,the system uses audio codec chip LM4550 to A/D transform and D/A transform the input analog audio signal and output digital audio signal.Using FPGA as the high speed signal processor to realize volume adjustment and audio effect control,so it can output different style music.Meantime, the system designs a FFT computing module and control system of VGA display interface,to compute the digital audio signal which is A/D transformed,and real-time display the frequency spectrum of audio signal on VGA.

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47

Ababei, Cristinel, Shaun Duerr, William Joseph Ebel Jr., Russell Marineau, Milad Ghorbani Moghaddam y Tanzania Sewell. "Open Source Digital Camera on Field Programmable Gate Arrays". International Journal of Handheld Computing Research 7, n.º 4 (octubre de 2016): 30–40. http://dx.doi.org/10.4018/ijhcr.2016100103.

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We present an open source digital camera implemented on a field programmable gate array (FPGA). The camera functionality is completely described in VHDL and tested on the DE2-115 educational FPGA board. Some of the current features of the camera include video mode at 30 fps, storage of taken snapshots into SDRAM memories, and grayscale and edge detection filters. The main contributions of this project include 1) the actual system level design of the camera, tested and verified on an actual FPGA chip, and 2) the public release of the entire implementation including source code and documentation. While the proposed camera is far from being able to compete with commercial offerings, it can serve as a framework to test new research ideas related to digital camera systems, image processing, computer vision, etc., as well as an educational platform for advanced digital design with VHDL and FPGAs. As examples of that, we report two spin-off projects developed on top of or starting from the presented digital camera system.

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Heinz, Carsten, Jaco Hofmann, Jens Korinth, Lukas Sommer, Lukas Weber y Andreas Koch. "The TaPaSCo Open-Source Toolflow". Journal of Signal Processing Systems 93, n.º 5 (mayo de 2021): 545–63. http://dx.doi.org/10.1007/s11265-021-01640-8.

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AbstractThe integration of FPGA-based accelerators into a complete heterogeneous system is a challenging task faced by many researchers and engineers, especially now that FPGAs enjoy increasing popularity as implementation platforms for efficient, application-specific accelerators for domains such as signal processing, machine learning and intelligent storage. To lighten the burden of system integration from the developers of accelerators, the open-source TaPaSCo framework presented in this work provides an automated toolflow for the construction of heterogeneous many-core architectures from custom processing elements, and a simple, uniform programming interface to utilize spatially distributed, parallel computation on FPGAs. TaPaSCo aims to increase the scalability and portability of FPGA designs through automated design space exploration, greatly simplifying the scaling of hardware designs and facilitating iterative growth and portability across FPGA devices and families. This work describes TaPaSCo with its primary design abstractions and shows how TaPaSCo addresses portability and extensibility of FPGA hardware designs for systems-on-chip. A study of successful projects using TaPaSCo shows its versatility and can serve as inspiration and reference for future users, with more details on the usage of TaPaSCo presented in an in-depth case study and a short overview of the workflow.

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49

Zheng, Hua Qiang, Li Fu Ma, Yang Liu y Fei Cai. "Real-Time Video Convert System Design Based on LVDS". Advanced Materials Research 159 (diciembre de 2010): 514–21. http://dx.doi.org/10.4028/www.scientific.net/amr.159.514.

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In this paper, we designed a real-time video convert system for the imaging devices which used digital precision progressive scan monochrome camera or the similar camera and as video signal sensor. System hardware circuit design based on LVDS transmission chip, multiformat video decoder chip: ADV718X and the Cyclone II series FPGA. System software design based on hardware description language, verilog HDL and VHDL. The system could real-time capture, process CVBS and output LVDS video data without the system computer.

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Fu, Shi Min, Cheng Jun Qiu, Dan Bu, Quan Yi Liu y Chao Wang. "Research on Internet of Things Based on SOPC". Applied Mechanics and Materials 195-196 (agosto de 2012): 132–37. http://dx.doi.org/10.4028/www.scientific.net/amm.195-196.132.

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An Internet of things system using Cyclone EP2C8 FPGA chip of Altera is designed and researched in this paper, which integrated NiosII soft-core processor, memory, functional interfaces with SOPC (system on a programmable chip) technology. The μC/OS-II embedded operating system is transplanted here to realize the network communication through driving the network chip. Simultaneously, the message stored in card can be correctly identified, recorded, added up by RFID technology, and sent to internet according to the requirement of communication. Thus, the internet of things function is realized.

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