Bibliografías temáticas / Hardware-software design

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Literatura académica sobre el tema "Hardware-software design"

Autor: Grafiati

Publicado: 4 de junio de 2021

Última modificación: 1 de febrero de 2022

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Artículos de revistas sobre el tema "Hardware-software design"

De Michell, G. y R. K. Gupta. "Hardware/software co-design". Proceedings of the IEEE 85, n.º 3 (marzo de 1997): 349–65. http://dx.doi.org/10.1109/5.558708.

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Mills, Mike y Greg Peterson. "Hardware/software co-design". ACM SIGAda Ada Letters XVIII, n.º 6 (noviembre de 1998): 18–27. http://dx.doi.org/10.1145/301687.289528.

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Kuchcinski, Krzysztof. "Design of hardware and software systems". Journal of Systems Architecture 42, n.º 9-10 (febrero de 1997): 663–64. http://dx.doi.org/10.1016/s1383-7621(96)00068-9.

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Aronsson, Markus y Mary Sheeran. "Hardware software co-design in Haskell". ACM SIGPLAN Notices 52, n.º 10 (31 de octubre de 2017): 162–73. http://dx.doi.org/10.1145/3156695.3122970.

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Naidu, DS. "Microprocessors: hardware, software and design applications". Microprocessors and Microsystems 9, n.º 2 (marzo de 1985): 86–87. http://dx.doi.org/10.1016/0141-9331(85)90431-4.

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Chen, Andrew, Rohaan Gupta, Anton Borzenko, Kevin Wang y Morteza Biglari-Abhari. "Accelerating SuperBE with Hardware/Software Co-Design". Journal of Imaging 4, n.º 10 (18 de octubre de 2018): 122. http://dx.doi.org/10.3390/jimaging4100122.

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Background Estimation is a common computer vision task, used for segmenting moving objects in video streams. This can be useful as a pre-processing step, isolating regions of interest for more complicated algorithms performing detection, recognition, and identification tasks, in order to reduce overall computation time. This is especially important in the context of embedded systems like smart cameras, which may need to process images with constrained computational resources. This work focuses on accelerating SuperBE, a superpixel-based background estimation algorithm that was designed for simplicity and reducing computational complexity while maintaining state-of-the-art levels of accuracy. We explore both software and hardware acceleration opportunities, converting the original algorithm into a greyscale, integer-only version, and using Hardware/Software Co-design to develop hardware acceleration components on FPGA fabric that assist a software processor. We achieved a 4.4× speed improvement with the software optimisations alone, and a 2× speed improvement with the hardware optimisations alone. When combined, these led to a 9× speed improvement on a Cyclone V System-on-Chip, delivering almost 38 fps on 320 × 240 resolution images.

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Kent, K. B., M. Serra y N. Horspool. "Hardware/software co-design for virtual machines". IEE Proceedings - Computers and Digital Techniques 152, n.º 5 (2005): 537. http://dx.doi.org/10.1049/ip-cdt:20041264.

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Wirth, Niklaus. "Hardware/software co-design then and now". Information Processing Letters 88, n.º 1-2 (octubre de 2003): 83–87. http://dx.doi.org/10.1016/s0020-0190(03)00385-5.

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Gómez-Pulido, Juan A. "Recent advances in Hardware/Software co-design". Journal of Systems Architecture 56, n.º 8 (agosto de 2010): 303–4. http://dx.doi.org/10.1016/j.sysarc.2010.06.008.

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Wolf, W. H. "Hardware-software co-design of embedded systems". Proceedings of the IEEE 82, n.º 7 (julio de 1994): 967–89. http://dx.doi.org/10.1109/5.293155.

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Tesis sobre el tema "Hardware-software design"

Nilsson, Per. "Hardware / Software co-design for JPEG2000". Thesis, Linköping University, Department of Electrical Engineering, 2006. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-5796.

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For demanding applications, for example image or video processing, there may be computations that aren’t very suitable for digital signal processors. While a DSP processor is appropriate for some tasks, the instruction set could be extended in order to achieve higher performance for the tasks that such a processor normally isn’t actually design for. The platform used in this project is flexible in the sense that new hardware can be designed to speed up certain computations.

This thesis analyzes the computational complex parts of JPEG2000. In order to achieve sufficient performance for JPEG2000, there may be a need for hardware acceleration.

First, a JPEG2000 decoder was implemented for a DSP processor in assembler. When the firmware had been written, the cycle consumption of the parts was measured and estimated. From this analysis, the bottlenecks of the system were identified. Furthermore, new processor instructions are proposed that could be implemented for this system. Finally the performance improvements are estimated.

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Bappudi, Bhargav. "Example Modules for Hardware-software Co-design". University of Cincinnati / OhioLINK, 2016. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1470043472.

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Liucheng, Miao, Su Jiangang y Feng Bingxuan. "HARDWARE-INDEPENDENT AND SOFTWARE-INDEPENDENT IN SYSTEM DESIGN". International Foundation for Telemetering, 2000. http://hdl.handle.net/10150/606803.

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International Telemetering Conference Proceedings / October 23-26, 2000 / Town & Country Hotel and Conference Center, San Diego, California
Today, open technology has been widely used in computer and other field, including software and hardware. The “Open Technology” about hardware and software can be called “Hardware-Independent and Software-Independent”(For example, Open Operating System in Computer.). But, in telemetry technology field, the system design based on “Hardware-Independent and Software-Independent” is primary stage. In this paper, the following question will be discussed: a. Why telemetry system design needs “open technology” b. How to accomplish system design based on “Hardware-Independent and Software-Independent” c. The application prospect of “hardware-Independent and Software-Independent” in system design.

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Li, Juncao. "An Automata-Theoretic Approach to Hardware/Software Co-verification". PDXScholar, 2010. https://pdxscholar.library.pdx.edu/open_access_etds/12.

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Hardware/Software (HW/SW) interfaces are pervasive in computer systems. However, many HW/SW interface implementations are unreliable due to their intrinsically complicated nature. In industrial settings, there are three major challenges to improving reliability. First, as there is no systematic framework for HW/SW interface specifications, interface protocols cannot be precisely conveyed to engineers. Second, as there is no unifying formal model for representing the implementation semantics of HW/SW interfaces accurately, some critical properties cannot be formally verified on HW/SW interface implementations. Finally, few automatic tools exist to help engineers in HW/SW interface development. In this dissertation, we present an automata-theoretic approach to HW/SW co-verification that addresses these challenges. We designed a co-specification framework to formally specify HW/SW interface protocols; we synthesized a hybrid Büchi Automaton Pushdown System, namely Büchi Pushdown System (BPDS), as the unifying formal model for HW/SW interfaces; and we created a co-verification tool, CoVer that implements our model checking algorithms and realizes our reduction algorithms for BPDS. The application of our approach to the Windows device/driver framework has resulted in the detection of fifteen specification issues. Furthermore, utilizing CoVer, we discovered twelve real bugs in five drivers. These non-trivial findings have demonstrated the significance of our approach in industrial applications.

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Cadenelli, Luca. "Hardware/software co-design for data-intensive genomics workloads". Doctoral thesis, Universitat Politècnica de Catalunya, 2019. http://hdl.handle.net/10803/668250.

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Since the last decade, the main components of computer systems have been evolving, diversifying, to overcome their physical limits and to minimize their energy footprint. Hardware specialization and heterogeneity have become key to design more efficient systems and tackle ever-important problems with ever-larger volumes of data. However, to fully take advantage of the new hardware, a tighter integration between hardware and software, called hardware/software co-design, is also needed. Hardware/software co-design is a time-consuming process that poses its challenges, such as code and performance portability. Despite its challenges and considerable costs, it is an effort that is crucial for data-intensive applications that run at scale. Such applications span across different fields, such as engineering, chemistry, life sciences, astronomy, high energy physics, earth sciences, et cetera. Another scientific field where hardware/software co-design is fundamental is genomics. Here, modern DNA sequencing technologies reduced the sequencing time and made its cost orders of magnitude cheaper than it was just a few years ago. This breakthrough, together with novel genomics methods, will eventually enable the long-awaited personalized medicine. Personalized medicine selects appropriate and optimal therapies based on the context of a patient’s genome, and it has the potential to change medical treatments as we know them today. However, the broad adoption of genomics methods is limited by their capital and operational costs. In fact, genomics pipelines consist of complex algorithms with execution times of many hours per each patient and vast intermediate data structures stored in main memory for good performance. To satisfy the main memory requirement genomics applications are usually scaled-out to multiple compute nodes. Therefore, these workloads require infrastructures of enterprise-class servers, with entry and running costs that that most labs, clinics, and hospitals cannot afford. Due to these reasons, co-designing genomics workloads to lower their total cost of ownership is essential and worth investigating. This thesis demonstrates that hardware/software co-design allows migrating data-intensive genomics applications to inexpensive desktop-class machines to reduce the total cost of ownership when compared to traditional cluster deployments. Firstly, the thesis examines algorithmic improvements to ease co-design and to reduce workload footprint, using NVMs as a memory extension, and so to be able to run in one single node. Secondly, it investigates how data-intensive algorithms can offload computation to programmable accelerators (i.e., GPUs and FPGAs) to reduce the execution time and the energy-to-solution. Thirdly, it explores and proposes techniques to substantially reduce the memory footprint through the adoption of flash memory to the point that genomics methods can run on one affordable desktop-class machine. Results on SMUFIN, a state-of-the-art real-world genomics method prove that hardware/software co-design allows significant reductions in the total cost of ownership of data-intensive genomics methods, easing their adoption on large repositories of genomes and also on the field.

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Engels, Daniel Wayne 1970. "Scheduling for hardware/software partitioning in embedded system design". Thesis, Massachusetts Institute of Technology, 2000. http://hdl.handle.net/1721.1/86443.

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Thesis (Ph.D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2000.
Includes bibliographical references (p. 197-204).
by Daniel Wayne Engels.
Ph.D.

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TIWARI, ANURAG. "HARDWARE/SOFTWARE CO-DEBUGGING FOR RECONFIGURABLE COMPUTING APPLICATIONS". University of Cincinnati / OhioLINK, 2002. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1011816501.

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BRUHNS, THOMAS VICTOR. "HARDWARE AND SOFTWARE FOR A COMPUTER CONTROLLED LIDAR SYSTEM". Diss., The University of Arizona, 1985. http://hdl.handle.net/10150/188042.

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The hardware and software for a computer controlled optical radar, or lidar, system are described. The system builds on a previously installed pulsed ruby backscatter lidar, capable of acquiring data at controlled azimuth and elevation angles through the atmosphere. The described system replaces hardwired logic with computer control. Two coupled computers are used to allow a degree of real time control while data are processed. One of these computers reads and controls mount elevation angle, reads the laser energy monitor, and senses firing of the laser. The other computer serves as a user interface, and receives the lidar return data from a digitizer and memory, and the angle and energy information from the other computer. The second computer also outputs data to a disc drive. The software provided with the system is described, and the feasibility of additional software for both control and data processing is explored. Particular attention is given to data integrity and instrument and computer operation in the presence of the high energy pulses used to drive the laser. A previously described laser energy monitor has been improved to isolate it from laser transients. Mount elevation angles are monitored with an absolute angle readout. As a troubleshooting aid, a simulator with an output that approximates the lidar receiver output was developed. Its output is digitally generated and provides a known repetitive signal. Operating procedures are described for standard data acquisition, and troubleshooting is outlined. The system can be used by a relatively inexperienced operator; English sentences are displayed on the system console CRT terminal to lead the operator through data acquisition once the system hardware is turned on. A brief synopsis of data acquired on the system is given. Those data are used as the basis of other referenced papers. It constitutes soundings for over one hundred days. One high point has been operation of the system in conjunction with a balloon borne atmospheric particulate sampling package. The system has also been used occasionally as the transmitter of a lidar system with physically separated receiver and transmitter.

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Ramírez, Bellido Alejandro. "High performance instruction fetch using software and hardware co-design". Doctoral thesis, Universitat Politècnica de Catalunya, 2002. http://hdl.handle.net/10803/5969.

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En los últimos años, el diseño de procesadores de altas prestaciones ha progresado a lo largo de dos corrientes de investigación: incrementar la profundidad del pipeline para permitir mayores frecuencias de reloj, y ensanchar el pipeline para permitir la ejecución paralela de un mayor numero de instrucciones. Diseñar un procesador de altas prestaciones implica balancear todos los componentes del procesador para asegurar que el rendimiento global no esta limitado por ningún componente individual. Esto quiere decir que si dotamos al procesador de una unidad de ejecución mas rápida, hay que asegurarse de que podemos hacer fetch y decodificar instrucciones a una velocidad suficiente para mantener ocupada a esa unidad de ejecución.

Esta tesis explora los retos presentados por el diseño de la unidad de fetch desde dos puntos de vista: el diseño de un software mas adecuado para las arquitecturas de fetch ya existente, y el diseño de un hardware adaptado a las características especiales del nuevo software que hemos generado.

Nuestra aproximación al diseño de un suevo software ha sido la propuesta de un nuevo algoritmo de reordenación de código que no solo pretende mejorar el rendimiento de la cache de instrucciones, sino que al mismo tiempo pretende incrementar la anchura efectiva de la unidad de fetch. Usando información sobre el comportamiento del programa (profile data), encadenamos los bloques básicos del programa de forma que los saltos condicionales tendrán tendencia a ser no tomados, lo cual favorece la ejecución secuencial del código. Una vez hemos organizado los bloques básicos en estas trazas, mapeamos las diferentes trazas en memoria de forma que minimicen la cantidad de espacio requerida para el código realmente útil, y los conflictos en memoria de este código. Además de describir el algoritmo, hemos realizado un análisis en detalle del impacto de estas optimizaciones sobre los diferentes aspectos del rendimiento de la unidad de fetch: la latencia de memoria, la anchura efectiva de la unidad de fetch, y la capacidad de predicción del predictor de saltos.

Basado en el análisis realizado sobre el comportamiento de los códigos optimizados, proponemos también una modificacion del mecanismo de la trace cache que pretende realizar un uso mas efectivo del escaso espacio de almacenaje disponible. Este mecanismo utiliza la trace cache únicamente para almacenar aquellas trazas que no podrían ser proporcionadas por la cache de instrucciones en un único ciclo.

También basado en el conocimiento adquirido sobre el comportamiento de los códigos optimizados, proponemos un nuevo predictor de saltos que hace un uso extensivo de la misma información que se uso para reordenar el código, pero en este caso se usa para mejorar la precisión del predictor de saltos.

Finalmente, proponemos una nueva arquitectura para la unidad de fetch del procesador basada en explotar las características especiales de los códigos optimizados. Nuestra arquitectura tiene un nivel de complejidad muy bajo, similar al de una arquitectura capaz de leer un único bloque básico por ciclo, pero ofrece un rendimiento muy superior, siendo comparable al de una trace cache, mucho mas costosa y compleja.

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Patel, Krutartha Computer Science &amp Engineering Faculty of Engineering UNSW. "Hardware-software design methods for security and reliability of MPSoCs". Awarded by:University of New South Wales. Computer Science & Engineering, 2009. http://handle.unsw.edu.au/1959.4/44854.

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Security of a Multi-Processor System on Chip (MPSoC) is an emerging area of concern in embedded systems. MPSoC security is jeopardized by Code Injection attacks. Code Injection attacks, which are the most common types of software attacks, have plagued single processor systems. Design of MPSoCs must therefore incorporate security as one of the primary objectives. Code Injection attacks exploit vulnerabilities in \trusted" and legacy code. An architecture with a dedicated monitoring processor (MONITOR) is employed to simultaneously supervise the application processors on an MPSoC. The program code in the application processors is divided into basic blocks. The basic blocks in the application processors are statically instrumented with special instructions that allow communication with the MONITOR at runtime. The MONITOR verifies the execution of all the processors at runtime using control flow checks and either a timing or instruction count check. This thesis proposes a monitoring system called SOFTMON, a design methodology called SHIELD, a design flow called LOCS and an architectural framework called CUFFS for detecting Code Injection attacks. SOFTMON, a software monitoring system, uses a software algorithm in the MONITOR. SOFTMON incurs limited area overheads. However, the runtime performance overhead is quite high. SHIELD, an extension to the work in SOFTMON overcomes the limitation of high runtime overhead using a MONITOR that is predominantly hardware based. LOCS uses only one special instruction per basic block compared to two, as was the case in SOFTMON and SHIELD. Additionally, profile information is generated for all the basic blocks in all the application processors for the MPSoC designer to tune the design by increasing or decreasing the frequency of loop basic blocks. CUFFS detects attacks even without application processors communicating to the MONITOR. The SOFTMON, SHIELD and LOCS approaches can only detect attacks if the application processors communicate to the MONITOR. CUFFS relies on the exact number of instructions in basic blocks to determine an attack, rather than time-frame based measures used in SOFTMON, SHIELD and LOCS. The lowest runtime performance overhead was achieved by LOCS (worst case of 37.5%), while the SOFTMON monitoring system had the least amount of area overheads of about 25%. The CUFFS approach employed an active MONITOR and hence detected a greater range of attacks. The CUFFS framework also detects bit flip errors (reliability errors) in the control flow instructions of the application processors on an MPSoC. CUFFS can detect nearly 70% of all bit flip errors in the control flow instructions. Additionally, a modified CUFFS approach is proposed to ensure reliable inter-processor communication on an MPSoC. The modified CUFFS approach uses a hardware based checksum approach for reliable inter-processor communication and incurred a runtime performance overhead of up to 25% and negligible area overheads compared to CUFFS. Thus, the approaches proposed in this thesis equip an MPSoC designer with tools to embed security features during an MPSoC's design phase. Incorporating security measures at the processor design level provides security against software attacks in MPSoCs and incurs manageable runtime, area and code-size overheads.

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Libros sobre el tema "Hardware-software design"

Micheli, Giovanni y Mariagiovanna Sami, eds. Hardware/Software Co-Design. Dordrecht: Springer Netherlands, 1996. http://dx.doi.org/10.1007/978-94-009-0187-2.

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van den Hurk, Joris y Jochen Jess. System Level Hardware/Software Co-design. Boston, MA: Springer US, 1998. http://dx.doi.org/10.1007/978-1-4757-2805-7.

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Ou, Jingzhao. Energy efficient hardware: Software co-synthesis using reconfigurable hardware. Boca Raton, Fla: Chapman & Hall/CRC, 2009.

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Ou, Jingzhao. Energy efficient hardware-software co-synthesis using reconfigurable hardware. Boca Raton, Fla: Chapman & Hall/CRC, 2009.

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Ou, Jingzhao. Energy efficient hardware-software co-synthesis using reconfigurable hardware. Boca Raton, Fla: Chapman & Hall/CRC, 2009.

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Microprocessors: Software and hardware design using MC68000. Windermere, FL: Innovate LLC, 2008.

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George, Willse, ed. PCI hardware and software: Architecture and design. 3^a ed. San Diego: Annabooks, 1996.

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George, Willse, ed. PCI hardware and software: Architecture and design. San Diego, CA: Annabooks, 1994.

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Balarin, Felice, Massimiliano Chiodo, Paolo Giusto, Harry Hsieh, Attila Jurecska, Luciano Lavagno, Claudio Passerone et al. Hardware-Software Co-Design of Embedded Systems. Boston, MA: Springer US, 1997. http://dx.doi.org/10.1007/978-1-4615-6127-9.

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Bergé, Jean-Michel, Oz Levia y Jacques Rouillard, eds. Hardware/Software Co-Design and Co-Verification. Boston, MA: Springer US, 1997. http://dx.doi.org/10.1007/978-1-4757-2629-9.

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Capítulos de libros sobre el tema "Hardware-software design"

Skliarova, Iouliia y Valery Sklyarov. "Hardware/Software Co-design". En Lecture Notes in Electrical Engineering, 213–41. Cham: Springer International Publishing, 2019. http://dx.doi.org/10.1007/978-3-030-20721-2_6.

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Jansen, Dirk. "Hardware/Software Co-Design". En The Electronic Design Automation Handbook, 172–98. Boston, MA: Springer US, 2003. http://dx.doi.org/10.1007/978-0-387-73543-6_7.

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Marichal, Roel, Gjalt de Jong, Piet van der Putten y Josephus van Sas. "Hardware Dependent Software, the Bridge Between Hardware and Software". En System Specification & Design Languages, 173–82. Boston, MA: Springer US, 2003. http://dx.doi.org/10.1007/0-306-48734-9_14.

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Simpson, Philip. "The Hardware to Software Interface". En FPGA Design, 91–94. New York, NY: Springer New York, 2010. http://dx.doi.org/10.1007/978-1-4419-6339-0_10.

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Micheli, Giovanni. "Hardware/Software Co-Design: Application Domains and Design Technologies". En Hardware/Software Co-Design, 1–28. Dordrecht: Springer Netherlands, 1996. http://dx.doi.org/10.1007/978-94-009-0187-2_1.

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Borriello, G., P. Chou y R. Ortega. "Embedded System Co-Design". En Hardware/Software Co-Design, 243–64. Dordrecht: Springer Netherlands, 1996. http://dx.doi.org/10.1007/978-94-009-0187-2_10.

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Lavagno, Luciano, Alberto Sangiovanni-Vincentelli y Harry Hsieh. "Embedded System Co-Design". En Hardware/Software Co-Design, 213–42. Dordrecht: Springer Netherlands, 1996. http://dx.doi.org/10.1007/978-94-009-0187-2_9.

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Mehta, Ashok B. "Hardware/Software Co-verification". En ASIC/SoC Functional Design Verification, 243–53. Cham: Springer International Publishing, 2017. http://dx.doi.org/10.1007/978-3-319-59418-7_12.

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Niemann, Ralf. "Hardware/Software Partitioning". En Hardware/Software Co-Design for Data Flow Dominated Embedded Systems, 47–131. Boston, MA: Springer US, 1998. http://dx.doi.org/10.1007/978-1-4757-2803-3_4.

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Balboni, Alessandro, William Fornaciari y Donatella Sciuto. "Tosca: A Pragmatic Approach To Co-Design Automation Of Control-Dominated Systems". En Hardware/Software Co-Design, 265–94. Dordrecht: Springer Netherlands, 1996. http://dx.doi.org/10.1007/978-94-009-0187-2_11.

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Actas de conferencias sobre el tema "Hardware-software design"

Mills, Mike y Greg Peterson. "Hardware/software co-design". En the 1998 annual ACM SIGAda international conference. New York, New York, USA: ACM Press, 1998. http://dx.doi.org/10.1145/289524.289528.

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Reddi, Vijay Janapa, Meeta S. Gupta, Michael D. Smith, Gu-yeon Wei, David Brooks y Simone Campanoni. "Software-assisted hardware reliability". En the 46th Annual Design Automation Conference. New York, New York, USA: ACM Press, 2009. http://dx.doi.org/10.1145/1629911.1630114.

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Hao, K. y Fei Xie. "Componentizing hardware/software interface design". En 2009 Design, Automation & Test in Europe Conference & Exhibition (DATE'09). IEEE, 2009. http://dx.doi.org/10.1109/date.2009.5090663.

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Aboulhamid, E. M. "New hardware/software design methodologies". En ICM'2001 Proceedings. 13th International Conference on Microelectronics. IEEE, 2001. http://dx.doi.org/10.1109/icm.2001.997473.

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"Hardware/software co-design (panel)". En the 35th annual conference, chair Peter Heller. New York, New York, USA: ACM Press, 1998. http://dx.doi.org/10.1145/277044.277086.

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Aghdasi, F. "Hardware-software co-design of asynchronous controllers". En IEE Colloquium Hardware-Software Co-Design. IEE, 2000. http://dx.doi.org/10.1049/ic:20000598.

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Eles, P. "Codesign of embedded systems: Where are we now?" En IEE Colloquium Hardware-Software Co-Design. IEE, 2000. http://dx.doi.org/10.1049/ic:20000589.

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Green, P. N. "Object-oriented development methods for embedded systems". En IEE Colloquium Hardware-Software Co-Design. IEE, 2000. http://dx.doi.org/10.1049/ic:20000590.

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Kollig, P. "HW/SW co-design in an industrial environment". En IEE Colloquium Hardware-Software Co-Design. IEE, 2000. http://dx.doi.org/10.1049/ic:20000591.

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Zedan, H. "A logic-based approach for hardware/software co-design". En IEE Colloquium Hardware-Software Co-Design. IEE, 2000. http://dx.doi.org/10.1049/ic:20000592.

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Informes sobre el tema "Hardware-software design"

Kaiser, Alex, Samuel Williams, Kamesh Madduri, Khaled Ibrahim, David Bailey, James Demmel y Erich Strohmaier. A Principled Kernel Testbed for Hardware/Software Co-Design Research. Office of Scientific and Technical Information (OSTI), abril de 2010. http://dx.doi.org/10.2172/983482.

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Xie, Yuan. Blackcomb2: Hardware-Software Co-design for Nonvolatile Memory in Exascale Systems. Office of Scientific and Technical Information (OSTI), abril de 2018. http://dx.doi.org/10.2172/1485357.

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Dinda, Peter August. Enabling Exascale Hardware and Software Design through Scalable System Virtualization (Final Report). Office of Scientific and Technical Information (OSTI), marzo de 2015. http://dx.doi.org/10.2172/1172772.

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Bridges, Patrick G. Final Report: Enabling Exascale Hardware and Software Design through Scalable System Virtualization. Office of Scientific and Technical Information (OSTI), febrero de 2015. http://dx.doi.org/10.2172/1171934.

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Mudge, Trevor. BLACKCOMB2: Hardware-software co-design for non-volatile memory in exascale systems. Office of Scientific and Technical Information (OSTI), diciembre de 2017. http://dx.doi.org/10.2172/1413470.

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Kuno, Harumi. Blackcomb 2: Hardware-Software Co-design for Non-Volatile Memory in Exascale Systems. Office of Scientific and Technical Information (OSTI), septiembre de 2018. http://dx.doi.org/10.2172/1469892.

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Garcia, F. N. Design of software and hardware components for a six-degrees of freedom optical position sensor. Office of Scientific and Technical Information (OSTI), junio de 1997. http://dx.doi.org/10.2172/623045.

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Taiber, Joachim. Unsettled Topics Concerning the Impact of Quantum Technologies on Automotive Cybersecurity. SAE International, diciembre de 2020. http://dx.doi.org/10.4271/epr2020026.

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Quantum computing is considered the “next big thing” when it comes to solving computational problems impossible to tackle using conventional computers. However, a major concern is that quantum computers could be used to crack current cryptographic schemes designed to withstand traditional cyberattacks. This threat also impacts future automated vehicles as they become embedded in a vehicle-to-everything (V2X) ecosystem. In this scenario, encrypted data is transmitted between a complex network of cloud-based data servers, vehicle-based data servers, and vehicle sensors and controllers. While the vehicle hardware ages, the software enabling V2X interactions will be updated multiple times. It is essential to make the V2X ecosystem quantum-safe through use of “post-quantum cryptography” as well other applicable quantum technologies. This SAE EDGE™ Research Report considers the following three areas to be unsettled questions in the V2X ecosystem: How soon will quantum computing pose a threat to connected and automated vehicle technologies? What steps and measures are needed to make a V2X ecosystem “quantum-safe?” What standardization is needed to ensure that quantum technologies do not pose an unacceptable risk from an automotive cybersecurity perspective?

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Coulson, Saskia, Melanie Woods, Drew Hemment y Michelle Scott. Report and Assessment of Impact and Policy Outcomes Using Community Level Indicators: H2020 Making Sense Report. University of Dundee, 2017. http://dx.doi.org/10.20933/100001192.

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Making Sense is a European Commission H2020 funded project which aims at supporting participatory sensing initiatives that address environmental challenges in areas such as noise and air pollution. The development of Making Sense was informed by previous research on a crowdfunded open source platform for environmental sensing, SmartCitizen.me, developed at the Fab Lab Barcelona. Insights from this research identified several deterrents for a wider uptake of participatory sensing initiatives due to social and technical matters. For example, the participants struggled with the lack of social interactions, a lack of consensus and shared purpose amongst the group, and a limited understanding of the relevance the data had in their daily lives (Balestrini et al., 2014; Balestrini et al., 2015). As such, Making Sense seeks to explore if open source hardware, open source software and and open design can be used to enhance data literacy and maker practices in participatory sensing. Further to this, Making Sense tests methodologies aimed at empowering individuals and communities through developing a greater understanding of their environments and by supporting a culture of grassroot initiatives for action and change. To do this, Making Sense identified a need to underpin sensing with community building activities and develop strategies to inform and enable those participating in data collection with appropriate tools and skills. As Fetterman, Kaftarian and Wanderman (1996) state, citizens are empowered when they understand evaluation and connect it in a way that it has relevance to their lives. Therefore, this report examines the role that these activities have in participatory sensing. Specifically, we discuss the opportunities and challenges in using the concept of Community Level Indicators (CLIs), which are measurable and objective sources of information gathered to complement sensor data. We describe how CLIs are used to develop a more indepth understanding of the environmental problem at hand, and to record, monitor and evaluate the progress of change during initiatives. We propose that CLIs provide one way to move participatory sensing beyond a primarily technological practice and towards a social and environmental practice. This is achieved through an increased focus in the participants’ interests and concerns, and with an emphasis on collective problem solving and action. We position our claims against the following four challenge areas in participatory sensing: 1) generating and communicating information and understanding (c.f. Loreto, 2017), 2) analysing and finding relevance in data (c.f. Becker et al., 2013), 3) building community around participatory sensing (c.f. Fraser et al., 2005), and 4) achieving or monitoring change and impact (c.f. Cheadle et al., 2000). We discuss how the use of CLIs can tend to these challenges. Furthermore, we report and assess six ways in which CLIs can address these challenges and thereby support participatory sensing initiatives: i. Accountability ii. Community assessment iii. Short-term evaluation iv. Long-term evaluation v. Policy change vi. Capability The report then returns to the challenge areas and reflects on the learnings and recommendations that are gleaned from three Making Sense case studies. Afterwhich, there is an exposition of approaches and tools developed by Making Sense for the purposes of advancing participatory sensing in this way. Lastly, the authors speak to some of the policy outcomes that have been realised as a result of this research.

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