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1
Niemelä, J. (Jari). "Design and verification of a logic input buffer". Master's thesis, University of Oulu, 2014. http://urn.fi/URN:NBN:fi:oulu-201402121090.
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Two low-power logic input buffer topologies are designed, simulated and compared. The most important parameters of the buffers are input threshold voltage level stability and minimal current consumption. Topologies have been implemented earlier for a wider line width process, and now the intention is to move them to a narrower line width process without losing performance. Based on the simulations, a topology with the better performance and smaller area is chosen and layout for particular topology is designed. Layout parasitics effect to the performance is also verified by simulations. In this thesis are also discussed common buffer structures and I/O structures shielding against outside of a circuit disturbances. Finally there is a measurement plan how an input buffer functionality could be measured and verified on a chipTyössä suunnitellaan, simuloidaan ja verrataan kahta eri topologialla toteutettua kontrollitulopuskuria, joiden tärkeimmät parametrit ovat tulon kynnystason stabiilisuus ja minimaalinen virrankulutus. Topologiat ovat aiemmin toteutettuja leveämmällä viivanleveydellä, ja ne on tarkoitus siirtää kapeamman viivanleveyden prosessiin suorituskyky säilyttäen. Simulointien perusteella valitaan suorituskyvyltään parempi ja pinta-alaltaan pienempi tulopuskuri, ja sille piirretään piirikuvio ja varmennetaan parasiittisten komponenttien vaikutus toimintaan. Diplomityössä käsitellään myös yleisesti puskureita ja I/O-rakenteiden suojausta. Puskurit ovat yhteydessä piirin ulkopuoliseen maailmaan ja niiden täytyy kestää piirin ulkopuoliset häiriötekijät. Lopuksi esitetään mittaussuunnitelma, jolla tulopuskurin toiminta voitaisiin mitata ja varmentaa valmistetusta komponentista
2
Lundberg, Jesper y Ronja Mehtonen. "Utvärdering och analys av batchstorlekar, produktsekvenser och omställningstider". Thesis, Högskolan i Skövde, Institutionen för ingenjörsvetenskap, 2015. http://urn.kb.se/resolve?urn=urn:nbn:se:his:diva-11859.
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Volvo GTO is one of the strongest brands in the truck industry, with a long and proud history of world-leading innovations. The factory in Skövde produces diesel engines of various sizes to Volvo GTO. The project has been carried out on the processing part of grovdel crankshaft. Where the objective was to construct a simulation model that reflects flows 0, 1 and 2 on the crankshaft grovdel order to produce the best driving style for the size of the batches and sequences, focusing on PIA, between the stock and conversion-up times. A theoretical study intervention gave knowledge to the methodology to ensure that the data is collected and processed correctly. The data were collected in an Excel document, which was integrated with the simulation model for an overview and adjustments would be possible. The simulation program, Siemens Plant Simulation 12 used in the construction of the complex model of the three flows, which where verified and validated against the real flows. Optimization on the simulation model was made with a high and a low demand for crankshafts. Several objects were taken into consideration as: minimal waiting processing Findel, minimal setup time and minimal total-PIA from a truly viable perspective. The optimization showed a possible production planning in order to best be able to run such large batches as possible with reduced readjustment time and for delays of production in processing rawflows to not occur in the refined flow. For maximum capacity in the company there are two different optimal solutions one solution focused on reducing setup time and the second solution to minimize the number of additional production hours per week. Discrete simulation of production flows are being used to support production planning and simulation model is created for the continued use of the Volvo GTO, either in simulation group or future researches and theses in collaboration with the University of Skövde. The project objectives were achieved with good results and resulted as a standing basis for future planning of batches and sequences of processing crankshaft Volvo GTO.
3
Jacobson, Mark Alan. "Input and response buffers in transcription handwriting". Diss., Georgia Institute of Technology, 1997. http://hdl.handle.net/1853/28862.
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Nguyen, Kim-Minh Carleton University Dissertation Engineering Electronics. "Module generators for the layout synthesis of BiCMOS input/output buffers". Ottawa, 1993.
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5
Charny, Anna. "Providing QoS guarantees in input buffered crossbar switches with speedup". Thesis, Massachusetts Institute of Technology, 1998. http://hdl.handle.net/1721.1/9628.
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Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1998.Includes bibliographical references (p. 103-105).
This dissertation investigates a number of issues related to providing Quality of Service guarantees in input-buffered crossbar switches with speedup. It is shown that speedup of 4 is sufficient to ensure 100% asymptotic throughput with any maximal matching algorithm employed by the arbiter. It is also demonstrated that the crossbar architecture is capable of providing delay guarantees comparable to those known for output-buffered switch architecture. Several algorithms which ensure different delay guarantees with different values of speedup are presented and analyzed.
by Anna Charny.
Ph.D.
6
Tabatabaee, Vahid. "Scheduling and rate provisioning for input-buffered cell based switch fabrics". College Park, Md. : University of Maryland, 2003. http://hdl.handle.net/1903/141.
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Thesis (Ph. D.) -- University of Maryland, College Park, 2003.Thesis research directed by: Electrical Engineering. Title from t.p. of PDF. Includes bibliographical references. Published by UMI Dissertation Services, Ann Arbor, Mich. Also available in paper.
7
Pisár, Peter. "Metody návrhu aktivních kmitočtových filtrů na základě pasivního RLC prototypu". Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2009. http://www.nusl.cz/ntk/nusl-218107.
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The aim of this diploma thesis is to design active frequency filters based on passive RLC prototype. Three methods of the design of active filters and active functional blocks of electronic circuits working in current or mixed mode are used to this purpose. These blocks allow to process electrical signals with frequencies up to low tens of megahertz. In addition they feature for instance with high slew rate and low supply voltage power. Active high-pass and low-pass 2nd order filters are designed using simulation of inductor by active subcircuit method. Grounded and subsequently floating synthetic inductor is made with the current conveyors in the first case and with the current operational amplifiers with single input and differential output in the second case. This method advantage is relatively simple design and disadvantage is great quantity of active functional blocks. Active filters based on passive frequency ladder 3rd order filter while only one floating inductor is connected, are designed with circuit equation method. In the first design differential input / output current followers are used and in the second case current-differencing buffered amplifiers are used. This method benefits by smaller active blocks number and disadvantage is more complex design of the active filter. Active filter based on passive prototype of low-pass 3rd order filter with two floating inductors is designed with Bruton transformation method. Final active filter uses current operational amplifiers with single input and differential output which together with other passive elements replace frequency depending negative resistor, which arise after previous Bruton transform. This method usage is advantageous if the design consists of larger quantity of inductors and less number of capacitors. High-pass 2nd order filter is simulated by tolerance and parametrical analyses. Physical realisation utilising current feedback operational amplifier which substitute commercially hardly accessible current conveyors is subsequently made. Measurements of constructed active filter show that additional modifications, which allow better amplitude frequency characteristics conformity, are necessary.
8
Liu, Dequan. "Joint buffer management and scheduling for input queued switches". Thesis, 2003. http://library1.njit.edu/etd/fromwebvoyage.cfm?id=njit-etd2003-024.
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Wang, Chen-Tai y 王振泰. "The Design of a Serial Input Random Output Buffer". Thesis, 1993. http://ndltd.ncl.edu.tw/handle/07289474930284679804.
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Hu, Ting-Wei y 胡庭維. "Input Buffer Improved High Speed Asynchronous Successive Approximation Register ADC". Thesis, 2016. http://ndltd.ncl.edu.tw/handle/70012398542253459114.
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碩士國立中興大學
電機工程學系所
104
This thesis presents an input buffer improved high speed Asynchronous successive Approximation Register (SAR) Analog-to-Digital Converter (ADC). The application is as a sub-ADC of a time-interleaved ADC. In order to enhance the converter’s effective number of bits, the input buffer is added. The frist design, Sarf2_34 ,has oscillations found during measurement. Thus a second design Sarf2_35 improve the input buffer circuit to solve, the output waveform oscillation issue. With TSMC 90nm GUTM manufacturing process, and sampling frequency as 166MHZ, measurement results of Sarf2_35 chip is obtained. When input frequency is 10MHZ ,the effective number of bits is 6.09bit.When input frequency is 1GHZ, the effective number of bits is 3.48bit.
11
Peng, Chih-Yang y 彭志洋. "Block and Input/Ouput Buffer Placement in Flip-Chip Design". Thesis, 2003. http://ndltd.ncl.edu.tw/handle/61649670636516290542.
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碩士國立臺灣大學
電子工程學研究所
91
The flip-chip package gives the highest chip density of any packaging method to support the pad-limited ASIC design. One of the most important characteristics of flip chip designs is that the input/output buffers could be placed anywhere inside a chip. For most practical designs, we have to control the timing of the input/output signals. This can be achieved through controlling the positions of bump balls, input/output buffers, and first stage/last-stage cells in a flip chip. Specifically, we intend to minimize the path length between blocks and bump balls as well as the delay skew of the paths. In this thesis, we propose a hierarchical top-down method for the block and input/output buffer placement in flip-chip design. We first cluster a block and its corresponding buffers to reduce the problem size. Then, we go into iterations of the following two steps: the alternating and interacting global optimization step and the partitioning step. The global optimization step places modules based on simulated annealing using the B*-tree representation to minimize a given cost function. The partitioning step dissects the chip into two subregions, and the modules are divided into two groups according to their coordinates and are placed in respective subregions. The two steps repeat until each subregion contains at most a given number of modules, defined by the ratio of the total module area to the chip area. At last, we refine the placement by perturbing modules inside a subregion as well as in different subregions. Compared with the placement using the B*-tree alone, our method obtains significantly better results, with an average cost of only 48.4\% of that obtained by using the B*-tree alone.
12
Varma, Ambrish Kant. "Improved behavioral modeling based on the input output buffer information specification". 2007. http://www.lib.ncsu.edu/theses/available/etd-01042007-012012/unrestricted/etd.pdf.
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Chao, Wen-Chang. "Performance-Driven Block and Input/Output Buffer Placement in Flip-Chip Design". 2004. http://www.cetd.com.tw/ec/thesisdetail.aspx?etdun=U0001-2907200414064000.
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Chao, Wen-Chang y 趙文璋. "Performance-Driven Block and Input/Output Buffer Placement in Flip-Chip Design". Thesis, 2004. http://ndltd.ncl.edu.tw/handle/6565c8.
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碩士國立臺灣大學
電子工程學研究所
92
The flip-chip package gives the highest chip density of any packaging methods to support the pad-limited ASIC design. One of the most important characteristics of flip chip designs is that the input/output buffers could be placed anywhere inside a chip. For most practical designs, we have to control the timing of the input/output signals. This can be achieved through controlling the positions of bump balls, input/output buffers, and first-stage/last-stage cells in a flip chip. Specifically, we intend to minimize the path length between blocks and bump balls as well as the delay skew of the paths. In this thesis, we propose a two-stage placement method for the block and input/output buffer placement in flip-chip design. In the first stage, we apply simulated annealing using the B*-tree representation to minimize the maximum wirelength and obtain an initial feasible placement. In the second stage, we apply an iterative algorithm to improve the initial solution. In each iteration, we find the zero-skew position for each buffer to minimize the signal delay skew between the buffer and one with the maximum signal delay. The iterative improvement terminates when all of the signal delay skews of input/output buffers are under an user-specified range. Compared with the placement using the B*-tree alone and the work in [16], our method obtains significantly better results. The B*-tree based algorithm ([16]) results in overall cost of 32.23 times (14.08 times) of that of our algorithm. In terms of running time, the B*-tree based algorithm ([16]) needs 15.34 times (10.47 times) of our CPU time. In particular, setting an appropriate grid size and a signal skew range, we can even get a placement with zero signal skews for all input/output buffers.
15
Narayana, Sagar 1986. "Throughput-Efficient Network-on-Chip Router Design with STT-MRAM". Thesis, 2012. http://hdl.handle.net/1969.1/148157.
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As the number of processor cores on a chip increases with the advance of CMOS technology, there has been a growing need of more efficient Network-on-Chip (NoC) design since communication delay has become a major bottleneck in large-scale multicore systems. In designing efficient input buffers of NoC routers for better performance and power efficiency, Spin-Torque Transfer Magnetic RAM (STT-MRAM) is regarded as a promising solution due to its nature of high density and near-zero leakage power. Previous work that adopts STT-MRAM in designing NoC router input buffer shows a limitation in minimizing the overhead of power consumption, even though it succeeds to some degree in achieving high network throughput by the use of SRAM to hide the long write latency of STT-MRAM.
In this thesis, we propose a novel input buffer design that depends solely on STT-MRAM without the need of SRAM to maximize the benefits of low leakage power and area efficiency inherent in STT-MRAM. In addition, we introduce power-efficient buffer refreshing schemes synergized with age-based switch arbitration that gives higher priority to older flits to remove unnecessary refreshing operations. On an average, we observed throughput improvements of 16% on synthetic workloads and benchmarks.
16
Lin, Chun-Yuan y 林俊源. "On the Design of Optical Buffer for Optical Input-Queued Switches with Quality of Service Guarantees". Thesis, 2005. http://ndltd.ncl.edu.tw/handle/44759898443916227840.
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碩士國立交通大學
資訊科學系所
93
This paper presents a quality of service (QoS) enable optical delay line (ODL) architecture to solve the problem of resource contention and support multilevel priority queues in an optical packet switch. ODL has been used in optical packet switches to resolve resource contention; however, the packets travel continuously in ODL limits the management of random access of the packets and increases the packet loss probability. Moreover, multiple ODL sets usually are needed to realize multiple priority queues in order to support QoS. In this paper, a new Unicast Recirculatiion ODL (URODL) architecture is proposed to resolve the output contention problem in an input-queued optical packet switch. To improve relatively poor throughput due to the head of Line (HOL) blocking in the input-queued switch, we modify URODL to support a more efficient window-based lookahead scheduling algorithm. Furthermore, a control strategy is designed to turn a single set of URODL into multiple logical queues to hold different priority packets. The simulation results show our URODL model reduces high priority packet loss effectively with the capability to support QoS. This URODL model can be easily implemented and managed in a fast optical packet switch.
17
Leonardo, David Barros. "Design of High-Bandwidth and High-Linearity Input Buffers for ADCs". Master's thesis, 2020. http://hdl.handle.net/10362/110350.
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Nowadays on-chip Input Buffers (IBs) for direct conversion front-ends are realized
with a higher voltage supply than that of the core voltage of the technology, mainly for
linearity purposes. This, in turn, makes it mandatory to have more than one voltage
source to supply a single chip in addition to having devices capable of handling higher
voltages.
This work explores the possibility of having IBs supplied with the technology’s core
voltage to standardize all of the devices and reducing the different voltage supply sources
and/or voltage regulators needed for operating the front-end drivers of the Analog to
Digital Converters (ADCs).
A new input buffer architecture will be presented and compared to some prior input
buffer implementations in the same conditions. This new architecture presents good
linearity and bandwidth results and can be used for input buffers with the added benefit
of not needing higher voltages nor special devices.
This new architecture is based off an existing one with another feedback loop to
improved high-frequency peaking and linearity issues. This architecture achieves better
results in bandwidth, a SNDR of 58 dB with and output voltage of 600 mV peak-to-peak
differential. Furthermore, this buffer achieves a better efficiency linearity-wise when
comparing to other buffers in the same conditions.
18
He, Chen-Yu y 何宸宇. "A Sub-ns-Access with Sub-mW/GHz 32Kb 5T SRAM Implementation and A Multi-Bit Buffer Design of ADC Input for In-SRAM Computing Architecture". Thesis, 2019. http://ndltd.ncl.edu.tw/handle/kgce86.
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碩士國立交通大學
電子研究所
108
This thesis has two portions, one is low power and high speed SRAM design. In this design, we propose a new 5T SRAM cells with multiple power supply voltages pulsed. Besides, we apply compact array architecture and open-BL to have smaller core area as compared to memory compiler. In idle, read or write mode, using assistant circuits and adaptive supply voltages of cells to optimize speed, power and reliability, respectively. Moreover, the design of tracking circuit is to ensure control correctness within PVT variation. In 28nm CMOS technology, the measurement results show the correct function. After the enhanced key modules design, the simulation results show the performance of sub-ns access with sub-mW/GHz. The second portion of this thesis is designs of multi-bit buffer in In-Memory Computing. Because SRAM cells can just store single bit data, we arrange the storing order of data and have multi-bit buffers to propose the reconfigurable architecture. This architecture can provide optional bit number of input, weigh and output. In buffer designs, we apply Two stage OTA to form a closed loop unity-gain buffer. In 28nm CMOS technology, simulation results show the function correctness within PVT variation.
19
Min, Geyong y X. Jin. "Analytical Modelling and Optimization of Congestion Control for Prioritized Multi-Class Self-Similar Traffic". 2013. http://hdl.handle.net/10454/9689.
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NoTraffic congestion in communication networks can dramatically deteriorate user-perceived Quality-of-Service (QoS). The integration of the Random Early Detection (RED) and priority scheduling mechanisms is a promising scheme for congestion control and provisioning of differentiated QoS required by multimedia applications. Although analytical modelling of RED congestion control has received significant research efforts, the performance models reported in the current literature were primarily restricted to the RED algorithm only without consideration of traffic scheduling scheme for QoS differentiation. Moreover, for analytical tractability, these models were developed under the simplified assumption that the traffic follows Short-Range-Dependent (SRD) arrival processes (e.g., Poisson or Markov processes), which are unable to capture the self-similar nature (i.e., scale-invariant burstiness) of multimedia traffic in modern communication networks. To fill these gaps, this paper presents a new analytical model of RED congestion control for prioritized multi-class self-similar traffic. The closed-form expressions for the loss probability of individual traffic classes are derived. The effectiveness and accuracy of the model are validated through extensive comparison between analytical and simulation results. To illustrate its application, the model is adopted as a cost-effective tool to investigate the optimal threshold configuration and minimize the required buffer space with congestion control.
20
Chen, M., X. L. Jin, Y. Z. Wang, X. Q. Cheng y Geyong Min. "Modelling priority queuing systems with varying service capacity". 2013. http://hdl.handle.net/10454/9635.
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NoMany studies have been conducted to investigate the performance of priority queuing (PQ) systems with constant service capacity. However, due to the time-varying nature of wireless channels in wireless communication networks, the service capacity of queuing systemsmay vary over time. Therefore, it is necessary to investigate the performance of PQ systems in the presence of varying service capacity. In addition, self-similar traffic has been discovered to be a ubiquitous phenomenon in various communication networks, which poses great challenges to performance modelling of scheduling systems due to its fractal-like nature. Therefore, this paper develops a flow-decomposition based approach to performance modelling of PQ systems subject to self-similar traffic and varying service capacity. It specifically proposes an analytical model to investigate queue length distributions of individual traffic flows. The validity and accuracy of the model is demonstrated via extensive simulation experiments.
21
Wu, Hsien. "Separate short-term memory buffers for input and output phonology". Thesis, 2003. http://hdl.handle.net/1911/18581.
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Evidence from brain-damaged patients suggests that there are separate buffers for input and output phonological retention in verbal short-term memory (STM). This possible distinction was investigated with college students (Experiment 1 to 3) and deaf signers of American Sign Language (ASL) (Experiment 4) using different verbal materials in a serial probed recall paradigm. It is reasoned that natural linguistic input (speech for hearing people and ASL for deaf people) would be stored in an input phonological buffer whereas internally generated phonology derived from reading, naming pictured objects, or lip-reading would be stored in an output phonological buffer. In this study, participants were presented with memory lists in which presentation modality (spoken vs. lip-read word, written vs. lip-read word, etc.) was changed after every second item. A probe item from the list was repeated at the end of the list and participants were instructed to either recall the item in the list that has immediately followed the probe or recall the first item after the probe that is in the same modality. Some of these same-modality items were temporally distant, that is, having two intervening items of a different modality. It is predicted that the temporally distant probe in the same modality with the target results in higher memory performance than the temporally adjacent probe in a different modality only if the switch in modalities is between input and output phonological forms. The results from Experiment 1 demonstrated that spoken words and written words were stored in the input and output phonological buffers, respectively. The results from Experiment 2 and 3 further supported the hypothesis in showing that written words were retained in the same buffer with lip-read words and with nameable pictures, while spoken words were retained in a different buffer from these materials. The findings from lists consisting of words in ASL and nameable pictures in Experiment 4 were not conclusive. However, preliminary data suggested that there might also be a separation between signed words and nameable pictures. Overall, the findings from this study conformed to the predictions from the hypothesis of separate input and output phonological retention.
22
"Performance analysis of iterative matching scheduling algorithms in ATM input-buffered switches". 1999. http://library.cuhk.edu.hk/record=b5889961.
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by Cheng Sze Wan.Thesis (M.Phil.)--Chinese University of Hong Kong, 1999.
Includes bibliographical references (leaves 72-[76]).
Abstracts in English and Chinese.
Chapter 1 --- Introduction --- p.1
Chapter 1.1 --- Background --- p.1
Chapter 1.2 --- Traffic Scheduling in Input-buffered Switches .。 --- p.3
Chapter 1.3 --- Organization of Thesis --- p.7
Chapter 2 --- Principle of Enchanced PIM Algorithm --- p.8
Chapter 2.1 --- Introduction --- p.8
Chapter 2.1.1 --- Switch Model --- p.9
Chapter 2.2 --- Enhanced Parallel Iterative Matching Algorithm (EPIM) --- p.10
Chapter 2.2.1 --- Motivation --- p.10
Chapter 2.2.2 --- Algorithm --- p.12
Chapter 2.3 --- Performance Evaluation --- p.16
Chapter 2.3.1 --- Simulation --- p.16
Chapter 2.3.2 --- Delay Analysis --- p.18
Chapter 3 --- Providing Bandwidth Guarantee in Input-Buffered Switches --- p.25
Chapter 3.1 --- Introduction --- p.25
Chapter 3.2 --- Bandwidth Reservation in Static Scheduling Algorithm --- p.26
Chapter 3.3 --- Incorporation of Dynamic and Static Scheduling Algorithms .。 --- p.32
Chapter 3.4 --- Simulation --- p.34
Chapter 3.4.1 --- Switch Model --- p.35
Chapter 3.4.2 --- Simulation Results --- p.36
Chapter 3.5 --- Comparison with Existing Schemes --- p.42
Chapter 3.5.1 --- Statistical Matching --- p.42
Chapter 3.5.2 --- Weighted Probabilistic Iterative Matching --- p.45
Chapter 4 --- EPIM and Cross-Path Switch --- p.50
Chapter 4.1 --- Introduction --- p.50
Chapter 4.2 --- Concept of Cross-Path Switching --- p.51
Chapter 4.2.1 --- Principle --- p.51
Chapter 4.2.2 --- Supporting Performance Guarantee in Cross-Path Switch --- p.52
Chapter 4.3 --- Implication of EPIM on Cross-Path switch --- p.55
Chapter 4.3.1 --- Problem Re-definition --- p.55
Chapter 4.3.2 --- Scheduling in Input Modules with EPIM --- p.58
Chapter 4.4 --- Simulation --- p.63
Chapter 5 --- Conclusion --- p.70
Bibliography --- p.72
23
王翹楚. "Single-Buffered banyan network with input buffering and priority assignment on ATM networks". Thesis, 1992. http://ndltd.ncl.edu.tw/handle/84787921776002104414.
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Shian-Sung, Shiu y 徐獻松. "Burst Performance of Input/Output Buffered ATM Switch with Speed Up and Unblanced Traffic". Thesis, 2002. http://ndltd.ncl.edu.tw/handle/10229832334604412958.
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碩士國立臺灣科技大學
電機工程系
90
With the huge bandwidth (i.e., the data transmission rate) available from optical fiber, the performance bottleneck of ATM-based broadband network has shifted from data transmission rate to processing power of ATM switches and propagation delay of transmission media. With the stochastic nature of input traffic, buffering is an indispensable element of all ATM switches. Although due to the head-of-line effect the throughput with input buffering is significantly lower than that with output buffering, output buffering implies higher complexity. To balance the performance and complexity issues, it is proposed to study nonblocking ATM switches with input/output buffers. The traditional performance measures of ATM switches are cell-based. For many applications the data unit, e.g., a video frame, is too large to place into an ATM cell, and thus is segmented into a series of cells. Thus, contiguous ATM cells are strongly correlated in the sense that they are destined for the same destination or the same ATM switch output. Burst-level performance measures of many applications that generate bursty traffic could more closely reflect quality of service. Therefore we will study both burst and cell level performance measures, e.g., burst (cell) average delay. In addition, since real-time information (e.g., voice, video, and multimedia) has been and expectedly will be the main stream of network traffic, their special requirements should be taken into account while designing ATM switches. One common feature of real-time information is that delay constraint is tight but burst (cell) loss under a certain level is allowed. In other words, bursts (cells) beyond a certain delay constraint might as well be discarded. Thus, it is proposed to analyze another type of performance measure: burst (cell) loss probability caused by excessive delay. In addition, since the priority of real-time traffic is usually higher than that of non-real-time traffic, the priority of each input port is classified into high or low priority. We will employ appropriate priority control to provide different burst (cell) average delays and delay loss probabilities to traffic with different priorities. Lastly, it is proposed to study the effects of the following factors on the design of ATM switches: high and low priority average burst length, high priority input port ratio, unbalanced pattern of traffic, number of input ports, and speed-up and cell contention resolution scheme (priority vs. random) of switches.
25
Huang, Chien-Chang y 黃建章. "Area-Efficient Layout Design for Output and Input Buffers to Improve Driving Capability and ESD Robustness of CMOS VLSI". Thesis, 1996. http://ndltd.ncl.edu.tw/handle/38572546648099296051.
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碩士國立交通大學
電子研究所
84
In this thesis, we propose three new layout designs of output and input buffers of CMOS IC''s. While the CMOS technology has been scaled down into deep-submicron regime with thinner gate oxide, shorter channel length, shallow drain/source junction, LDD (lightly-doped drain) structure, and silicided diffusion, these advanced processes cause serious degradation on the ESD robustness of CMOS IC''s. To achieve the required ESD robustness, the output buffer, which also acts as the protection device for the CMOS IC''s often has to be designed with much larger dimensions than those in the traditional long-channel CMOS technologies. Besides, when the power supply has been scaled down, the width/length (W/L) ratios of NMOS and PMOS devices in the last stage of an output buffer are must enlarged up to offer enough driving/sinking capability of CMOS output buffer for external heavy loading. All the aforementioned factors will increase the layout area of the output buffer. For this reason, three new layout designs, which include square-type layout, hexagon-type layout, and octagon-type layout, are proposed in this thesis. Comparing to the output buffer by the traditional finger-type layout, the new proposed layout styles can provide the current driving/sinking capability of output buffer and ESD robustness of NMOS (PMOS) of I/O ESD protection circuits within a smaller layout area. The drain diffusion area and parasitic drain capacitance of NMOS or PMOS by this new proposed layout are smaller than those by the finger-type layout. Thus, this proposed layout designs are more suitable for CMOS output buffer in the high-speed applications. Also, they can be used in the input protection circuits to provide the ESD protection for CMOS IC''s with smaller layout area. One set of output buffers with different device dimensions and layout spacings have been designed and fabricated by a 0.6-(m SPDM CMOS technology to verify the layout efficiency with comparison to the traditional finger-type layout.
26
Chen, Wen-Jyh y 陳文智. "On Service Guarantees for Input Buffered Crossbar Switches: A Capacity Decomposition Approach by Birkhoff and von Neumann". Thesis, 1999. http://ndltd.ncl.edu.tw/handle/08815334331093349207.
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碩士國立清華大學
電機工程學系
87
Based on a decomposition result by Birkhoff and von Neumann for a doubly substochastic matrix, in this paper we propose a scheduling algorithm that is capable of providing service guarantees for input-buffered crossbar switches. Our service guarantees are uniformly good for all non-uniform traffic, and thus imply 100% throughput. The off-line computational complexity to identify the scheduling algorithm is O(N^4.5) for an N×N switch. Once the algorithm is identified, its on-line computational complexity is O(log N) and its on-line memory complexity is O(N^3log N). Neither framing nor internal speedup is required for our approach.