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Artículos de revistas sobre el tema "Input buffer"

Autor: Grafiati

Publicado: 4 de junio de 2021

Última modificación: 1 de febrero de 2022

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1

Li, Cunlu, Dezun Dong, Shazhou Yang, Xiangke Liao, Guangyu Sun y Yongheng Liu. "CIB-HIER". ACM Transactions on Architecture and Code Optimization 18, n.º 4 (31 de diciembre de 2021): 1–21. http://dx.doi.org/10.1145/3468062.

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Hierarchical organization is widely used in high-radix routers to enable efficient scaling to higher switch port count. A general-purpose hierarchical router must be symmetrically designed with the same input buffer depth, resulting in a large amount of unused input buffers due to the different link lengths. Sharing input buffers between different input ports can improve buffer utilization, but the implementation overhead also increases with the number of shared ports. Previous work allowed input buffers to be shared among all router ports, which maximizes the buffer utilization but also introduces higher implementation complexity. Moreover, such design can impair performance when faced with long packets, due to the head-of-line blocking in intermediate buffers. In this work, we explain that sharing unused buffers between a subset of router ports is a more efficient design. Based on this observation, we propose Centralized Input Buffer Design in Hierarchical High-radix Routers (CIB-HIER), a novel centralized input buffer design for hierarchical high-radix routers. CIB-HIER integrates multiple input ports onto a single tile and organizes all unused input buffers in the tile as a centralized input buffer. CIB-HIER only allows the centralized input buffer to be shared between ports on the same tile, without introducing additional intermediate virtual channels or global scheduling circuits. Going beyond the basic design of CIB-HIER, the centralized input buffer can be used to relieve the head-of-line blocking caused by shallow intermediate buffers, by stashing long packets in the centralized input buffer. Experimental results show that CIB-HIER is highly effective and can significantly increase the throughput of high-radix routers.

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2

Lanyi, S. y M. Pisani. "A high-input-impedance buffer". IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications 49, n.º 8 (agosto de 2002): 1209–11. http://dx.doi.org/10.1109/tcsi.2002.801287.

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3

Scheinhardt, Werner R. W. y Bert Zwart. "A TANDEM FLUID QUEUE WITH GRADUAL INPUT". Probability in the Engineering and Informational Sciences 16, n.º 1 (enero de 2002): 29–45. http://dx.doi.org/10.1017/s0269964802161031.

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For a two-node tandem fluid model with gradual input, we compute the joint steady-state buffer-content distribution. Our proof exploits martingale methods developed by Kella and Whitt. For the case of finite buffers, we use an insightful sample-path argument to extend an earlier proportionality result of Zwart to the network case.

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4

Paik, Jung Hoon y Chae Tak Lim. "The Analysis of Input Queueing Techniques on a Crosspoint Packet Switch". Journal of Circuits, Systems and Computers 07, n.º 04 (agosto de 1997): 319–31. http://dx.doi.org/10.1142/s0218126697000231.

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In this paper, an N × N input-buffered crosspoint packet switch which selects a Head of the Line, HOL, packet in contention randomly is analyzed with a new approach. The approach is based on both a Markov chain representation of the input buffer and the probability that a HOL packet is successfully served. The probability as a function of N is derived, and it makes it possible to express the average packet delay and the average number of packets in the buffer as a function of N. The new contention resolution policy based on the occupancy of the input buffer is also presented and analyzed with this same approach and the relationship between the two selection policies is analyzed.

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5

Chan, P. K., L. Siek, T. Lim y M. K. Han. "Adaptive-biased buffer with low input capacitance". Electronics Letters 36, n.º 9 (2000): 775. http://dx.doi.org/10.1049/el:20000644.

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6

Bundalo, Z. V. y B. L. Dorić. "Three-state CMOS buffer with input hysteresis". Electronics Letters 24, n.º 14 (1988): 885. http://dx.doi.org/10.1049/el:19880603.

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7

Jiang, Fei, Heather E. Preisendanz, Tamie L. Veith, Raj Cibin y Patrick J. Drohan. "Riparian buffer effectiveness as a function of buffer design and input loads". Journal of Environmental Quality 49, n.º 6 (11 de octubre de 2020): 1599–611. http://dx.doi.org/10.1002/jeq2.20149.

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8

Kisriani, Shinta, Eri Prasetyo Wibowo, Busono Soerowirdjo, Hamzah Afandi y Veronica Ernita Kristianti. "A Comparison Study of Three of Input Buffer Designed Using 0.35µm CMOS Technology". Advanced Materials Research 646 (enero de 2013): 184–90. http://dx.doi.org/10.4028/www.scientific.net/amr.646.184.

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In memory device that is contained in the digital application, there is a sequence of input buffer.The input buffer’s function is to improve a digital signal and remove noise. The buffer circuit take these input signal with imperfections and convert them in to full digital logic levels by slicing the signals at correct levels which depends upon the switching point voltage. In this paper,using three topologies, that are NMOS, PMOS and Parallel input buffer. It would be present into design, simulation and analysis of all topologies input buffer. The result in this paper to determine the best of the three topologies to used. The delay time used to determine the best of topologies. Mentor graphic is tools which used in this paper to design and simulation. The technology used in this paper is 0.35 µm CMOS Technology. Analysis of comparison all of topologies used in this paper based on six parameters. The result of comparison analysis can be seen in more details in this explanation.

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9

CITRO, R. "An Adaptive Dynamic Buffer Management (ADBM) Approach for Input Buffers in ATM Networks". IEICE Transactions on Communications E88-B, n.º 3 (1 de marzo de 2005): 1084–96. http://dx.doi.org/10.1093/ietcom/e88-b.3.1084.

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10

Zwart, A. P. "A fluid queue with a finite buffer and subexponential input". Advances in Applied Probability 32, n.º 01 (marzo de 2000): 221–43. http://dx.doi.org/10.1017/s000186780000985x.

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We consider a fluid model similar to that of Kella and Whitt [32], but with a buffer having finite capacity K. The connections between the infinite buffer fluid model and the G/G/1 queue established by Kella and Whitt are extended to the finite buffer case: it is shown that the stationary distribution of the buffer content is related to the stationary distribution of the finite dam. We also derive a number of new results for the latter model. In particular, an asymptotic expansion for the loss fraction is given for the case of subexponential service times. The stationary buffer content distribution of the fluid model is also related to that of the corresponding model with infinite buffer size, by showing that the two corresponding probability measures are proportional on [0,K) if the silence periods are exponentially distributed. These results are applied to obtain large buffer asymptotics for the loss fraction and the mean buffer content when the fluid queue is fed by N On-Off sources with subexponential on-periods. The asymptotic results show a significant influence of heavy-tailed input characteristics on the performance of the fluid queue.

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11

Zwart, A. P. "A fluid queue with a finite buffer and subexponential input". Advances in Applied Probability 32, n.º 1 (marzo de 2000): 221–43. http://dx.doi.org/10.1239/aap/1013540031.

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We consider a fluid model similar to that of Kella and Whitt [32], but with a buffer having finite capacity K. The connections between the infinite buffer fluid model and the G/G/1 queue established by Kella and Whitt are extended to the finite buffer case: it is shown that the stationary distribution of the buffer content is related to the stationary distribution of the finite dam. We also derive a number of new results for the latter model. In particular, an asymptotic expansion for the loss fraction is given for the case of subexponential service times. The stationary buffer content distribution of the fluid model is also related to that of the corresponding model with infinite buffer size, by showing that the two corresponding probability measures are proportional on [0,K) if the silence periods are exponentially distributed. These results are applied to obtain large buffer asymptotics for the loss fraction and the mean buffer content when the fluid queue is fed by N On-Off sources with subexponential on-periods. The asymptotic results show a significant influence of heavy-tailed input characteristics on the performance of the fluid queue.

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12

Tabash, I. K., M. A. Mamun y A. Negi. "A Fuzzy Logic Based Network Congestion Control Using Active Queue Management Techniques". Journal of Scientific Research 2, n.º 2 (26 de abril de 2010): 273–84. http://dx.doi.org/10.3329/jsr.v2i2.2786.

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Conventional IP routers are passive devices that accept packets and perform the routing function on any input. Usually the tail-drop (TD) strategy is used where the input which exceeds the buffer capacity are simply dropped. In active queue management (AQM) methods routers manage their buffers by dropping packets selectively. We study one of the AQM methods called as random exponential marking (REM). We propose an intelligent approach to AQM based on fuzzy logic controller (FLC) to drop packets dynamically, keep the buffer size around desired level and also prevent buffer overflow. Our proposed approach is based on REM algorithm, which drops the packets by drop probability function. In our proposal we replace the drop probability function by a FLC to drop the packets, stabilize the buffer around the desired size and reduce delay. Simulation results show a better regulation of the buffer. Keywords: Random exponential marking; Active queue management; Fuzzy logic controller; Pro-active queue management. © 2010 JSR Publications. ISSN: 2070-0237 (Print); 2070-0245 (Online). All rights reserved. DOI: 10.3329/jsr.v2i2.2786 J. Sci. Res. 2 (2), 273-284 (2010)

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13

Prabhakar, Balaji, Nicholas Bambos y T. S. Mountford. "The synchronization of Poisson processes and queueing networks with service and synchronization nodes". Advances in Applied Probability 32, n.º 03 (septiembre de 2000): 824–43. http://dx.doi.org/10.1017/s0001867800010272.

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This paper investigates the dynamics of a synchronization node in isolation, and of networks of service and synchronization nodes. A synchronization node consists of M infinite capacity buffers, where tokens arriving on M distinct random input flows are stored (there is one buffer for each flow). Tokens are held in the buffers until one is available from each flow. When this occurs, a token is drawn from each buffer to form a group-token, which is instantaneously released as a synchronized departure. Under independent Poisson inputs, the output of a synchronization node is shown to converge weakly (and in certain cases strongly) to a Poisson process with rate equal to the minimum rate of the input flows. Hence synchronization preserves the Poisson property, as do superposition, Bernoulli sampling and M/M/1 queueing operations. We then consider networks of synchronization and exponential server nodes with Bernoulli routeing and exogenous Poisson arrivals, extending the standard Jackson network model to include synchronization nodes. It is shown that if the synchronization skeleton of the network is acyclic (i.e. no token visits any synchronization node twice although it may visit a service node repeatedly), then the distribution of the joint queue-length process of only the service nodes is product form (under standard stability conditions) and easily computable. Moreover, the network output flows converge weakly to Poisson processes. Finally, certain results for networks with finite capacity buffers are presented, and the limiting behavior of such networks as the buffer capacities become large is studied.

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14

Prabhakar, Balaji, Nicholas Bambos y T. S. Mountford. "The synchronization of Poisson processes and queueing networks with service and synchronization nodes". Advances in Applied Probability 32, n.º 3 (septiembre de 2000): 824–43. http://dx.doi.org/10.1239/aap/1013540246.

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This paper investigates the dynamics of a synchronization node in isolation, and of networks of service and synchronization nodes. A synchronization node consists of M infinite capacity buffers, where tokens arriving on M distinct random input flows are stored (there is one buffer for each flow). Tokens are held in the buffers until one is available from each flow. When this occurs, a token is drawn from each buffer to form a group-token, which is instantaneously released as a synchronized departure. Under independent Poisson inputs, the output of a synchronization node is shown to converge weakly (and in certain cases strongly) to a Poisson process with rate equal to the minimum rate of the input flows. Hence synchronization preserves the Poisson property, as do superposition, Bernoulli sampling and M/M/1 queueing operations. We then consider networks of synchronization and exponential server nodes with Bernoulli routeing and exogenous Poisson arrivals, extending the standard Jackson network model to include synchronization nodes. It is shown that if the synchronization skeleton of the network is acyclic (i.e. no token visits any synchronization node twice although it may visit a service node repeatedly), then the distribution of the joint queue-length process of only the service nodes is product form (under standard stability conditions) and easily computable. Moreover, the network output flows converge weakly to Poisson processes. Finally, certain results for networks with finite capacity buffers are presented, and the limiting behavior of such networks as the buffer capacities become large is studied.

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15

Alnasser, Emad. "A Novel High Input Impedance AC-Coupled Buffer". Communications on Applied Electronics 5, n.º 4 (25 de junio de 2016): 17–22. http://dx.doi.org/10.5120/cae2016652278.

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16

Kao, Tzu‐Cheng, Chung‐Yu Hung, Jian‐Hsing Lee, Chen‐Hsin Lien, Chien‐Wei Chiu, Kuo‐Hsuan Lo, Hung‐Der Su y Wu‐Te Weng. "Failure mechanism for input buffer under CDM test". Electronics Letters 50, n.º 9 (abril de 2014): 667–69. http://dx.doi.org/10.1049/el.2013.4094.

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17

Arslan, Emre. "A high performance differential input CMOS current buffer". AEU - International Journal of Electronics and Communications 82 (diciembre de 2017): 1–6. http://dx.doi.org/10.1016/j.aeue.2017.07.037.

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18

Sasaki, Galen H. "Input buffer requirements for round robin polling systems". Performance Evaluation 18, n.º 3 (noviembre de 1993): 237–61. http://dx.doi.org/10.1016/0166-5316(93)90019-q.

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19

Yiannopoulos, Konstantinos, Kyriakos G. Vlachos y Emmanouel Varvarigos. "Multiple-Input-Buffer and Shared-Buffer Architectures for Optical Packet- and Burst-Switching Networks". Journal of Lightwave Technology 25, n.º 6 (junio de 2007): 1379–89. http://dx.doi.org/10.1109/jlt.2007.896804.

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20

Li, Shuo, Xiaomeng Zhang y Saiyu Ren. "High Frequency Unity Gain Buffer in 90-nm CMOS Technology". Journal of Circuits, Systems and Computers 25, n.º 07 (22 de abril de 2016): 1650071. http://dx.doi.org/10.1142/s0218126616500717.

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A new unity gain buffer architecture is presented for on-chip CMOS mixed signal applications. The proposed two-stage common source active load (CSAL) buffer with source feedback offers improved performance compared to previously published source follower and source-coupled differential-pair-based unity gain buffers. A 90-nm CMOS design ([Formula: see text] equals 1.2[Formula: see text]V) of the buffer has the following performance parameters. With [Formula: see text]/[Formula: see text] of 10 fF/250 fF, [Formula: see text] is 4.4[Formula: see text]GHz, low frequency gain is 0.16[Formula: see text]dB, maximum input range within 2% gain variation is 260[Formula: see text]mV, total harmonic distortion (THD) is [Formula: see text]63.3[Formula: see text]dB, offset error (input offset minus output offset) is 26[Formula: see text]mV, and 1.06[Formula: see text]mW power consumption. The active load, low gain amplifiers eliminate stability issues and any need for compensation capacitors. The architecture facilitates a relatively large input/output voltage swing while keeping transistors operating in the saturation region, making it suitable for submicron technologies with low rail voltages.

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21

Huang, Xing Fa, Rong Bin Hu y Liang Li. "A CMOS Input Buffer for High-Resolution A/D Converters with High Sampling Rates". Applied Mechanics and Materials 678 (octubre de 2014): 497–500. http://dx.doi.org/10.4028/www.scientific.net/amm.678.497.

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With respect to the application of high-speed, high-resolution A/D converter, the design and implementation of a CMOS input buffer is introduced. The buffer features high-speed and high-linearity. Its performances have been verified in a 14-bit 250MSPS pipelined A/D converter which is developed in 0.18um CMOS-based process technology. The simulation shows that the SFDR of the buffer is up to 104dB at an input clock of 250MHz with an input signal of 25MHz.

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22

GRAMMATIKAKIS, MILTOS D., ERIC FLEURY y MIRO KRAETZL. "CONTINUOUS ROUTING IN PACKET SWITCHES". International Journal of Foundations of Computer Science 09, n.º 02 (junio de 1998): 121–37. http://dx.doi.org/10.1142/s0129054198000106.

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Considering continuous routing, we analyze the transient behavior of n×n routers with input buffering, split input buffering, output buffering, and central buffering with dedicated virtual circuits, one for each source-destination pair in a network. Assuming similar buffer space requirements, output buffering has the highest throughput. Split input buffering and central buffering have comparable performance; split input buffering slightly outperforms central buffering for large switches. Input buffering is known to saturate at packet generating rates above 0.586. By extending these models, two 1024-node, unique-path multistage networks configured with (approximately-modeled) input buffered STC104 32×32 switches, or central buffered Telegraphos 4×4 switches (Telegraphos I version) are compared. Surprisingly, the network configured with smaller switches performs better. This is due to the higher peak bandwidth of the Telegraphos switch and saturation of the input buffered STC104 switch.

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23

Sequeira, Luis, Julián Fernández-Navajas, Jose Saldana, José Ramón Gállego y María Canales. "Describing the Access Network by means of Router Buffer Modelling: A New Methodology". Scientific World Journal 2014 (2014): 1–9. http://dx.doi.org/10.1155/2014/238682.

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The behaviour of the routers’ buffer may affect the quality of service (QoS) of network services under certain conditions, since it may modify some traffic characteristics, as delay or jitter, and may also drop packets. As a consequence, the characterization of the buffer is interesting, especially when multimedia flows are transmitted and even more if they transport information with real-time requirements. This work presents a new methodology with the aim of determining the technical and functional characteristics of real buffers (i.e., behaviour, size, limits, and input and output rate) of a network path. It permits the characterization of intermediate buffers of different devices in a network path across the Internet.

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24

Li, Peng, Jonathan C. Beard y Jeremy D. Buhler. "Deadlock-free buffer configuration for stream computing". International Journal of High Performance Computing Applications 31, n.º 5 (20 de diciembre de 2016): 441–50. http://dx.doi.org/10.1177/1094342016675679.

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Stream computing is a popular paradigm for parallel and distributed computing, where compute nodes are connected by first-in first-out data channels. Each channel can be considered as a concatenation of several data buffers, including an output buffer for the sender and an input buffer for the receiver. The configuration of buffer sizes impacts the performance as well as the correctness of the application. In this article, we focus on application deadlocks that are caused by incorrect configuration of buffer sizes. We describe three types of deadlock in streaming applications, categorized by how they can be created. To avoid them, we first prove necessary and sufficient conditions for deadlock-free computations; then based on the theorems, we propose both compile-time and runtime solutions for deadlock avoidance.

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25

Jankowski, Mariusz y Andrzej Napieralski. "High-voltage high input impedance unity-gain voltage buffer". Microelectronics Journal 44, n.º 7 (julio de 2013): 576–85. http://dx.doi.org/10.1016/j.mejo.2013.03.006.

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26

Changsik Yoo, Min-Kyu Kim y Wonchan Kim. "A static power saving TTL-to-CMOS input buffer". IEEE Journal of Solid-State Circuits 30, n.º 5 (mayo de 1995): 616–20. http://dx.doi.org/10.1109/4.384180.

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27

Kumar, R., V. K. Garg y S. I. Marcus. "Finite buffer realization of input-output discrete-event systems". IEEE Transactions on Automatic Control 40, n.º 6 (junio de 1995): 1042–53. http://dx.doi.org/10.1109/9.388681.

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28

Del Grosso, C., G. Antoniol, E. Merlo y P. Galinier. "Detecting buffer overflow via automatic test input data generation". Computers & Operations Research 35, n.º 10 (octubre de 2008): 3125–43. http://dx.doi.org/10.1016/j.cor.2007.01.013.

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29

Kumar, Anuj y Rabi N. Mahapatra. "An integrated scheduling and buffer management scheme for input queued switches with finite buffer space". Computer Communications 29, n.º 1 (diciembre de 2005): 42–51. http://dx.doi.org/10.1016/j.comcom.2005.03.006.

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30

DEVILLERS, OLIVIER y PHILIPPE GUIGUE. "THE SHUFFLING BUFFER". International Journal of Computational Geometry & Applications 11, n.º 05 (octubre de 2001): 555–72. http://dx.doi.org/10.1142/s021819590100064x.

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The complexity of randomized incremental algorithms is analyzed with the assumption of a random order of the input. To guarantee this hypothesis, the n data have to be known in advance in order to be mixed what contradicts with the on-line nature of the algorithm. We present the shuffling buffer technique to introduce sufficient randomness to guarantee an improvement on the worst case complexity by knowing only k data in advance. Typically, an algorithm with O(n2) worst-case complexity and O(n) or O(n log n) randomized complexity has an [Formula: see text] complexity for the shuffling buffer. We illustrate this with binary search trees, the number of Delaunay triangles or the number of trapezoids in a trapezoidal map created during an incremental construction.

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31

LU, CHIH-WEN. "LOW-POWER HIGH-SPEED CLASS-AB BUFFER AMPLIFIERS FOR LIQUID-CRYSTAL DISPLAY SIGNAL DRIVER APPLICATION". Journal of Circuits, Systems and Computers 11, n.º 04 (agosto de 2002): 427–44. http://dx.doi.org/10.1142/s0218126602000550.

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Two types of low-power, high-speed, but with a large input dynamic range and output swing class-AB output buffer amplifiers which are suitable for the liquid-crystal display signal driver application are proposed. The driving capabilities of the circuits are achieved by adding comparators which sense the rising and falling edges of the input waveform and then turn on an auxiliary driving transistor to help charging/discharging the output load. The auxiliary driving transistors stay at "off" in the stable state, thus drawing no static power. Hence, the buffers draw little current during static but have an improved driving capability during transients. They are demonstrated in a 0.6 μm CMOS technology. The measured data do show that the proposed output buffer circuits are very suitable for the application of liquid-crystal display signal driver.

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32

C.D., Jaidhar y A. V. Reddy. "Efficient Variable Length Block Switching Mechanism". International Journal of Computers Communications & Control 2, n.º 3 (1 de septiembre de 2007): 269. http://dx.doi.org/10.15837/ijccc.2007.3.2359.

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Most popular and widely used packet switch architecture is the crossbar. Its attractive characteristics are simplicity, non-blocking and support for simultaneous multiple packet transmission across the switch. The special version of crossbar switch is Combined Input Crossbar Queue (CICQ) switch. It overcomes the limitations of un-buffered crossbar by employing buffers at each crosspoint in addition to buffering at each input port. Adoption of Crosspoint Buffer (CB) simplifies the scheduling complexity and adapts the distributed nature of scheduling. As a result, matching operation is not needed. Moreover, it supports variable length packets transmission without segmentation. Native switching of variable length packet transmission results in unfairness. To overcome this unfairness, Fixed Length Block Transfer mechanism has been proposed. It has the following drawbacks: (a) Fragmented packets are reassembled at the Crosspoint Buffer (CB). Hence, minimum buffer requirement at each crosspoint is twice the maximum size of the block. When number of ports are more, existence of such a switch is infeasible, due to the restricted memory available in switch core. (b) Reassembly circuit at each crosspoint adds the cost of the switch. (c) Packet is eligible to transfer from CB to output only when the entire packet arrives at the CB, which increases the latency of the fragmented packet in the switch. To overcome these drawbacks, this paper presents Variable Length Block Transfer mechanism. It does not require internal speedup, segmentation and reassembly circuits. Using simulation it is shown that proposed mechanism is superior to Fixed Length Block Transfer mechanism in terms of delay and throughput.

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33

Li, Liang, Xing Fa Huang, Ming Yuan Xu, Xiao Feng Shen y Xi Chen. "A Novel Input Buffer Used for SHA-Less Pipeline ADC". Applied Mechanics and Materials 678 (octubre de 2014): 501–4. http://dx.doi.org/10.4028/www.scientific.net/amm.678.501.

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This paper discussed a input buffer structure with replica load, analysed its theory of improving input signal linearity and decreasing distortion, gived some circuit embodiments, one of which was used for a 12-bit 500MSPS SHA-less ADC based on BiCMOS technolgy, Spurious Free Dynamic Range (SFDR) reached above 90dB with a 250MHz input signal.

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34

Chan, F. T. S. "Evaluation of combined dispatching and routeing strategies for a flexible manufacturing system". Proceedings of the Institution of Mechanical Engineers, Part B: Journal of Engineering Manufacture 216, n.º 7 (1 de julio de 2002): 1033–46. http://dx.doi.org/10.1243/09544050260174229.

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This paper is concerned with the evaluation of combined dispatching and routeing strategies on the performance of a flexible manufacturing system. Three routeing policies: no alternative routeings, alternative routeings dynamic and alternative routeings planned are considered with four dispatching rules with finite buffer capacity. In addition, the effect of changing part mix ratios is also discussed. The performance measures considered are makespan, average machine utilization, average flow time and average delay at local input buffers. Simulation results indicate that the alternative routeings dynamic policy gives the best results in three performance measures except for average delay at local input buffers. Further, the effect of changing part mix ratios is not significant.

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35

Katsuki, A., T. Hashimoto y T. Matsunaga. "Electronic Choke Having High Input-Impedance Buffer and Signal Canceller". Journal of the Magnetics Society of Japan 32, n.º 3 (2008): 424–29. http://dx.doi.org/10.3379/msjmag.32.424.

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36

Van Dijk, Nico M. "An LCFS finite buffer model with finite source batch input". Journal of Applied Probability 26, n.º 2 (junio de 1989): 372–80. http://dx.doi.org/10.2307/3214042.

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Queueing systems are studied with a last-come, first-served queueing discipline and batch arrivals generated by a finite number of non-exponential sources. A closed-form expression is derived for the steady-state queue length distribution. This expression has a scaled geometric form and is insensitive to the input distribution. Moreover, an algorithm for the recursive computation of the normalizing constant and the busy source distribution is presented. The results are of both practical and theoretical interest as an extension of the standard Poisson batch input case.

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37

Diab, H., H. Tabbara y N. Mansour. "Simulation of dynamic input buffer space in multistage interconnection networks". Advances in Engineering Software 31, n.º 1 (enero de 2000): 13–24. http://dx.doi.org/10.1016/s0965-9978(99)00025-3.

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38

Massoulie, Laurent y Alain Simonian. "Large buffer asymptotics for the queue with fractional Brownian input". Journal of Applied Probability 36, n.º 03 (septiembre de 1999): 894–906. http://dx.doi.org/10.1017/s0021900200017654.

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In this paper, a strong asymptotic estimate for the queue content distribution of a fluid queue fed by a fractional Brownian input with Hurst parameter H ∊ [1/2,1[is studied. By applying general results on suprema of centred Gaussian processes, in particular, we show that for large x. Explicit formulae for constants κ, γ and L are given in terms of H and system parameters.

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39

Van Dijk, Nico M. "An LCFS finite buffer model with finite source batch input". Journal of Applied Probability 26, n.º 02 (junio de 1989): 372–80. http://dx.doi.org/10.1017/s0021900200027352.

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Queueing systems are studied with a last-come, first-served queueing discipline and batch arrivals generated by a finite number of non-exponential sources. A closed-form expression is derived for the steady-state queue length distribution. This expression has a scaled geometric form and is insensitive to the input distribution. Moreover, an algorithm for the recursive computation of the normalizing constant and the busy source distribution is presented. The results are of both practical and theoretical interest as an extension of the standard Poisson batch input case.

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40

Sabaa, Amr, Fayez ElGuibaly y Dale Shpak. "Design and modelling of a nonlocking input-buffer ATM switch". Canadian Journal of Electrical and Computer Engineering 22, n.º 3 (julio de 1997): 87–93. http://dx.doi.org/10.1109/cjece.1997.7102138.

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41

Kim, Ji-Min, Chan-Young Park, Yu-Seop Kim, Hye-Jeong Song y Jong-Dae Kim. "Input Impedance Calibration of Buffer-less Thermistor Temperature Measurement System". International Journal of Control and Automation 6, n.º 6 (31 de diciembre de 2013): 413–22. http://dx.doi.org/10.14257/ijca.2013.6.6.39.

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42

Fan, Ruixue, Minoru Akiyama y Yoshiaki Tanaka. "An input buffer-type ATM switching system using schedule comparison". Electronics and Communications in Japan (Part I: Communications) 74, n.º 11 (noviembre de 1991): 17–25. http://dx.doi.org/10.1002/ecja.4410741102.

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43

Jiang Xie y Chin-Tau Lea. "Speedup and buffer division in input/output queuing atm switches". IEEE Transactions on Communications 51, n.º 7 (julio de 2003): 1195–203. http://dx.doi.org/10.1109/tcomm.2003.814208.

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44

Duque-Carrillo, J. F. y R. Perez-Aloe. "High-bandwidth CMOS test buffer with very small input capacitance". Electronics Letters 26, n.º 25 (1990): 2084. http://dx.doi.org/10.1049/el:19901343.

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45

Tsukada, M., J. Nishikido, Y. Shimazu, A. Misawa y H. Nakano. "Experiments on photonic cell switching with an optical input buffer". Electronics Letters 30, n.º 13 (23 de junio de 1994): 1081–82. http://dx.doi.org/10.1049/el:19940710.

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46

Massoulie, Laurent y Alain Simonian. "Large buffer asymptotics for the queue with fractional Brownian input". Journal of Applied Probability 36, n.º 3 (septiembre de 1999): 894–906. http://dx.doi.org/10.1239/jap/1032374642.

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In this paper, a strong asymptotic estimate for the queue content distribution of a fluid queue fed by a fractional Brownian input with Hurst parameter H ∊ [1/2,1[is studied. By applying general results on suprema of centred Gaussian processes, in particular, we show that for large x. Explicit formulae for constants κ, γ and L are given in terms of H and system parameters.

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47

Yang, Shuna y Norvald Stol. "A novel delay line buffering architecture for asynchronous optical packet switched networks". International Journal of Information, Communication Technology and Applications 1, n.º 1 (9 de marzo de 2015): 69–82. http://dx.doi.org/10.17972/ajicta20151112.

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Optical buffering is one major challenge in realizing all-optical packet switching. In this paper we focus on a delay-line buffer architecture, named a Multiple-Input Single-Output (MISO) optical buffer, which is realized by cascaded fiber delay lines (FDLs). This architecture reduces the physical size of a buffer by up to an order of magnitude or more by allowing reuse of its delay line elements. We consider the MISO buffers in a network scenario where the incoming packets are asynchronous and of fixed length. A novel Markov model is developed to analyze the performance of our buffering scheme, in terms of packet loss ratio, average packet delay and the output link utilization. Both simulation and analytical results show that the length value of basic FDL element will significantly affect the performance of this buffer. This paper gives clear guidelines for designing optimal basic FDL lengths under different network scenarios. It is noticeable that this optimal length value is independent of the buffer sizes for specific traffic load and pattern.

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48

Martínez-Nieto, Javier, María Sanz-Pascual, Nicolás Medrano-Marqués, Belén Calvo-López y Arturo Sarmiento-Reyes. "High-Linearity Self-Biased CMOS Current Buffer". Electronics 7, n.º 12 (11 de diciembre de 2018): 423. http://dx.doi.org/10.3390/electronics7120423.

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A highly linear fully self-biased class AB current buffer designed in a standard 0.18 μ m CMOS process with 1.8 V power supply is presented in this paper. It is a simple structure that, with a static power consumption of 48 μ W, features an input resistance as low as 89 Ω , high accuracy in the input–output current ratio and total harmonic distortion (THD) figures lower than −60 dB at 30 μ A amplitude signal and 1 kHz frequency. Robustness was proved through Monte Carlo and corner simulations, and finally validated through experimental measurements, showing that the proposed configuration is a suitable choice for high performance low voltage low power applications.

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49

Ott, Teunis J. y J. George Shanthikumar. "On a buffer problem for packetized voice with an N-periodic strongly interchangeable input process". Journal of Applied Probability 28, n.º 3 (septiembre de 1991): 630–46. http://dx.doi.org/10.2307/3214497.

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Consider a slotted communication channel which carries packetized voice and which can transmit exactly one packet every timeslot. Assume that every conversation routed over this channel generates exactly one packet every N timeslots. We study, for the case of an infinite buffer and an N-periodic strongly interchangeable input process, buffer behavior and packet delays as functions of the number of calls routed over the channel, as long as that number is less than or equal to N. Among our results are a simple algorithm which computes the marginal distribution of the buffer content and an algorithm with complexity of order N4 which computes the distribution of the maximal buffer content (over a period of N timeslots).

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50

Ott, Teunis J. y J. George Shanthikumar. "On a buffer problem for packetized voice with an N-periodic strongly interchangeable input process". Journal of Applied Probability 28, n.º 03 (septiembre de 1991): 630–46. http://dx.doi.org/10.1017/s0021900200042479.

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Consider a slotted communication channel which carries packetized voice and which can transmit exactly one packet every timeslot. Assume that every conversation routed over this channel generates exactly one packet every N timeslots. We study, for the case of an infinite buffer and an N-periodic strongly interchangeable input process, buffer behavior and packet delays as functions of the number of calls routed over the channel, as long as that number is less than or equal to N. Among our results are a simple algorithm which computes the marginal distribution of the buffer content and an algorithm with complexity of order N 4 which computes the distribution of the maximal buffer content (over a period of N timeslots).

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