Tesis sobre el tema "Integrated circuits Very large scale integration"
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Hong, Won-kook. "Single layer routing : mapping topological to geometric solutions." Thesis, McGill University, 1986. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=66030.
Texto completoMatsumori, Barry Alan. "QUALIFICATION RESEARCH FOR RELIABLE, CUSTOM LSI/VLSI ELECTRONICS." Thesis, The University of Arizona, 1985. http://hdl.handle.net/10150/275313.
Texto completoJafar, Mutaz 1960. "THERMAL MODELING/SIMULATION OF LEVEL 1 AND LEVEL 2 VLSI PACKAGING." Thesis, The University of Arizona, 1986. http://hdl.handle.net/10150/276959.
Texto completoVoranantakul, Suwan 1962. "CONDUCTIVE AND INDUCTIVE CROSSTALK COUPLING IN VLSI PACKAGES." Thesis, The University of Arizona, 1986. http://hdl.handle.net/10150/277037.
Texto completoDagenais, Michel R. "Timing analysis for MOSFETS, an integrated approach." Thesis, McGill University, 1987. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=75459.
Texto completoLiu, Yansong. "Passivity checking and enforcement in VLSI model reduction exercise." Click to view the E-thesis via HKUTO, 2008. http://sunzi.lib.hku.hk/hkuto/record/B41290690.
Texto completoHong, Seong-Kwan. "Performance driven analog layout compiler." Diss., Georgia Institute of Technology, 1994. http://hdl.handle.net/1853/15037.
Texto completoDavis, Jeffrey Alan. "A hierarchy of interconnect limits and opportunities for gigascale integration (GSI)." Diss., Georgia Institute of Technology, 1999. http://hdl.handle.net/1853/15803.
Texto completoAnbalagan, Pranav. "Limitations and opportunities for wire length prediction in gigascale integration." Diss., Atlanta, Ga. : Georgia Institute of Technology, 2007. http://hdl.handle.net/1853/22670.
Texto completoIvanov, André. "Dynamic testibility measures and their use in ATPG." Thesis, McGill University, 1985. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=63324.
Texto completoZhao, Wenhui, and 趙文慧. "Efficient circuit simulation via adaptive moment matching and matrix exponential techniques." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 2013. http://hdl.handle.net/10722/197488.
Texto completoHum, Herbert Hing-Jing. "A linear unification processor /." Thesis, McGill University, 1987. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=63790.
Texto completoChu, Chung-kwan, and 朱頌君. "Computationally efficient passivity-preserving model order reduction algorithms in VLSI modeling." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 2007. http://hub.hku.hk/bib/B38719551.
Texto completoVenkatesan, Raguraman. "Multilevel interconnect architectures for gigascale integration (GSI)." Diss., Georgia Institute of Technology, 2003. http://hdl.handle.net/1853/13370.
Texto completoNarayanan, Prakash. "Analytical modeling and simulation of bicmos for VLSI circuits." Thesis, Virginia Tech, 1990. http://hdl.handle.net/10919/42199.
Texto completo張永泰 and Wing-tai Cheung. "Geometric programming and signal flow graph assisted design of interconnect and analog circuits." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 2007. http://hub.hku.hk/bib/B39558526.
Texto completoWilson, Denise M. "Analog VLSI architecture for chemical sensing microsystems." Diss., Georgia Institute of Technology, 1995. http://hdl.handle.net/1853/13322.
Texto completoPeckel, Marcos David. "A MOS delay model for switch-level simulation /." Thesis, McGill University, 1985. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=65990.
Texto completoPanda, Uma R. "An efficient single-latch scan-design scheme/." Thesis, McGill University, 1985. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=63266.
Texto completoKRISHT, MUHAMMED HUSSEIN, and MUHAMMED HUSSEIN KRISHT. "LPCVD TUNGSTEN MULTILAYER METALLIZATION FOR VLSI SYSTEMS." Diss., The University of Arizona, 1985. http://hdl.handle.net/10150/187983.
Texto completoKarunaratne, Maddumage Don Gamini. "An intelligent function level backward state justification search for ATPG." Diss., The University of Arizona, 1989. http://hdl.handle.net/10150/184921.
Texto completoHowells, Michael C. "A cluster-proof approach to yield enhancement of large area binary tree architectures /." Thesis, McGill University, 1987. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=66194.
Texto completoGeller, Ronnie Dee. "A VLSI architecture for a neurocomputer using higher-order predicates." Full text open access at:, 1987. http://content.ohsu.edu/u?/etd,137.
Texto completoAl-Mahmood, Saiyid Jami Islah Ahmad. "A distributed design rule checker for VLSI layouts." Thesis, This resource online, 1990. http://scholar.lib.vt.edu/theses/available/etd-11012008-063423/.
Texto completoTyagi, Dhawal. "TENOR : an ATPG for transition faults in combinational circuits /." Thesis, This resource online, 1994. http://scholar.lib.vt.edu/theses/available/etd-06302009-040525/.
Texto completoKelley, Brian T. "VLSI computing architectures for high speed seismc migration." Diss., Georgia Institute of Technology, 1992. http://hdl.handle.net/1853/13919.
Texto completoBragg, Julian Alexander. "A biomorphic analog VLSI implementation of a mammalian motor unit." Diss., Georgia Institute of Technology, 2002. http://hdl.handle.net/1853/20693.
Texto completoTan, Chong Guan. "Another approach to PLA folding." Thesis, McGill University, 1985. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=66054.
Texto completo高雲龍 and Wan-lung Ko. "A new optimization model for VLSI placement." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 1998. http://hub.hku.hk/bib/B29812938.
Texto completoRasafar, Hamid 1954. "THE HIGH FREQUENCY AND TEMPERATURE DEPENDENCE OF DIELECTRIC PROPERTIES OF PRINTED CIRCUIT BOARD MATERIALS." Thesis, The University of Arizona, 1987. http://hdl.handle.net/10150/276509.
Texto completoChen, Ing-yi 1962. "Efficient reconfiguration by degradation in defect-tolerant VLSI arrays." Thesis, The University of Arizona, 1989. http://hdl.handle.net/10150/277195.
Texto completoHolland, Kenneth Chris. "Probability of latching single event upset errors in VLSI circuits." Thesis, Virginia Tech, 1991. http://hdl.handle.net/10919/41980.
Texto completoLiu, Yansong, and 劉岩松. "Passivity checking and enforcement in VLSI model reduction exercise." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 2008. http://hub.hku.hk/bib/B41290690.
Texto completoLee, Hoi-Ming Bonny 1961. "The evaluation of the PODEM algorithm as a mechanism to generate goal states for a sequential circuit test search." Thesis, The University of Arizona, 1988. http://hdl.handle.net/10150/276730.
Texto completoTang, Maolin. "Intelligent approaches to VLSI routing." Thesis, Edith Cowan University, Research Online, Perth, Western Australia, 2000. https://ro.ecu.edu.au/theses/1375.
Texto completoWhipple, Thomas Driggs 1961. "Design and implementation of an integrated VLSI packaging support software environment." Thesis, The University of Arizona, 1989. http://hdl.handle.net/10150/277105.
Texto completoKhordoc, Karim. "A MOS switch-level simulator with delay calculation /." Thesis, McGill University, 1986. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=65461.
Texto completoBishop, Gregory Raymond H. ""On stochastic modelling of very large scale integrated circuits : an investigation into the timing behaviour of microelectronic systems" /." Title page, contents and abstract only, 1993. http://web4.library.adelaide.edu.au/theses/09PH/09phb6222.pdf.
Texto completoKosaraju, Chakravarthy S. "A set of behavioral modeling primitives." Thesis, Virginia Tech, 1990. http://hdl.handle.net/10919/41989.
Texto completoCho, Chang H. "A formal model for behavioral test generation." Diss., This resource online, 1994. http://scholar.lib.vt.edu/theses/available/etd-06062008-170406/.
Texto completoDeng, Chaodan. "Process development for si-based nanostructures using pulsed UV laser induced epitaxy." Full text open access at:, 1995. http://content.ohsu.edu/u?/etd,206.
Texto completoMoini, Alireza. "Synthesis of biological vision models using analog VLSI /." Title page, contents and abstract only, 1997. http://web4.library.adelaide.edu.au/theses/09PH/09phm712.pdf.
Texto completoTan, Wei-Siong. "A VLSI parallel processor structure for scientific computing." Diss., Georgia Institute of Technology, 1989. http://hdl.handle.net/1853/13455.
Texto completoPatel, Girish N. "A neuromorphic architecture for modeling intersegmental coordination." Diss., Georgia Institute of Technology, 1999. http://hdl.handle.net/1853/13528.
Texto completoGordon, Christal. "An adaptive floating-gate network using action-potential signaling." Thesis, Georgia Institute of Technology, 2000. http://hdl.handle.net/1853/15683.
Texto completoMăndoiu, Ion I. "Approximation algorithms for VLSI routing." Diss., Georgia Institute of Technology, 2000. http://hdl.handle.net/1853/9128.
Texto completo梁迅中 and Shun-chung Leung. "Silicon compiler for bit-serial signal processing architecture with automatic time alignment." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 1987. http://hub.hku.hk/bib/B31207741.
Texto completo袁志勤 and Chi-kan Yuen. "A double-track greedy algorithm for VLSI channel routing." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 1997. http://hub.hku.hk/bib/B31220241.
Texto completoMa, Min. "Model order reduction for efficient modeling and simulation of interconnect networks." Thesis, McGill University, 2007. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=103269.
Texto completoShope, David Allen 1958. "Thermal characterization of VLSI packaging." Thesis, The University of Arizona, 1988. http://hdl.handle.net/10150/276686.
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