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Tesis sobre el tema "Interconnects (Integrated circuit technology) Copper"

Autor: Grafiati

Publicado: 4 de junio de 2021

Última modificación: 18 de febrero de 2022

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1

Osborn, Tyler Nathaniel. "All-copper chip-to-substrate interconnects for high performance integrated circuit devices." Diss., Atlanta, Ga. : Georgia Institute of Technology, 2009. http://hdl.handle.net/1853/28211.

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Thesis (M. S.)--Chemical Engineering, Georgia Institute of Technology, 2009.<br>Committee Chair: Kohl, Paul; Committee Member: Bidstrup Allen, Sue Ann; Committee Member: Fuller, Thomas; Committee Member: Hesketh, Peter; Committee Member: Hess, Dennis; Committee Member: Meindl, James.

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2

Wu, Fangyu. "Hydrogen-based plasma etch of copper at low temperature." Diss., Georgia Institute of Technology, 2011. http://hdl.handle.net/1853/43617.

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Although copper (Cu) is the preferred interconnect material due to its lower resistivity than aluminum (Al), Cu subtractive etching processes have not been developed at temperatures less than 180 °C, primarily due to the inability to form volatile etch products at low temperature. The conventional damascene technology avoids the need for subtractive etching of Cu by electroplating Cu into previously etched dielectric trenches/vias, followed by a chemical/mechanical planarization (CMP) process. However, a critical "size effect" limitation has arisen for damascene technology as a result of the c

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3

Darmakkolla, Srikar Rao. "Copper Nanowires Synthesis and Self-Assembly for Interconnect Applications." PDXScholar, 2017. https://pdxscholar.library.pdx.edu/open_access_etds/4034.

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One-dimensional (1D) nanomaterial self-assembly offers an excellent approach to the fabrication of highly complex nanodevices. Despite considerable effort and research, precisely controlling the orientation and positioning of nanowires (NWs) on a large-scale area and assembling into a functional device is still a state of the art problem. This thesis focuses on the dimensionally controlled copper nanowires (Cu NWs) synthesis, and magnetic field assisted self-assembly of cupronickel nanowires (Cu/Ni NWs) into interconnect structures on a carbon doped silicon dioxide (CDO) wafer. CDO is a low di

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4

Jha, Gopal Chandra. "Copper to copper bonding by nano interfaces for fine pitch interconnections and thermal applications." Thesis, Atlanta, Ga. : Georgia Institute of Technology, 2008. http://hdl.handle.net/1853/22588.

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5

Khan, Sadia Arefin. "Electromigration analysis of high current carrying adhesive-based copper-to-copper interconnections." Thesis, Georgia Institute of Technology, 2012. http://hdl.handle.net/1853/44885.

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"More Than Moore's Law" is the driving principle for the electronic packaging industry. This principle focuses on system integration instead of transistor density in order to achieve faster, thinner, and smarter electronic devices at a low cost. A core area of electronics packaging is interconnection technology, which enables ultra-miniaturization and high functional density. Solder bump technology is one of the original, and most common interconnection methods for flip chips. With growing demand for finer pitch and higher number of I/Os, solder bumps have been forced to smaller dimensions and

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6

Koh, Sau W. "Fatigue modeling of nano-structured chip-to-package interconnections." Diss., Atlanta, Ga. : Georgia Institute of Technology, 2009. http://hdl.handle.net/1853/28263.

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Thesis (M. S.)--Materials Science and Engineering, Georgia Institute of Technology, 2009.<br>Committee Chair: Rao R. Tummala; Committee Co-Chair: Ashok Saxena; Committee Member: Karl Jacob; Committee Member: Suresh Sitaraman; Committee Member: Thomas H. Sanders, Jr.

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7

Okereke, Raphael Ifeanyi. "Electroplated multi-path compliant copper interconnects for flip-chip packages." Diss., Georgia Institute of Technology, 2014. http://hdl.handle.net/1853/51800.

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The international technology roadmap for semiconductors (ITRS) 2012 report foresees the use of porous dielectric materials with a low dielectric constant in conjunction with copper interconnects as a way to reduce the resistive-capacitive (RC) delay in microelectronic applications. However, the introduction of pores in the dielectric not only serves as stress raisers but also diminishes the structural strength of the material. The challenge therefore with the implementation of low-k dielectrics for high-performance flip-chip packages is to create a reliable die to organic substrate interconnec

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8

Mehrotra, Gaurav. "Ultra thin ultrafine-pitch chip-package interconnections for embedded chip last approach." Thesis, Atlanta, Ga. : Georgia Institute of Technology, 2008. http://hdl.handle.net/1853/22594.

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9

Mistkawi, Nabil George. "Fundamental Studies in Selective Wet Etching and Corrosion Processes for High-Performance Semiconductor Devices." PDXScholar, 2010. https://pdxscholar.library.pdx.edu/open_access_etds/6.

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As multistep, multilayer processing in semiconductor industry becomes more complex, the role of cleaning solutions and etching chemistries are becoming important in enhancing yield and in reducing defects. This thesis demonstrates successful formulations that exhibit copper and tungsten compatibility, and are capable of Inter Layer Dielectric (ILD) cleaning and selective Ti etching. The corrosion behavior of electrochemically deposited copper thin films in deareated and non-dearated cleaning solution containing hydrofluoric acid (HF) has been investigated. Potentiodynamic polarization experime

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10

Lopez, Gerald Gabriel. "The impact of interconnect process variations and size effects for gigascale integration." Diss., Atlanta, Ga. : Georgia Institute of Technology, 2009. http://hdl.handle.net/1853/31781.

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Thesis (Ph.D)--Electrical and Computer Engineering, Georgia Institute of Technology, 2010.<br>Committee Chair: Jeffrey A. Davis; Committee Co-Chair: James D. Meindl; Committee Member: Azad J. Naeemi; Committee Member: Dennis W. Hess; Committee Member: George F. Riley; Committee Member: Linda S. Milor. Part of the SMARTech Electronic Thesis and Dissertation Collection.

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11

Lin, Ta-Hsuan. "Assembly process development, reliability and numerical assessment of copper column flexible flip chip technology." Diss., Online access via UMI:, 2008.

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Thesis (Ph. D.)--State University of New York at Binghamton, Department of Systems Science and Industrial Engineering, Thomas J. Watson School of Engineering and Applied Science, 2008.<br>Includes bibliographical references.

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12

Honrao, Chinmay. "Fine-pitch Cu-snag die-to-die and die-to-interposer interconnections using advanced slid bonding." Thesis, Georgia Institute of Technology, 2013. http://hdl.handle.net/1853/50333.

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Multi-chip integration with emerging technologies such as a 3D IC stack or 2.5D interposer is primarily enabled by the off-chip interconnections. The I/O density, speed and bandwidth requirements for emerging mobile and high-performance systems are projected to drive the interconnection pitch to less than 20 microns by 2015. A new class of low-temperature, low-pressure, high-throughput, cost-effective and maufacturable technologies are needed to enable such fine-pitch interconnections. A range of interconnection technologies are being pursued to achieve these fine-pitch interconnections, most

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13

Choudhury, Abhishek. "Chip-last embedded low temperature interconnections with chip-first dimensions." Thesis, Georgia Institute of Technology, 2010. http://hdl.handle.net/1853/37104.

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Small form-factor packages with high integration density are driving the innovations in chip-to-package interconnections. Metallurgical interconnections have evolved from the conventional eutectic and lead-free solders to fine pitch copper pillars with lead-free solder cap. However, scaling down the bump pitch below 50-80µm and increasing the interconnect density with this approach creates a challenge in terms of accurate solder mask lithography and joint reliability with low stand-off heights. Going beyond the state of the art flip-chip interconnection technology to achieve ultra-fine bump pi

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14

Bin, Hashim Aeffendi Helmi. "Polymer photonic interconnects." Thesis, University of Cambridge, 2012. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.610796.

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15

Naeemi, Azad. "Analysis and optimization for global interconnects for gigascale integration (GSI)." Diss., Available online, Georgia Institute of Technology, 2004:, 2003. http://etd.gatech.edu/theses/available/etd-04072004-180121/unrestricted/naeemi%5Fazad%5F200312%5Fphd.pdf.

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16

Sekar, Deepak Chandra. "Optimal signal, power, clock and thermal interconnect networks for high-performance 2d and 3d integrated circuits." Diss., Atlanta, Ga. : Georgia Institute of Technology, 2008. http://hdl.handle.net/1853/26562.

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Thesis (Ph.D)--Electrical and Computer Engineering, Georgia Institute of Technology, 2009.<br>Committee Chair: Meindl, James; Committee Co-Chair: Davis, Jeffrey; Committee Member: Callen, Russell; Committee Member: Gaylord, Thomas; Committee Member: Kohl, Paul; Committee Member: Mukhopadhyay, Saibal. Part of the SMARTech Electronic Thesis and Dissertation Collection.

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17

Joyner, James W. "Opportunities and limitations of three-dimensional integration for interconnect design." Diss., Georgia Institute of Technology, 2003. http://hdl.handle.net/1853/13763.

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18

Kramer, Joshua. "A dynamic power optimization methodology for gigabit electrical links." Access to citation, abstract and download form provided by ProQuest Information and Learning Company; downloadable PDF file, 134 p, 2007. http://proquest.umi.com/pqdweb?did=1397913001&sid=3&Fmt=2&clientId=8331&RQT=309&VName=PQD.

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19

Bakir, Muhannad S. "Sea of Leads electrical-optical polymer pillar chip I/O interconnections for gigascale integration." Diss., Available online, Georgia Institute of Technology, 2004:, 2003. http://etd.gatech.edu/theses/available/etd-04082004-180010/unrestricted/bakir%5Fmuhannad%5Fs%5F200312%5Fphd.pdf.

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20

Villalaz, Ricardo A. "Volume Grating Couplers for Optical Interconnects: Analysis, Design, Fabrication, and Testing." Diss., Available online, Georgia Institute of Technology, 2004:, 2004. http://etd.gatech.edu/theses/available/etd-07102004-165012/unrestricted/villalaz%5Fricardo%5Fa%5F200407%5Fphd.pdf.

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Thesis (Ph. D.)--School of Electrical and Computer Engineering, Georgia Institute of Technology, 2005. Directed by Thomas Gaylord.<br>Glytsis, Elias, Committee Co-Chair ; Buck, John, Committee Member ; Kohl, Paul, Committee Member ; Adibi, Ali, Committee Member ; Gaylord, Thomas, Committee Chair. Vita. Includes bibliographical references.

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21

Esconjauregui, Cruz Santiago. "Growth of carbon nanotubes for interconnects applications." Thesis, University of Cambridge, 2011. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.609620.

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22

Iqbal, Muzammil. "Intrachip global communication evaluation of challenges and optical solutions /." Access to citation, abstract and download form provided by ProQuest Information and Learning Company; downloadable PDF file, 209 p, 2007. http://proquest.umi.com/pqdweb?did=1251904841&sid=2&Fmt=2&clientId=8331&RQT=309&VName=PQD.

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23

Gupta, Piyush. "Effect of intermetallic compounds on thermomechanical reliability of lead-free solder interconnects for flip-chips." Thesis, Available online, Georgia Institute of Technology, 2004:, 2004. http://etd.gatech.edu/theses/available/etd-08202004-125146/unrestricted/gupta%5Fpiyush%5F200412%5Fmaster.pdf.

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Thesis (M.S.)--Materials Science and Engineering, Georgia Institute of Technology, 2005.<br>Suresh, Committee Member ; C.P. Wong, Committee Member ; Rao R. Tummala, Committee Chair. Includes bibliographical references.

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24

Chandrasekhar, Janani. "Signal to power coupling and noise induced jitter in differential signaling." Thesis, Atlanta, Ga. : Georgia Institute of Technology, 2008. http://hdl.handle.net/1853/24778.

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Thesis (M. S.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2008.<br>Committee Chair: Swaminathan Madhavan; Committee Member: Chatterjee Abhijit; Committee Member: Davis Jeffrey.

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25

Zhu, Qi. "Helix-type compliant off-chip interconnect for microelectronic packaging." Diss., Georgia Institute of Technology, 2003. http://hdl.handle.net/1853/17541.

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26

Chai, Yang. "Fabrication and characterization of carbon nanotubes for interconnect applications /." View abstract or full-text, 2009. http://library.ust.hk/cgi/db/thesis.pl?ECED%202009%20CHAI.

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27

Li, Yiming. "Plasma processing of advanced interconnects for microelectronic applications." Diss., Georgia Institute of Technology, 2002. http://hdl.handle.net/1853/11034.

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28

Leung, Lydia Lap Wai. "Low-loss on-chip interconnects for silicon integrated radio-frequency and microwave systems /." View abstract or full-text, 2005. http://library.ust.hk/cgi/db/thesis.pl?ELEC%202005%20LEUNG.

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29

Brenner, Kevin A. "Benchmarking and chemical doping techniques for nanoscale graphene interconnects." Diss., Georgia Institute of Technology, 2013. http://hdl.handle.net/1853/47581.

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The interconnect fabric that provides electrical connectivity to active devices is an essential component to modern semiconductor chips. As the dimensions of these devices are scaled to improve performance and keep pace with Moore's Law, the local Cu interconnects must scale in parallel. Intrinsic material properties of Cu result in spiking electrical resistivity with scaling and present a looming bottleneck to chip performance. In this thesis, we introduce graphene as a replacement material to Cu interconnects in support of future chip scaling. In particular we focus on experimentally est

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30

Haemer, Joseph Michael. "Thermo-mechanical modeling and design of micro-springs for microelectronic probing and packaging." Thesis, Georgia Institute of Technology, 2000. http://hdl.handle.net/1853/16830.

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31

Barrera-Gonzalez, Claudia Patricia. "Variable swing optimal parallel links minimal power, maximal density for parallel links /." Access to citation, abstract and download form provided by ProQuest Information and Learning Company; downloadable PDF file, 120 p, 2009. http://proquest.umi.com/pqdweb?did=1818417501&sid=11&Fmt=2&clientId=8331&RQT=309&VName=PQD.

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32

Kacker, Karan. "Design and fabrication of free-standing structures as off-chip interconnects for microsystems packaging." Diss., Atlanta, Ga. : Georgia Institute of Technology, 2008. http://hdl.handle.net/1853/26464.

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Thesis (Ph.D)--Mechanical Engineering, Georgia Institute of Technology, 2009.<br>Committee Chair: Dr. Suresh K. Sitaraman; Committee Member: Dr. F. Levent Degertekin; Committee Member: Dr. Ioannis Papapolymerou; Committee Member: Dr. Madhavan Swaminathan; Committee Member: Dr. Nazanin Bassiri-Gharb. Part of the SMARTech Electronic Thesis and Dissertation Collection.

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33

Rakheja, Shaloo. "Interconnects for post-CMOS devices: physical limits and device and circuit implications." Diss., Georgia Institute of Technology, 2012. http://hdl.handle.net/1853/45866.

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The objective of this dissertation is to classify the opportunities, advantages, and limits of novel interconnects for post-CMOS logic that can augment or eventually replace the CMOS logic. Post-CMOS devices are envisaged on the idea of using state variables other than the electron charge to store and manipulate information. In the first component of the thesis, a comprehensive analysis of the performance and the energy dissipation of novel logic based on various state variables is conducted, and it is demonstrated that the interconnects will continue to be a major challenge even for post-CMOS

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34

Qiao, Hao. "Sparse hierarchical model order reduction for high speed interconnects." Thesis, McGill University, 2009. http://digitool.Library.McGill.CA:8881/R/?func=dbin-jump-full&object_id=32359.

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35

Sundaresan, Krishnan. "Activity-aware modeling and design optimization of on-chip signal interconnects." Diss., Connect to online resource - MSU authorized users, 2006.

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Thesis (Ph. D.)--Michigan State University. Dept. of Electrical and Computer Engineering, 2006.<br>Title from PDF t.p. (viewed on Nov. 17, 2008) Includes bibliographical references (p. 183-195). Also issued in print.

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36

Chen, Quan. "Efficient numerical modeling of random surface roughness for interconnect internal impedance extraction." Click to view the E-thesis via HKUTO, 2007. http://sunzi.lib.hku.hk/HKUTO/record/B3955708X.

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37

Mule, Anthony Victor. "Volume grating coupler-based optical interconnect technologies for polylithic gigascale integration." Available online, Georgia Institute of Technology, 2004:, 2004. http://etd.gatech.edu/theses/available/etd-06072004-131259/unrestricted/mule%5Fanthony%5Fv%5F200405%5Fphd.pdf.

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38

Liu, Yansong. "Passivity checking and enforcement in VLSI model reduction exercise." Click to view the E-thesis via HKUTO, 2008. http://sunzi.lib.hku.hk/hkuto/record/B41290690.

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39

Jamadagni, Navaneeth Prasannakumar. "3-D modelling of IC interconnect using OpenAccess and Art of Illusion." PDXScholar, 2010. https://pdxscholar.library.pdx.edu/open_access_etds/28.

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In search of higher speed and integration, the integrated circuit (IC) technology is scaling down. The total on-chip interconnect length is increasing exponentially. In fact, interconnect takes up the most part of the total chip area. The parasitics associated with these interconnect have significant impact on the circuit performance. Some of the effects of parasitics include cross talk, voltage drop and high current density. These issues can result in cross-talk induced functional failure and failures due to IR drop and electro-migration. This has resulted in interconnect- driven design trend

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40

Sundaram, Venkatesh. "Advances in electronic packaging technologies by ultra-small microvias, super-fine interconnections and low loss polymer dielectrics." Diss., Atlanta, Ga. : Georgia Institute of Technology, 2009. http://hdl.handle.net/1853/28141.

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Thesis (M. S.)--Materials Science and Engineering, Georgia Institute of Technology, 2009.<br>Committee Chair: Tummala, Rao; Committee Member: Iyer, Mahadevan; Committee Member: Saxena, Ashok; Committee Member: Swaminathan, Madhavan; Committee Member: Wong, Chingping.

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41

Agnihotri, Ameya Ramesh. "Combinatorial optimization techniques for VLSI placement." Diss., Online access via UMI:, 2007.

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42

Mule, Anthony Victor. "Volume grating coupler-based optical interconnect technologies for polylithic gigascale integrat." Diss., Georgia Institute of Technology, 2004. http://hdl.handle.net/1853/9447.

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43

Huang, Zhaoran. "Multi gigahertz InGaAs/InP inverted MSM photodetectors for photoreceiver and waveguide applications." Diss., Georgia Institute of Technology, 2003. http://hdl.handle.net/1853/5412.

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44

Ma, Lunyu. "Design and development of stress-engineered compliant interconnect in microelectronic packaging." Diss., Georgia Institute of Technology, 2003. http://hdl.handle.net/1853/16066.

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45

Rydberg, Ray Robert. "A gasp of fresh air a high speed distributed FIFO scheme for managing interconnect parasitics /." Online access for everyone, 2005. http://www.dissertations.wsu.edu/Thesis/Spring2005/R%5FRydberg%5F050505.pdf.

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46

Xie, Rongsi. "Carbon nanotube growth for interconnect application." Thesis, University of Cambridge, 2014. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.648535.

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47

Zheng, Jiantao. "Interfacial fracture of micro thin film interconnects under monotonic and cyclic loading." Diss., Atlanta, Ga. : Georgia Institute of Technology, 2008. http://hdl.handle.net/1853/26489.

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Thesis (Ph. D.)--Mechanical Engineering, Georgia Institute of Technology, 2009.<br>Committee Chair: Sitaraman, Suresh; Committee Member: Degertekin, Levent; Committee Member: McDowell, David; Committee Member: Tummala, Rao; Committee Member: Vandentop, Gilroy; Committee Member: Wang, Zhong Lin. Part of the SMARTech Electronic Thesis and Dissertation Collection.

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48

He, Rongsen. "Indirect interconnection networks for high performance routers/switches." Online access for everyone, 2007. http://www.dissertations.wsu.edu/Dissertations/Summer2007/R_He_072307.pdf.

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49

Wu, Junwei. "Electrodeposition of manganese/cobalt alloys for solid oxide fuel cell interconnect applications." Morgantown, W. Va. : [West Virginia University Libraries], 2009. http://hdl.handle.net/10450/10611.

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Thesis (Ph. D.)--West Virginia University, 2009.<br>Title from document title page. Document formatted into pages; contains xiii, 163 p. : ill. (some col.). Includes abstract. Includes bibliographical references.

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50

Chen, Bingan. "Carbon nanotubes for adhesive, interconnect, and energy storage applications." Thesis, University of Cambridge, 2014. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.648440.

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