Tesis sobre el tema "Linear integrated circuits Operational amplifiers"

High-performance, high-frequency operational transconductance amplifiers (OTAs) are very important elements in the design of high-frequency continuous-time integrated analog signal processing circuits, because resistors, inductors, integrators, mutators, buffers, multipliers, and filters can be built by OTAs and capacitors. The critical considerations for OTA design are linearity, tuning, frequency response, output impedance, power supply rejection (PSR) and common-mode rejection (CMR). For linearity considerations, two different methods are proposed. One uses cross-coupled pairs (CMOS or NMOS), producing OTAs with very high linearity but either the input range is relatively small or the CMR to asymmetrical inputs is poor. Another employs multiple differential pairs (current addition or subtraction), producing OTAs with high linearity over a very large input range. So, there are tradeoffs among the critical considerations. For different applications, different OTAs should be selected. For consideration of frequency response, the first reported GaAs OTA was designed for achieving very-high-frequency performance, instead of using AC compensation techniques. GaAs is one of the fastest available technologies, but it was new and less mature than silicon when we started the design in 1989. So, there were several issues, such as low output impedance, no P-channel devices, and Schottky clamp. To overcome these problems, new techniques are proposed, and the designed OTA has comparable performance to a CMOS OTA. For PSR and CMR considerations, a fully balanced circuit structure is employed with a common-mode feedback (CMF) circuit used to stabilize the DC output voltages. To reduce the interaction of the operation of CMF and tuning of OTAs, three improved versions of the CMF circuits used in operational amplifiers are proposed. With the designed OTAs, a I GHz GaAs inductor with small parasitics is designed using the proposed procedure to reduce high-frequency effects. Two CMOS high-order, high-frequency filters are designed: one in cascade structure and one in LC ladder form. Also, a 200 MHz third-order elliptic GaAs filter is designed with special consideration of very-high-frequency parasitics. All circuits were fabricated and measured. The experimental results were used to verify the designs.

Thesis (Ph. D.)--School of Electrical and Computer Engineering, Georgia Institute of Technology, 2005. Directed by Phillip Allen.
Morley, Thomas, Committee Member ; Leach, Marshall, Committee Member ; Ayazi, Farrokh, Committee Member ; Rincon-Mora, Gabriel, Committee Member ; Allen, Phillip, Committee Chair. Includes bibliographical references.

Abstract Class A and class AB operational amplifiers are an essential part of a mixed- signal chip, where they are used as active filter sub-blocks, compensators, reference current generators and voltage buffers, to name just a few of many applications. For analog circuits such as operational amplifiers a mixed-signal chip is a very unfriendly operating environment, where the power supply is often corrupted by high current switching circuits. In addition, power supply voltages for analog blocks are shrinking, because of the deployment of new battery technologies and fine line length integrated circuit processes, which can reduce the amplifier dynamic range a problem requiring supply insensitive low voltage compatible amplifier topologies and other analog blocks. The aims of this thesis were to further develop the low voltage compatible class AB amplifier topologies published earlier by other authors, to improve their bandwidth efficiency by means of re-examining two- and three-stage amplifier compensation techniques and to find solutions for enhancing the high frequency power supply noise rejection performance of class A and class AB amplifiers without degrading their signal path stability. The class AB amplifier cores presented here improve the amplifier’s power supply noise insensitivity at high frequencies and increase bandwidth efficiency when compared to the commonly used two-stage Miller compensated amplifier, enabling the construction of better buffers and more power-efficient and reliable low voltage mixed signal chips.

Next generation mobile communication systems require the use of linear RF power amplifier for higher data transmission rates. However, linear RF power amplifiers are inherently inefficient and usually require additional circuits or further system adjustments for better efficiency. This dissertation focuses on the development of new efficiency enhancement schemes for linear RF power amplifiers. The multistage Doherty amplifier technique is proposed to improve the performance of linear RF power amplifiers operated in a low power level. This technique advances the original Doherty amplifier scheme by improving the efficiency at much lower power level. The proposed technique is supported by a new approach in device periphery calculation to reduce AM/AM distortion and a further improvement of linearity by the bias adaptation concept. The device periphery adjustment technique for efficiency enhancement of power amplifier integrated circuits is also proposed in this work. The concept is clearly explained together with its implementation on CMOS and SiGe RF power amplifier designs. Furthermore, linearity improvement technique using the cancellation of nonlinear terms is proposed for the CMOS power amplifier in combination with the efficiency enhancement technique. In addition to the efficiency enhancement of power amplifiers, a scalable large-signal MOSFET model using the modified BSIM3v3 approach is proposed. A new scalable substrate network model is developed to enhance the accuracy of the BSIM3v3 model in RF and microwave applications. The proposed model simplifies the modeling of substrate coupling effects in MOS transistor and provides great accuracy in both small-signal and large-signal performances.

Thesis (Ph.D.)--City University of Hong Kong, 2009.
"Submitted to Department of Electronic Engineering in partial fulfillment of the requirements for the degree of Doctor of Philosophy." Includes bibliographical references (leaves 129-134)

Orientadores: Jacobus Willibrordus Swart, Jader Alves de Lima Filho
Dissertação (mestrado) - Universidade Estadual de Campinas, Faculdade de Engenharia Eletrica e de Computação
Made available in DSpace on 2018-08-08T17:33:52Z (GMT). No. of bitstreams: 1 Agostinho_PetersonRibeiro_M.pdf: 4830694 bytes, checksum: d3db6a2118db3df2774037e49df52865 (MD5) Previous issue date: 2006
Resumo: Este trabalho descreve o procedimento de projeto de amplificadores operacionais rail-to-rail em tecnologia CMOS. Para isto, foram objetos desse processo quatro configurações distintas. As quatro topologias utilizam estágio de entrada rail-to-rail com controle de gm e estágio de saída classe-AB com controle de corrente quiescente. Como especificação para as três primeiras configurações estão tensão de alimentação de ± 0.9V, ganho de manha aberta em baixas freqüências de 60dB e freqüência de ganho unitário de 4MHz para uma carga externa de 10k? em paralelo com 10pF. A quarta configuração é uma nova topologia adaptada para que os transistores operem na região de inversão fraca, com o objetivo de reduzir o consumo de potência. Como especificação para esta configuração temos tensão de alimentação de ± 0.75V e minimização do consumo de potência. Os resultados obtidos a partir dos protótipos fabricados em tecnologia CMOS 0.35µm foram próximos às especificações. Uma placa de circuito impresso foi implementada para caracterização dos amplificadores e, além disso, foi utilizado nessa placa um amplificador comercial para realizar comparações
Abstract: This dissertation describes the process of designing rail-to-rail operational amplifiers in CMOS technology. To accomplish this, the author focused on four distinct structures. The four topologies have rail-to-rail input stage with gm-control circuit and Class-AB output stage with quiescent-current control. The specification of three configurations included the nominal power supply of ± 0.9V, minimum open-loop low-frequency gain of 60dB and unity-gain frequency of 4MHz driving an external load of 10k? in parallel with 10pF. The fourth one is a new topology adapted to operate with transistors in weak inversion, in order to decrease the power consumption. The specification included nominal power supply of ± 0.75V and minimization of power consumption. Prototypes of the amplifiers were fabricated in 0.35µm CMOS technology and the results were in good agreements with the specifications. A printed circuit board was implemented to test the amplifiers and, additionally, was inserted a commercial amplifier, to make comparisons
Mestrado
Eletrônica, Microeletrônica e Optoeletrônica
Mestre em Engenharia Elétrica

For many high-speed, high-performance circuits, purely differential inputs are needed. This project focuses on building high-speed voltage converters which can transfer a single-ended signal to a purely differential signal, or a differential input signal to a single-ended signal. Operational transconductance amplifier (OTAs) techniques are widely used in high-speed continuous-time integrated analog signal processing (ASP) circuits because resistors, inductors, integrators, buffers, multipliers and filters can be built by OT As and capacitors. Taking advantage of OT As, very-high-speed voltage converters are designed in CMOS technology. These converters can work in a frequency range from DC (OHz) up to lOOMHz and higher, and keep low distortion over a± 0.5V input range. They can replace transformers so that designing fully integrated differential circuits becomes possible. The designs are based on a MOSIS 2μm n-well process. SPICE simulations of these designs are given. The circuit was laid out with MAGIC layout tools and fabricated through MOSIS. The chip was measured at PSU and Intel circuit labs and the experimental results show the correctness of the designs.

The feasibility of developing test circuits to perform in-circuit testing of analog circuits is investigated in this thesis. A modular approach to analog testing has been adopted. Accordingly, the testing of an operational amplifier, which is a basic building block in analog circuits, is addressed. One convenient technique for measuring the frequency response of an op-amp requires a unity gain buffer to be inserted into its feedback loop. This buffer has to be simple in construction, small and accurate. Two buffer circuits that satisfy these requirements are described in this thesis. Enhanced slewing techniques are devised to achieve increased levels of performance. The buffers were integrated with an op-amp into a test chip. Digital logic is used to provide controllability and accessibility to each of the buffers and the op-amp so that they can characterized separately. The performance of the enhanced slewing buffers was verified with measurements performed on the test chip. The performance of the buffers conformed well with the simulated values. The buffers exhibited excellent settling times even while driving large capacitive loads. Their output swing and distortion performance were good for inputs as large as 2 V peak-to-peak values.
Graduation date: 1994

碩士
國立暨南國際大學
電機工程學系
97
This study investigated the performance of our newly-designed readout circuit on linear array pH sensor. From this research, I learned signal processing, circuit design, interface relationship between sensor and readout circuit, and noise analysis. The experimental procedures were that silver reference electrode, substituted the traditional glass reference electrode, was used together with a single pH sensor for pH measurements in order to prove the silver electrode could be used as a reference electrode. Then, the silver reference electrode was used together with the linear array pH sensor for pH measurements. The advantages of using linear array sensor were multi-sensing of analytes at the same time, still workable even several sensors of the linear array sensor were damaged, and higher signal to noise ratio. In this study, a readout circuit for the linear array pH sensor was designed and developed, using chopper stabilization technique. It consisted of analog multiplexer, chopper stabilized operational amplifier, level shift, filter and buffer stage. The operational amplifier used in this design was a folded cascade amplifier. It was found that the circuit could reduce input offset, drift voltage and noise and noise could be further reduced on a faster chopper frequency. This readout circuit could be used for measuring small signal of low frequency biosensor. The finalized readout circuit design was then implemented through the chip-implementation-center (CIC) using TSMC 0.35um 2P4M standard CMOS process. In conclusion, a readout circuit utilizing chopper stabilization technique was designed and developed in this study. The readout circuit used together with the linear array pH sensor were able to have a measurement range of pH2~pH12.

For the first method, a novel linearization scheme for CMOS double-balanced mixer based on the use of multi-bias dual-gate transistors is presented. In this technique, two intermodulation distortion components with proper phase relationship, generated by devices operating at different bias conditions, are added together to cancel each other for the improvement of mixer's linearity. The measured performance of a fabricated CMOS mixer operating at RF frequency of 2.45GHz and LO frequency of 2.35GHz is demonstrated. Over 35dB of IMD reduction is achieved by the proposed method under optimal biasing condition.
In the second design, a novel linearization scheme for cascode amplifier based upon capacitive feedback is presented. This method involves the optimal design of the feedback network for IMD reduction. By using Volterra series analysis, expression for IMD products is derived and the corresponding circuit parameters for optimized linearity are obtained. For experimental verification, CMOS cascode amplifiers are designed and fabricated to operate at 2.45GHz with supply voltage of 2V. By measurement, IIP3 is improved of almost 7dB by using the proposed feedback technique. The performance dependency of the fabricated amplifiers under different bias conditions is also examined. The results indicate that the proposed technique can offer low sensitivity to the variation of process parameters.
Linearity is one of the major requirements in modern communication systems due to the limited channel spacing. In the past years, various linearization schemes have been studied extensively for RF circuit design such as low-noise amplifiers and power amplifiers. These techniques offer IMD reduction at the expense of circuit complexity. In the last decade, much effort has been devoted to the development of single-chip RF transceiver using sub-micron CMOS technology. This thesis presents three simple and effective linearization techniques for CMOS mixer and amplifier design. They are experimentally verified by circuit fabrication based on 0.35mum CMOS process.
The last approach combines the advantages of source degeneration and the capacitive feedback for cascode amplifier linearization. Experiments are performed on CMOS amplifiers operating at 2.45GHz, and more than 11dB of IIP3 enhancement is observed.
Au Yeung, Chung Fai.
"August 2007."
Adviser: Chang Kwok Keung.
Source: Dissertation Abstracts International, Volume: 69-02, Section: B, page: 1189.
Thesis (Ph.D.)--Chinese University of Hong Kong, 2007.
Includes bibliographical references (p. 153-161).
Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web.
Electronic reproduction. [Ann Arbor, MI] : ProQuest Information and Learning, [200-] System requirements: Adobe Acrobat Reader. Available via World Wide Web.
Abstract in English and Chinese.
School code: 1307.

Existing linearisation methods were examined to establish the requirements for a wideband power amplifier model. A range of memoryless models were investigated, in particular polynomial models. No suitable memoryless models were found. The shortcomings of the models were analysed and directions for future investigations presented.
thesis (MEng(ElectronicsEngineering))--University of South Australia, 2003.

Chan Shek-Hang.
Thesis (M.Phil.)--Chinese University of Hong Kong, 2002.
Includes bibliographical references (leaves 94-97).
Abstracts in English and Chinese.
Abstract --- p.i
Acknowledgement --- p.iv
Table of Contents --- p.v
List of Figures --- p.ix
List of Tables --- p.xiii
Chapter Chapter 1 --- Introduction --- p.1
Chapter 1.1 --- Overview --- p.1
Chapter 1.2 --- Significance of the research --- p.2
Chapter 1.3 --- Objectives --- p.3
Chapter 1.4 --- Thesis outline --- p.4
Chapter Chapter 2 --- Background theory --- p.5
Chapter 2.1 --- Introduction --- p.5
Chapter 2.2 --- Electrical properties of MOS transistors --- p.5
Chapter 2.2.1 --- Strong inversion --- p.5
Chapter 2.2.2 --- Weak inversion --- p.6
Chapter 2.2.3 --- Moderate inversion --- p.8
Chapter 2.2.4 --- The transistors biased in this work --- p.8
Chapter 2.3 --- Rail-to-rail signals --- p.8
Chapter 2.4 --- Rail-to-rail operational amplifier --- p.10
Chapter 2.4.1 --- Rail-to-rail differential input pairs --- p.10
Chapter 2.4.1.1 --- Principle --- p.10
Chapter 2.4.1.2 --- Two stage operational amplifier --- p.13
Chapter 2.4.2 --- Folded-cascode gain stage --- p.14
Chapter 2.5 --- The nature of operational amplifier distortion --- p.16
Chapter 2.5.1 --- The total harmonic distortion --- p.17
Chapter Chapter 3 --- Constant transconductance rail-to-rail input stage --- p.20
Chapter 3.1 --- Introduction --- p.20
Chapter 3.2 --- Review of constant-gm input stage --- p.20
Chapter 3.2.1 --- Rail-to-rail input stages with current-based gm control --- p.20
Chapter 3.2.1.1 --- gm controlled by three-times current mirror --- p.21
Chapter 3.2.1.2 --- gm controlled by square root current control --- p.23
Chapter 3.2.1.3 --- gm controlled by using current switches only --- p.25
Chapter 3.2.2 --- Rail-to-rail input stages with voltage-based gm control --- p.28
Chapter 3.2.2.1 --- gm controlled by an ideal zener diode --- p.28
Chapter 3.2.2.2 --- gm controlled by two diodes --- p.30
Chapter 3.2.2.3 --- gm controlled by an electronic zener --- p.31
Chapter 3.3 --- Conclusion --- p.32
Chapter Chapter 4 --- Proposed constant transconductance rail-to-rail input stage --- p.34
Chapter 4.1 --- Introduction --- p.34
Chapter 4.2 --- Principle of the conventional input stage --- p.35
Chapter 4.2.1 --- Translinear circuit --- p.35
Chapter 4.3 --- Previous work --- p.36
Chapter 4.3.1 --- Input bias circuit --- p.36
Chapter 4.3.2 --- Weak inversion operation --- p.38
Chapter 4.3.3 --- Power up problem --- p.43
Chapter 4.4 --- Operational transconductance amplifier with proposed input biased stage --- p.47
Chapter 4.4.1 --- Proposed input biased stage architecture --- p.47
Chapter 4.4.2 --- Proposed input biased stage with 2 gm control circuits --- p.50
Chapter 4.4.3 --- OTA with proposed input biased stage --- p.51
Chapter Chapter 5 --- Simulation Results --- p.54
Chapter 5.1 --- Introduction --- p.54
Chapter 5.2 --- DC bias simulation --- p.54
Chapter 5.2.1 --- Total transconductance variation --- p.54
Chapter 5.2.2 --- Power consumption --- p.56
Chapter 5.3 --- AC simulation --- p.56
Chapter 5.3.1 --- Open-loop gain --- p.57
Chapter 5.3.2 --- Gain-bandwidth product --- p.59
Chapter 5.3.3 --- Phase margin --- p.59
Chapter 5.4 --- Transient simulation --- p.60
Chapter 5.4.1 --- Voltage follower --- p.60
Chapter 5.4.2 --- Total harmonic distortion --- p.62
Chapter 5.4.3 --- Step response --- p.65
Chapter 5.5 --- Conclusion --- p.67
Chapter Chapter 6 --- Layout Consideration --- p.68
Chapter 6.1 --- Introduction --- p.68
Chapter 6.2 --- Substrate tap --- p.68
Chapter 6.3 --- Input protection circuitry --- p.69
Chapter 6.4 --- Die micrographs of the OTA --- p.71
Chapter Chapter 7 --- Measurement Results --- p.74
Chapter 7.1 --- Introduction --- p.74
Chapter 7.2 --- DC bias measurement results --- p.74
Chapter 7.2.1 --- Total transconductance variation --- p.74
Chapter 7.2.2 --- Power consumption --- p.77
Chapter 7.3 --- AC measurement results --- p.78
Chapter 7.3.1 --- Open-loop gain --- p.78
Chapter 7.3.2 --- Gain-bandwidth product --- p.81
Chapter 7.3.3 --- Phase margin --- p.81
Chapter 7.4 --- Transient measurement result --- p.82
Chapter 7.4.1 --- Voltage follower --- p.82
Chapter 7.4.2 --- Total harmonic distortion --- p.85
Chapter 7.4.3 --- Step response --- p.87
Chapter 7.5 --- Conclusion --- p.88
Chapter Chapter 8 --- Conclusion --- p.90
Chapter 8.1 --- Contribution --- p.90
Chapter 8.2 --- Further development --- p.91
Chapter Chapter 9 --- Appendix --- p.92
Chapter Chapter 10 --- Bibliography --- p.94

Fan Chun Wah.
"March 2002."
Thesis (Ph.D.)--Chinese University of Hong Kong, 2002.
Includes bibliographical references (p. [140]-148).
Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web.
Mode of access: World Wide Web.
Abstracts in English and Chinese.

Leung Chi-Shuen.
Thesis (M.Phil.)--Chinese University of Hong Kong, 2002.
Includes bibliographical references (leaves 82-89).
Abstracts in English and Chinese.
Chapter Chapter 1 --- Introduction --- p.1
Chapter Chapter 2 --- Review of Linearization Techniques --- p.4
Chapter 2.1 --- Feedforward --- p.5
Chapter 2.2 --- Feedback --- p.7
Chapter 2.3 --- Predistortion --- p.10
Chapter Chapter 3 --- The Volterra Series Method for Nonlinear Analysis --- p.12
Chapter 3.1 --- Volterra Series Method --- p.13
Chapter 3.2 --- Nonlinear Transfer Function --- p.14
Chapter 3.3 --- Weakly Nonlinear Approximation --- p.18
Chapter 3.4 --- Nonlinear Modeling --- p.19
Chapter 3.5 --- Determination of Nonlinear Transfer Function --- p.22
Chapter Chapter 4 --- Manifestation of Nonlinear Behavior --- p.25
Chapter 4.1 --- Two-Tone Volterra Series Analysis --- p.25
Chapter 4.2 --- Harmonic Distortion --- p.28
Chapter 4.3 --- AM/AM and AM/PM --- p.29
Chapter 4.4 --- Intermodulation Distortion --- p.31
Chapter Chapter 5 --- The Generalized Baseband Signal Injection Method --- p.33
Chapter 5.1 --- Generalized Baseband Signal Injection Method (GM) --- p.34
Chapter 5.2 --- Application of GM to Predistorter-Amplifier Linearization --- p.38
Chapter 5.2.1 --- Case 1: Standalone Amplifier without Injection --- p.40
Chapter 5.2.2 --- Case 2: Injection to Amplifier Only --- p.41
Chapter 5.2.3 --- Case 3: Injection to Diode Predistorter Only --- p.41
Chapter 5.2.4 --- Case 4: Injection to Both Diode Predistorter and Amplifier --- p.42
Chapter 5.3 --- Application of GM to Multi-Stage Amplifier Linearization --- p.43
Chapter 5.3.1 --- Case 1: Amplifying System with No Signal Injection --- p.46
Chapter 5.3.2 --- Case 2: Amplifying System with Single Injection Point --- p.47
Chapter 5.3.3 --- Case 3: Amplifying System with Two Injection Points --- p.48
Chapter Chapter 6 --- Experimental Setup and Measurements --- p.50
Chapter 6.1 --- Experimental Setup --- p.51
Chapter 6.1.1 --- Diode Predistorter --- p.51
Chapter 6.1.2 --- Small Signal Amplifier --- p.54
Chapter 6.1.3 --- Medium Power Amplifier --- p.58
Chapter 6.1.4 --- Baseband Signal Generation Circuit --- p.61
Chapter 6.1.5 --- Baseband Amplifiers --- p.63
Chapter 6.2 --- Linearization of Amplifier with Predistortion Circuitry --- p.65
Chapter 6.2.1 --- Two-Tone Test --- p.65
Chapter 6.2.2 --- Vector Signal Test --- p.68
Chapter 6.2.3 --- Dynamic Range Evaluation --- p.70
Chapter 6.3 --- Linearization of Multi-Stage Amplifying System --- p.71
Chapter 6.3.1 --- Determination of Transfer and Gain Coefficients --- p.71
Chapter 6.3.2 --- Two-Tone Test --- p.74
Chapter 6.3.3 --- Vector Signal Test --- p.77
Chapter 6.3.4 --- Dynamic Range Evaluation --- p.79
Chapter Chapter 7 --- Conclusion and Future Work --- p.80
References --- p.82
Author's Publications --- p.90

The electronics industry has developed incredibly in last few years and the need for low voltage and low power consuming devices is reflected with its growth. A small extension in battery life can be reflected in an order of magnitude in terms of retail prices. From multimedia gadgets (like laptops, mobiles, notebook etc.) to the biomedical device, all applications have seen a rapid advancement. All these devices need a low voltage and low power transceiver to connect with the wireless networks. This PhD thesis is focused on the development of new designing techniques for low voltage, low power integrated circuits, having close attention on circuits suitable for analog devices. The vast majority of high performance analog circuit cells realized in metal–oxide–semiconductor field-effect transistor (MOSFET) technologies traditionally exploits transistors operating in saturation. Meanwhile there exists a region of weak inversion, which was left unexploited until recently, where the behavior of a MOS transistor is similar to a bipolar transistor in qualitative terms. This region could be exploited for the devices which require operating with low voltage supply. Instead of operating in saturation region, the MOS devices employed in this design, operate in weak inversion. The MOS devices in the proposed circuits are bulk-controlled. In the conventional mode of biasing the bulk terminal is left unused and is connected with lowest supply voltage or ground while the gate is usually chosen for the input signal introduction to bias the circuit. The bulk can be used as an input for signal, can lower the threshold of a transistor if biased properly, ultimately lowering the supply voltage requirement of the transistor. In this work a modified Nauta’s Transconductor, which operates on very low voltages and have a tunable transconductance is employed to design filters. The filter constructed can be tuned in the range of few MHz. The proposed filter is operated using a 0.5V supply and its cutoff frequency can be easily adjusted. All circuits are designed and analyzed using a triple well 0.13μm CMOS process. This OTA is further modified to achieve better performance, in order to implement it in a complex filter. In low IF devices the down-conversion of image signal along with the wanted signal at the same frequency is a major problem. Complex filter can easily remove this image signal by applying a frequency shifting operation. A sixth order complex filter by implementing Leapfrog technique is designed using the differential OTA. The filter is designed to meet the Bluetooth and Zigbee standard requirements. The filter operates on a 0.5V supply voltage, and has very good results for Image rejection, sensitivity, noise and the filter is orthogonally tunable. The performance of the filter has been evaluated through simulation results by employing a triple well 0.13μm CMOS process. This filter design can be implemented in the Bluetooth devices used for the biomedical applications.
Η βιομηχανία της ηλεκτρονικής έχει αναπτυχθεί απίστευτα τα τελευταία χρόνια και η ανάπτυξη αυτή συνδυάζεται με την ανάγκη για συσκευές που λειτουργούν σε χαμηλή τάση και με χαμηλή κατανάλωση ενέργειας. Σε ότι αφορά την εμπορική τιμή, μια μικρή αύξηση της διάρκειας ζωής της μπαταρίας μπορεί να αντανακλάται σε μια αύξηση κατά μία τάξη μεγέθους της τιμής. Όλες οι εφαρμογές, από τις συσκευές πολυμέσων (όπως κινητά τηλέφωνα, φορητούς υπολογιστές, notebook κ.λπ.) έως και τις βιοϊατρικές συσκευές έχουν δει μια ταχεία πρόοδο. Όλες αυτές οι συσκευές, για να συνδέονται με ασύρματα δίκτυα, χρειάζονται πομποδέκτη χαμηλής τάσης και χαμηλής κατανάλωσης ισχύος. Η παρούσα διδακτορική διατριβή επικεντρώνεται στην ανάπτυξη νέων τεχνικών σχεδιασμού για ολοκληρωμένα κυκλώματα με έμφαση στα αναλογικά κυκλώματα, χαμηλής τάσης και χαμηλής ισχύος. Η συντριπτική πλειοψηφία των δομικών βαθμίδων αναλογικών κυκλωμάτων υψηλών επιδόσεων πραγματοποιείται σε τεχνολογία μετάλλου οξειδίου ημιαγωγού τρανζίστορ φαινομένου πεδίου (MOSFET) και εκμεταλλεύεται τα τρανζίστορ που παραδοσιακά λειτουργούν σε κόρο. Ωστόσο, υπάρχει η περιοχή ασθενούς αναστροφής, η οποία αφέθηκε ανεκμετάλλευτη μέχρι πρόσφατα, όπου η συμπεριφορά των τρανζίστορ MOS είναι παρόμοια με αυτήν των διπολικών τρανζίστορ. Αυτή η περιοχή θα μπορούσε να αξιοποιηθεί για τις συσκευές που απαιτούν λειτουργία με χαμηλή τάση τροφοδοσίας. Αντί να λειτουργούν στην περιοχή κόρου, τα τρανζίστορ MOS που χρησιμοποιούνται σε αυτό το σχεδιασμό, λειτουργούν σε ασθενή αναστροφή. Τα τρανζίστορ MOS στα προτεινόμενα κυκλώματα είναι ελεγχόμενα από το υπόστρωμα (bulk-driven). Στο συμβατικό τρόπο οδήγησης το υπόστρωμα παραμένει αχρησιμοποίητο και συνδέεται με την χαμηλότερη τάση τροφοδοσίας ή τη γείωση, ενώ η πύλη συνήθως, επιλέγεται για την εισαγωγή σήματος εισόδου και οδηγεί το κύκλωμα. Το υπόστρωμα μπορεί να χρησιμοποιηθεί ως είσοδος για το σήμα, μπορεί να μειώσει την τάση κατωφλίου (threshold voltage) των τρανζίστορ, και τελικά, χαμηλώνει την τάση λειτουργίας του τρανζίστορ. Σε αυτήν την διδακτορική διατριβή χρησιμοποιείται ως διαγωγός (transconductor) ένα τροποποιημένο κύκλωμα Nauta, ο οποίος λειτουργεί σε πολύ χαμηλές τάσεις. Οι ελεγχόμενοι διαγωγοί χρησιμοποιούνται για το σχεδιασμό των προτεινόμενων συντονιζόμενων φίλτρων. Τα κατασκευασμένα φίλτρα μπορούν να συντονιστούν στην περιοχή των λίγων MHz. Τα προτεινόμενα φίλτρα λειτουργούν χρησιμοποιώντας τάση τροφοδοσίας 0.5V και η συχνότητα αποκοπής τους μπορεί εύκολα να προσαρμοστεί. Όλα τα κυκλώματα σχεδιάζονται και εξομοιώνονται χρησιμοποιώντας μία τεχνολογία CMOS triple well 0.13μm. Ο υπό μελέτη τελεστικός ενισχυτής διαγωγιμότητας (Operational Transconductor Amplifier - OTA) έχει τροποποιηθεί περαιτέρω, για να επιτευχθεί καλύτερη απόδοση και να εφαρμοστεί σε ένα μιγαδικό φίλτρο. Η μετατροπή σήματος από τις μεσαίες συχνότητες (IF) στις χαμηλές συχνότητες παρουσιάζεται ένα σημαντικό πρόβλημα όπου μαζί με το επιθυμητό σήμα εμφανίζεται και το σήμα εικόνας στην ίδια συχνότητα. Τα μιγαδικά (complex) φίλτρα μπορούν να αφαιρέσουν εύκολα το σήμα εικόνας, εφαρμόζοντας μια διαδικασία μετατόπισης συχνότητας. Ένα μιγαδικό Leapfrog φίλτρο έχει σχεδιαστεί χρησιμοποιώντας διαφορικούς ενισχυτές διαγωγιμότητας. Το τελικό μιγαδικό φίλτρο δωδέκατης τάξης έχει σχεδιαστεί για να καλύψει τις απαιτήσεις του προτύπου Bluetooth και Zigbee. Το φίλτρο λειτουργεί με τάση τροφοδοσίας 0.5V και έχει πολύ καλά αποτελέσματα στην απόρριψη εικόνας, την ευαισθησία και το θόρυβο. Επίσης, η κεντρική συχνότητα και το εύρος συχνοτήτων είναι ανεξάρτητα ρυθμιζόμενα. Η απόδοση του φίλτρου έχει επαληθευτεί μέσω προσομοίωσης χρησιμοποιώντας μοντέλα τρανζίστορ μιας τεχνολογίας CMOS triple well 0.13μm. Φίλτρα που σχεδιάζονται με την προτεινόμενη μέθοδο μπορούν να εφαρμοστούν σε συσκευές Bluetooth που χρησιμοποιούνται και σε βιοϊατρικές εφαρμογές.

Είναι γνωστό ότι τα κυκλώματα των τελεστικών ενισχυτών (Op-Amps) είναι από τις βασικότερες δομικές βαθμίδες στον χώρο της σχεδίασης αναλογικών ολοκληρωμένων κυκλωμάτων. Μια εναλλακτική δομή του τελεστικού ενισχυτή αποτελεί το κύκλωμα ενός Current Feedback Operational Amplifier (CFOA). Ένας CFOA είναι ουσιαστικά ένας μεταφορέας ρεύματος (Current Conveyor-CCII) σε σειρά με έναν ακολουθητή τάσης (Voltage Follower), και είναι ιδιαιτέρως χρήσιμος κατά την σχεδίαση κυκλωμάτων χαμηλής τάσης τροφοδοσίας. Στην εργασία αυτή μελετήθηκαν τέσσερις δομές CFOA, σχεδιασμένες για λειτουργία με χαμηλή τάση τροφοδοσίας, και χρησιμοποιήθηκαν για τον σχεδιασμό φίλτρων με τις μεθόδους Leapfrog, τοπολογικής εξομοίωσης και κυματική. Στο πρώτο κεφάλαιο αναφέρονται οι γενικές αρχές που ισχύουν στην σχεδίαση κυκλωμάτων για λειτουργία με χαμηλή τάση τροφοδοσίας καθώς και τις πιο συχνά χρησιμοποιούμενες τεχνικές σχεδίασης. Στο δεύτερο κεφάλαιο μελετώνται αναλυτικά οι τέσσερις δομές CFOA συγκρίνοντας τους βασικότερους παράγοντες απόδοσής τους. Τα κυκλώματα των CFOA που μελετώνται βασίζονται σε πρόσφατα δημοσιευμένες δομές Current Conveyor (CCII). Στο τρίτο κεφάλαιο αναλύεται η μέθοδος σχεδίασης φίλτρων Leapfrog, και χρησιμοποιείται για την σχεδίαση ενός Butterworth φίλτρου 3ης τάξης. Ως δομική βαθμίδα για την σχεδίαση αυτού του φίλτρου χρησιμοποείται ο CFOA [2]. Το τρίτο κεφάλαιο ολοκληρώνεται με την παρουσίαση των βασικότερων παραγώντων απόδοσης. Στο τέταρτο κεφάλαιο παρουσιάζεται η τοπολογική μέθοδος σχεδίασης φίλτρων, στην οποία γίνεται τοπολογική αντικατάσταση πηνίου, σε παθητικό φίλτρο, από ισοδύναμο κύκλωμα με ενεργά στοιχεία. Και στην περίπτωση αυτή η δομική μονάδα σχεδιασμού είναι ο CFOA [2]. Στο πέμπτο κεφάλαιο παρουσιάζεται η σχεδίαση ενός Butterworth φίλτρου 3ης τάξης με την κυματική μέθοδο. Η σχεδίαση πραγματοποιήθηκε χρησιμοποιώντας ως δομική βαθμίδα τον CFOA [1]. Στο έκτο κεφάλαιο παρουσιάζεται η φυσική σχεδίαση (layout) του Butterworth φίλτρου 3ης τάξης που σχεδιάστηκε με την leapfrog μέθοδο στο τρίτο κεφάλαιο. Η φυσική σχεδίαση πραγματοποιήθηκε με την χρήση του λογισμικού Cadence και του περιβάλλοντος Virtuoso που περιλαμβάνει για την φυσική σχεδίαση αναλογικών ηλεκτρονικών κυκλωμάτων . Τέλος στο έβδομο κεφάλαιο γίνεται σύγκριση των αποτελεσμάτων εξομοίωσης των δομών CFOA’s αλλά και των αποτελεσμάτων εξομοίωσης των φίλτρων που σχεδιάστηκαν στα παραπάνω κεφάλαια . Επίσης παρουσιάζονται κάποιες προτάσεις για μελλοντική και περαιτέρω έρευνα.
Operational amplifier is one of most important analog building block. An alternative structure for operational amplifier is a Current Feedback Operational Amplifier (CFOA). A CFOA is essentially consists of a current conveyor (CCII) connecting with a Voltage Follower (VF). The usage of CFOA for the low-voltage analog IC design is quite useful. In this work four different CFOA structures, designed for low-voltage operation, were considered. Also the aforementioned CFOAs were used to build a butterworth filter with Leapfrog method, topological simulation method and wave method. In first chapter the basic design rules and the most common design techniques for low-voltage IC design is presented. In chapter 2 the four structures of CFOAs circuits were considered, under the light of comparison of most critical factors of operation. The CFOAs circuits were based in most resent published topologies of Current Conveyor (CCII). In chapter 3 the Leapfrog method for filters design was discussed. Also a 3rd order butterworth filter is designed based on this method. The CFOA of ref [2] is the main building lock to construct this filter. In chapter 4 another method for filter design is presented named topological simulation method. According to this method passive elements such as inductors and capacitors are replaced by active elements. The main building block is also CFOA of ref [2]. In Chapter 5 a 3rd order butterworth filter based on wave method is designed. In this case the main building block was the CFOA circuit of ref [1]. Chapter 6 presents the layout of the 3rd order butterworth filter which designed at chapter 3 with leapfrog method. The layout design was implemented using Virtuoso environment of Cadence design framework II platform. Chapter 7 conclude this work presenting the simulated comparison results for all four CFOAs circuits and the 3rd order butterworth filters that were designed with the three different methods. Some thoughts for further research in the this subject are also presented.