Literatura académica sobre el tema "Memory Affinity"
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Artículos de revistas sobre el tema "Memory Affinity"
Fishman, Michael A. y Alan S. Perelson. "Lymphocyte memory and affinity selection". Journal of Theoretical Biology 173, n.º 3 (abril de 1995): 241–62. http://dx.doi.org/10.1016/s0022-5193(95)80003-4.
Texto completoNikolopoulos, D. S., E. Artiaga, E. Ayguadé y J. Labarta. "Exploiting memory affinity in OpenMP through schedule reuse". ACM SIGARCH Computer Architecture News 29, n.º 5 (diciembre de 2001): 49–55. http://dx.doi.org/10.1145/563647.563657.
Texto completoJi, Minwen. "Affinity-based management of main memory database clusters". ACM Transactions on Internet Technology 2, n.º 4 (noviembre de 2002): 307–39. http://dx.doi.org/10.1145/604596.604599.
Texto completoShimoda, Michiko, Toru Nakamura, Yoshimasa Takahashi, Hideki Asanuma, Shin-ichi Tamura, Takeshi Kurata, Tsuguo Mizuochi, Norihiro Azuma, Choemon Kanno y Toshitada Takemori. "Isotype-specific Selection of High Affinity Memory B Cells in Nasal-associated Lymphoid Tissue". Journal of Experimental Medicine 194, n.º 11 (3 de diciembre de 2001): 1597–608. http://dx.doi.org/10.1084/jem.194.11.1597.
Texto completoKoni, Pandelakis A. y Richard A. Flavell. "Lymph Node Germinal Centers Form in the Absence of Follicular Dendritic Cell Networks". Journal of Experimental Medicine 189, n.º 5 (1 de marzo de 1999): 855–64. http://dx.doi.org/10.1084/jem.189.5.855.
Texto completoTorrellas, Josep, Andrew Tucker y Anoop Gupta. "Benefits of cache-affinity scheduling in shared-memory multiprocessors". ACM SIGMETRICS Performance Evaluation Review 21, n.º 1 (junio de 1993): 272–74. http://dx.doi.org/10.1145/166962.167038.
Texto completoNeuberger, Michael S., Michael R. Ehrenstein, Cristina Rada, Julian Sale, Facundo D. Batista, Gareth Williams y Cesar Milstein. "Memory in the B–cell compartment: antibody affinity maturation". Philosophical Transactions of the Royal Society of London. Series B: Biological Sciences 355, n.º 1395 (29 de marzo de 2000): 357–60. http://dx.doi.org/10.1098/rstb.2000.0573.
Texto completoGóes, Luís Fabrício Wanderley, Christiane Pousa Ribeiro, Márcio Castro, Jean-François Méhaut, Murray Cole y Marcelo Cintra. "Automatic Skeleton-Driven Memory Affinity for Transactional Worklist Applications". International Journal of Parallel Programming 42, n.º 2 (31 de mayo de 2013): 365–82. http://dx.doi.org/10.1007/s10766-013-0253-x.
Texto completoKaji, Tomohiro, Akiko Ishige, Masaki Hikida, Junko Taka, Atsushi Hijikata, Masato Kubo, Takeshi Nagashima et al. "Distinct cellular pathways select germline-encoded and somatically mutated antibodies into immunological memory". Journal of Experimental Medicine 209, n.º 11 (1 de octubre de 2012): 2079–97. http://dx.doi.org/10.1084/jem.20120127.
Texto completoSmith, Kenneth G. C., Amanda Light, Lorraine A. O'Reilly, Soon-Meng Ang, Andreas Strasser y David Tarlinton. "bcl-2 Transgene Expression Inhibits Apoptosis in the Germinal Center and Reveals Differences in the Selection of Memory B Cells and Bone Marrow Antibody-Forming Cells". Journal of Experimental Medicine 191, n.º 3 (7 de febrero de 2000): 475–84. http://dx.doi.org/10.1084/jem.191.3.475.
Texto completoTesis sobre el tema "Memory Affinity"
Pousa, Ribeiro Christiane. "Contributions au contrôle de l'affinité mémoire sur architectures multicoeurs et hiérarchiques". Thesis, Grenoble, 2011. http://www.theses.fr/2011GRENM030/document.
Texto completoMulti-core platforms with non-uniform memory access (NUMA) design are now a common resource in High Performance Computing. In such platforms, the shared memory is organized in an hierarchical memory subsystem in which the main memory is physically distributed into several memory banks. Additionally, the hierarchical memory subsystem of these platforms feature several levels of cache memories. Because of such hierarchy, memory access costs may vary depending on the distance between tasks and data. Furthermore, since the number of cores is considerably high in such machines, concurrent accesses to the same distributed shared memory are performed. These accesses produce more stress on the memory banks, generating load-balancing issues, memory contention and remote accesses. Therefore, the main challenge on a NUMA platform is to reduce memory access latency and memory contention. In this context, the main objective of this thesis is to attain scalable performances on multi-core NUMA machines by controlling memory affinity. The first goal of this thesis is to investigate which characteristics of the NUMA platform and the application have an important impact on the memory affinity control and propose mechanisms to deal with them on multi-core machines with NUMA design. We focus on High Performance Scientific Numerical workloads with regular and irregular memory access characteristics. The study of memory affinity aims at the proposal of an environment to manage memory affinity on Multi-core Platforms with NUMA design. This environment provides fine grained mechanisms to manage data placement for an application by using compilation time and architecture information. The second goal is to provide solutions that show performance portability. By performance portability, we mean solutions that are capable of providing similar performances improvements on different NUMA platforms. In order to do so, we propose mechanisms that are independent of machine architecture and compiler. The portability of the proposed environment is evaluated through the performance analysis of several benchmarks and applications over different platforms. Last, the third goal of this thesis is to design memory affinity mechanisms that can be easily adapted and used in different parallel systems. Our approach takes into account the different data structures used in High Performance Scientific Numerical workloads, in order to propose solutions that can be used in different contexts. We evaluate the adaptability of such mechanisms in two parallel programming systems. All the ideas developed in this research work are implemented in a Framework named Minas (Memory affInity maNAgement Software). Several OpenMP benchmarks and two real world applications from geophysics are used to evaluate its performance. Additionally, Minas integration on Charm++ (Parallel Programming System) and OpenSkel (Skeleton Pattern System for Software Transactional Memory) is also evaluated
Zhou, Naweiluo. "Autonomic Thread Parallelism and Mapping Control for Software Transactional Memory". Thesis, Université Grenoble Alpes (ComUE), 2016. http://www.theses.fr/2016GREAM045/document.
Texto completoParallel programs need to manage the trade-off between the time spent in synchronisation and computation. The trade-off is significantly affected by the number of active threads. High parallelism may decrease computing time while increase synchronisation cost. Furthermore, thread placement on different cores may impact on program performance, as the data access time can vary from one core to another due to intricacies of its underlying memory architecture. Therefore, the performance of a program can be improved by adjusting its parallelism degree and the mapping of its threads to physical cores. Alas, there is no universal rule to decide them for a program from an offline view, especially for a program with online behaviour variation. Moreover, offline tuning is less precise. This thesis presents work on dynamical management of parallelism and thread placement. It addresses multithread issues via Software Transactional Memory (STM). STM has emerged as a promising technique, which bypasses locks, to tackle synchronisation through transactions. Autonomic computing offers designers a framework of methods and techniques to build autonomic systems with well-mastered behaviours. Its key idea is to implement feedback control loops to design safe, efficient and predictable controllers, which enable monitoring and adjusting controlled systems dynamically while keeping overhead low. This dissertation proposes feedback control loops to automate management of threads at runtime and diminish program execution time
Nordén, Markus. "Multithreaded PDE Solvers on Non-Uniform Memory Architectures". Doctoral thesis, Uppsala universitet, Avdelningen för teknisk databehandling, 2006. http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-7149.
Texto completoRadovic, Zoran. "Software Techniques for Distributed Shared Memory". Doctoral thesis, Uppsala University, Department of Information Technology, 2005. http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-6058.
Texto completoIn large multiprocessors, the access to shared memory is often nonuniform, and may vary as much as ten times for some distributed shared-memory architectures (DSMs). This dissertation identifies another important nonuniform property of DSM systems: nonuniform communication architecture, NUCA. High-end hardware-coherent machines built from large nodes, or from chip multiprocessors, are typical NUCA systems, since they have a lower penalty for reading recently written data from a neighbor's cache than from a remote cache. This dissertation identifies node affinity as an important property for scalable general-purpose locks. Several software-based hierarchical lock implementations exploiting NUCAs are presented and evaluated. NUCA-aware locks are shown to be almost twice as efficient for contended critical sections compared to traditional lock implementations.
The shared-memory “illusion”' provided by some large DSM systems may be implemented using either hardware, software or a combination thereof. A software-based implementation can enable cheap cluster hardware to be used, but typically suffers from poor and unpredictable performance characteristics.
This dissertation advocates a new software-hardware trade-off design point based on a new combination of techniques. The two low-level techniques, fine-grain deterministic coherence and synchronous protocol execution, as well as profile-guided protocol flexibility, are evaluated in isolation as well as in a combined setting using all-software implementations. Finally, a minimum of hardware trap support is suggested to further improve the performance of coherence protocols across cluster nodes. It is shown that all these techniques combined could result in a fairly stable performance on par with hardware-based coherence.
Centuori, Sara M., Cecil J. Gomes, Samuel S. Kim, Charles W. Putnam, Brandon T. Larsen, Linda L. Garland, David W. Mount y Jesse D. Martinez. "Double-negative (CD27−IgD−) B cells are expanded in NSCLC and inversely correlate with affinity-matured B cell populations". BIOMED CENTRAL LTD, 2018. http://hdl.handle.net/10150/627195.
Texto completoLöf, Henrik. "Iterative and Adaptive PDE Solvers for Shared Memory Architectures". Doctoral thesis, Uppsala universitet, Avdelningen för teknisk databehandling, 2006. http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-7136.
Texto completoMoreaud, Stéphanie. "Mouvement de données et placement des tâches pour les communications haute performance sur machines hiérarchiques". Phd thesis, Université Sciences et Technologies - Bordeaux I, 2011. http://tel.archives-ouvertes.fr/tel-00635651.
Texto completoWirzberger, Maria, René Schmidt, Maria Georgi, Wolfram Hardt, Guido Brunnett y Günter Daniel Rey. "Effects of system response delays on elderly humans’ cognitive performance in a virtual training scenario". Springer Nature, 2019. https://monarch.qucosa.de/id/qucosa%3A34294.
Texto completoGrund, Lidiane Zito. "Papel das citocinas IL-5 e IL-17A na diferenciação de células produtoras de anticorpos de vida longa (ASC) induzida pelo veneno do peixe Thalassophryne nattereri". Universidade de São Paulo, 2009. http://www.teses.usp.br/teses/disponiveis/42/42133/tde-09022010-114250/.
Texto completoT. nattereri fish venom induces a memory immune response with the differentiation of B cells B220neg, an indicative of long-lived antibody-secreting cells - ASC. To assess the effect of the venom on differentiation of ASCs, BALB/c mice were immunized with venom and sacrificed at days 21, 28, 48, 74 and 120 to evaluate plasmatic antibodies and B cell subtypes in peritoneum, spleen and bone marrow. The venom promoted splenomegaly, germinal centers formation and persistent levels of specific antibodies IgG1, IgG2a and anaphylactic IgE. B1a cells and ASC emerged rapidly and CD138pos ASCs can be divided into three subsets (B220high CD43high, B220low CD43low, and B220neg CD43high) that persist at different levels in all compartments. Finally, by neutralization methods we suggested an important role for IL-5 and IL-17A on development of B220neg ASCs and B1a population and moreover the production of TNF-a, IL-1b, IL-6, KC as well as the venom retained in follicular dendritic cells seem to provide mechanisms to explain the maintenance of ASCs.
HUANG, CHUN-CHIH y 黃俊智. "Improvement of Memory Bandwidth Utilization using OpenMP Task with Processor Affinity". Thesis, 2013. http://ndltd.ncl.edu.tw/handle/38777552387604890104.
Texto completo輔仁大學
資訊工程學系碩士班
102
The CPU design has been evolving for more than 30 years since the first x86-microprocessor. The processor frequency has increased according to Moore's Law and continued upward until encountering bottlenecks caused by power consumption problems and heat dissipation. As a result, CPU performance improvement has slowed recently. The current solution is to increase the number of cores, but not increase the operating frequency. Even though the computing performance of processors has increased, memory speed and bandwidth have not caught up with processor speed in terms of shared memory architectures. Multi-core processor technology is rapidly evolving, but the memory interface is a limiting factor in fulfilling the needs of multi-core and multi-threaded processors. This is a big challenge for software developers. This thesis mainly focuses on research regarding applications that consume a large amount of memory resources, and measuring the memory bandwidth usage in parallel programming applications in shared memory multi-core computing environments. The run time thread is dynamically allocated to each processor core by the scheduler of operating system. Current parallel programming researches only aim to load balance and keep the multi-core running efficiently. As a result, applications may have poor spatial data locality. This will also cause uneven memory bandwidth usage due to differences in memory access paths. The question of obtaining maximum memory bandwidth utilization by controlling the thread of processor affinity is the main scope of this particular research. According to the test results, the OpenMP task level parallelism achieved a 7% (8776.87 MB/s to 9376.27 MB/s) improvement compared to OpenMP parallel level parallelism. Memory bandwidth utilization of 62% (8786.87 MB/s to 14201.88 MB/s) was achieved if appropriate processor affinity was set for thread placement. OpenMP task level parallelism in addition to processor affinity resulted in 69% (8786.87 MB/s to 14802.69 MB/s) of improvement using 2 threads. Similarly, using 4 threads with 33% (11801.28 to 15704.62 MB/s) of improvement, 6 threads with 20% (13098.61 to 15840.78 MB/s) of improvement, 12 and 24 threads with 15% (13753.40 to 15825.86 MB/s) of improvement had been observed. Thus, task level parallelism combined with processor affinity greatly increases the level of parallelism in an OpenMP parallel programming environment. As a result, it can improve the overall performance of parallel applications.
Libros sobre el tema "Memory Affinity"
Torrellas, Josep. Evaluating the benefits of cache-affinity scheduling in shared-memory multiprocessors. Stanford, Calif: Computer Systems Laboratory, Stanford University, 1992.
Buscar texto completoKämpchen, Martin. Indo-German Exchanges in Education. Oxford University Press, 2020. http://dx.doi.org/10.1093/oso/9780190126278.001.0001.
Texto completoCapítulos de libros sobre el tema "Memory Affinity"
Terboven, Christian, Jonas Hahnfeld, Xavier Teruel, Sergi Mateo, Alejandro Duran, Michael Klemm, Stephen L. Olivier y Bronis R. de Supinski. "Approaches for Task Affinity in OpenMP". En OpenMP: Memory, Devices, and Tasks, 102–15. Cham: Springer International Publishing, 2016. http://dx.doi.org/10.1007/978-3-319-45550-1_8.
Texto completoPophale, Swaroop y Oscar Hernandez. "Evaluating OpenMP Affinity on the POWER8 Architecture". En OpenMP: Memory, Devices, and Tasks, 35–46. Cham: Springer International Publishing, 2016. http://dx.doi.org/10.1007/978-3-319-45550-1_3.
Texto completoSchmidl, Dirk, Tim Cramer, Christian Terboven, Dieter an Mey y Matthias S. Müller. "An OpenMP Extension Library for Memory Affinity". En Using and Improving OpenMP for Devices, Tasks, and More, 103–14. Cham: Springer International Publishing, 2014. http://dx.doi.org/10.1007/978-3-319-11454-5_8.
Texto completoVirouleau, Philippe, Adrien Roussel, François Broquedis, Thierry Gautier, Fabrice Rastello y Jean-Marc Gratien. "Description, Implementation and Evaluation of an Affinity Clause for Task Directives". En OpenMP: Memory, Devices, and Tasks, 61–73. Cham: Springer International Publishing, 2016. http://dx.doi.org/10.1007/978-3-319-45550-1_5.
Texto completoShi, Weisong y Zhimin Tang. "Affinity-Based Self Scheduling for Software Shared Memory Systems". En Lecture Notes in Computer Science, 163–68. Berlin, Heidelberg: Springer Berlin Heidelberg, 1999. http://dx.doi.org/10.1007/978-3-540-46642-0_23.
Texto completoPousa Ribeiro, Christiane, Márcio Castro, Jean-François Méhaut y Alexandre Carissimi. "Improving Memory Affinity of Geophysics Applications on NUMA Platforms Using Minas". En Lecture Notes in Computer Science, 279–92. Berlin, Heidelberg: Springer Berlin Heidelberg, 2011. http://dx.doi.org/10.1007/978-3-642-19328-6_27.
Texto completoMitchell, Kate. "‘Making it seem like it’s authentic’: the Faux-Victorian Novel as Cultural Memory in Affinity and Fingersmith". En History and Cultural Memory in Neo-Victorian Fiction, 117–42. London: Palgrave Macmillan UK, 2010. http://dx.doi.org/10.1057/9780230283121_6.
Texto completoKim, Dongwook, Eunjin Kim y Joonwon Lee. "A Virtual Cache Scheme for Improving Cache-Affinity on Multiprogrammed Shared Memory Multiprocessors". En High Performance Computing Systems and Applications, 249. Boston, MA: Springer US, 1998. http://dx.doi.org/10.1007/978-1-4615-5611-4_25.
Texto completoVeugelers, John W. P. "Discourse and Politics". En Empire's Legacy, 133–52. Oxford University Press, 2019. http://dx.doi.org/10.1093/oso/9780190875664.003.0010.
Texto completoAhmad, Waseem. "Artificial Immune Optimization Algorithm". En Improving Knowledge Discovery through the Integration of Data Mining Techniques, 104–23. IGI Global, 2015. http://dx.doi.org/10.4018/978-1-4666-8513-0.ch006.
Texto completoActas de conferencias sobre el tema "Memory Affinity"
Ribeiro, Christiane Pousa, Jean-Francois Mehaut, Alexandre Carissimi, Marcio Castro y Luiz Gustavo Fernandes. "Memory Affinity for Hierarchical Shared Memory Multiprocessors". En 2009 21st International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD). IEEE, 2009. http://dx.doi.org/10.1109/sbac-pad.2009.16.
Texto completoPasqualin, Douglas Pereira, Matthias Diener, Andre Rauber Du Bois y Mauricio Lima Pilla. "Thread Affinity in Software Transactional Memory". En 2020 19th International Symposium on Parallel and Distributed Computing (ISPDC). IEEE, 2020. http://dx.doi.org/10.1109/ispdc51135.2020.00033.
Texto completoTorrellas, Josep, Andrew Tucker y Anoop Gupta. "Benefits of cache-affinity scheduling in shared-memory multiprocessors". En the 1993 ACM SIGMETRICS conference. New York, New York, USA: ACM Press, 1993. http://dx.doi.org/10.1145/166955.167038.
Texto completoDiener, Matthias, Eduardo H. M. Cruz, Marco A. Z. Alves, Edson Borin y Philippe O. A. Navaux. "Optimizing memory affinity with a hybrid compiler/OS approach". En CF '17: Computing Frontiers Conference. New York, NY, USA: ACM, 2017. http://dx.doi.org/10.1145/3075564.3075566.
Texto completoRibeiro, Christiane Pousa, Jean-Francois Mehaut y Alexandre Carissimi. "Memory affinity management for numerical scientific applications over Multi-core Multiprocessors with Hierarchical Memory". En 2010 IEEE International Symposium on Parallel & Distributed Processing, Workshops and Phd Forum (IPDPSW 2010). IEEE, 2010. http://dx.doi.org/10.1109/ipdpsw.2010.5470796.
Texto completoZhong, Qi, Xuetao Guan, Tao Huang, Xu Cheng y Keyi Wang. "Affinity-aware DMA buffer management for reducing off-chip memory access". En the 27th Annual ACM Symposium. New York, New York, USA: ACM Press, 2012. http://dx.doi.org/10.1145/2245276.2232031.
Texto completoArul, Joseph M. y Chun-Chih Huang. "Improvement of memory bandwidth utilization using OpenMP task with processor affinity". En 2015 International Symposium on Next-Generation Electronics (ISNE). IEEE, 2015. http://dx.doi.org/10.1109/isne.2015.7131947.
Texto completoMisale, Claudia. "Accelerating Bowtie2 with a lock-less concurrency approach and memory affinity". En 2014 22nd Euromicro International Conference on Parallel, Distributed and Network-Based Processing (PDP). IEEE, 2014. http://dx.doi.org/10.1109/pdp.2014.50.
Texto completoJia, Gangyong, Xi Li, Chao Wang, Xuehai Zhou y Zongwei Zhu. "Memory Affinity: Balancing Performance, Power, Thermal and Fairness for Multi-core Systems". En 2012 IEEE International Conference on Cluster Computing (CLUSTER). IEEE, 2012. http://dx.doi.org/10.1109/cluster.2012.33.
Texto completoVaswani, Raj y John Zahorjan. "The implications of cache affinity on processor scheduling for multiprogrammed, shared memory multiprocessors". En the thirteenth ACM symposium. New York, New York, USA: ACM Press, 1991. http://dx.doi.org/10.1145/121132.121140.
Texto completoInformes sobre el tema "Memory Affinity"
Cox, Jeremy. The unheard voice and the unseen shadow. Norges Musikkhøgskole, agosto de 2018. http://dx.doi.org/10.22501/nmh-ar.621671.
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