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Artículos de revistas sobre el tema "Pipeline datapath"

Autor: Grafiati

Publicado: 25 de mayo de 2024

Última modificación: 19 de julio de 2025

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1

D.PREETHI, G.KEERTHANA K.RESHMA Mr.A.RAJA. "ENGINEERING DESIGN OF RECONFIGURABLE PIPELINED DATAPATH." Journal For Innovative Development in Pharmaceutical and Technical Science 2, no. 12 (2019): 26–29. https://doi.org/10.5281/zenodo.3600025.

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Configurable processing has caught the creative mind of numerous draftsmen who need the exhibition of use explicit equipment joined with the re programmability of universally useful PCs. Sadly, Configurable processing has had rather constrained achievement generally on the grounds that the FPGAs on which they are constructed are more fit to executing arbitrary rationale than registering assignments. This paper presents RaPiD, another coarse-grained FPGA engineering that is enhanced for exceptionally monotonous, calculation escalated errands. Extremely profound application-explicit calculation

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2

Ravikumar, C. P., and V. Saxena. "TOGAPS: A Testability Oriented Genetic Algorithm For Pipeline Synthesis." VLSI Design 5, no. 1 (1996): 77–87. http://dx.doi.org/10.1155/1996/65320.

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In this paper, we describe TOGAPS, a Testability-Oriented Genetic Algorithm for Pipeline Synthesis. The input to TOGAPS is an unscheduled data flow graph along with a specification of the desired pipeline latency. TOGAPS generates a register-level description of a datapath which is near-optimal in terms of area, meets the latency requirement, and is highly testable. Genetic search is employed to explore a 3-D search space, the three dimensions being the chip area, average latency, and the testability of the datapath. Testability of a design is evaluated by counting the number of self-loops in

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3

Kirat, Pal Singh, and Dod Shiwani. "Performance Improvement in MIPS Pipeline Processor based on FPGA." International Journal of Engineering Technology, Management and Applied Sciences 4, no. 1 (2016): 57–64. https://doi.org/10.5281/zenodo.48482.

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The paper describes the design and synthesis of a basic 5 stage pipelined MIPS-32 processor for finding the longer path delay using different process technologies. The large propagation delay or critical path within the circuit and improving the hardware which causes delay is a standard method for increasing the performance. The organization of pipeline stages in such a way that pipeline can be clocked at a high frequency. The design has been synthesized at different process technologies targeting using Spartan3, Spartan6, Virtex4, Virtex5 and Virtex6 devices. The synthesis report indicates th

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4

Kirat, Pal Singh, and Kumar Dilip. "Performance Evaluation of Low Power MIPS Crypto Processor based on Cryptography Algorithms." International Journal of Engineering Research and Applications 2, no. 3 (2012): 1625–34. https://doi.org/10.5281/zenodo.33251.

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This paper presents the design and implementation of low power 32-bit encrypted and decrypted MIPS processor for Data Encryption Standard (DES), Triple DES, Advanced Encryption Standard (AES) based on MIPS pipeline architecture. The organization of pipeline stages has been done in such a way that pipeline can be clocked at high frequency. Encryption and Decryption blocks of three standard cryptography algorithms on MIPS processor and dependency among themselves are explained in detail with the help of a block diagram. Clock gating technique is used to reduce the power consumption in MIPS crypt

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5

Kingyens, Jeffrey, and J. Gregory Steffan. "The Potential for a GPU-Like Overlay Architecture for FPGAs." International Journal of Reconfigurable Computing 2011 (2011): 1–15. http://dx.doi.org/10.1155/2011/514581.

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We propose a soft processor programming model and architecture inspired by graphics processing units (GPUs) that are well-matched to the strengths of FPGAs, namely, highly parallel and pipelinable computation. In particular, our soft processor architecture exploits multithreading, vector operations, and predication to supply a floating-point pipeline of 64 stages via hardware support for up to 256 concurrent thread contexts. The key new contributions of our architecture are mechanisms for managing threads and register files that maximize data-level and instruction-level parallelism while overc

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6

Kirat, Pal Singh, and Parmar Shivani. "Vhdl Implementation of A Mips-32 Pipeline Processor." International Journal of Applied Engineering Research 7, no. 11 (2012): 1952–56. https://doi.org/10.5281/zenodo.33247.

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This paper presents the design and implement a basic five stage pipelined MIPS-32 CPU. Particular attention will be paid to the reduction of clock cycles for lower instruction latency as well as taking advantage of high-speed components in an attempt to reach a clock speed of at least 100 MHz. The final results allowed the CPU to be run at over 200 MHz with a very reasonable chip area of around 900,000nm2.

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7

Gaurav Yadav. "Efficient SIMD computations on FPGA: Architectures, design techniques, and applications." World Journal of Advanced Research and Reviews 26, no. 1 (2025): 197–209. https://doi.org/10.30574/wjarr.2025.26.1.1056.

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Field-Programmable Gate Arrays (FPGAs) provide a flexible and efficient platform for implementing Single Instruction, Multiple Data (SIMD) computations, offering advantages over traditional CPUs and GPUs through customizable architectures. This article explores the design considerations, optimization techniques, and practical applications of SIMD operations on FPGAs. We examine how vector processing units, specialized memory organizations, and interconnect architectures can be tailored to application requirements, while investigating methods for datapath optimization, memory access enhancement

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8

Lee, Y. H., M. Khalil-Hani, and M. N. Marsono. "An FPGA-Based Quantum Computing Emulation Framework Based on Serial-Parallel Architecture." International Journal of Reconfigurable Computing 2016 (2016): 1–18. http://dx.doi.org/10.1155/2016/5718124.

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Hardware emulation of quantum systems can mimic more efficiently the parallel behaviour of quantum computations, thus allowing higher processing speed-up than software simulations. In this paper, an efficient hardware emulation method that employs a serial-parallel hardware architecture targeted for field programmable gate array (FPGA) is proposed. Quantum Fourier transform and Grover’s search are chosen as case studies in this work since they are the core of many useful quantum algorithms. Experimental work shows that, with the proposed emulation architecture, a linear reduction in resource u

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9

Kashima, Ryota, Ikki Nagaoka, Masamitsu Tanaka, Taro Yamashita, and Akira Fujimaki. "64-GHz Datapath Demonstration for Bit-Parallel SFQ Microprocessors Based on a Gate-Level-Pipeline Structure." IEEE Transactions on Applied Superconductivity 31, no. 5 (2021): 1–6. http://dx.doi.org/10.1109/tasc.2021.3061353.

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10

Sergiyenko, Anatoliy, and Ivan Mozghovyi. "Method for Mapping Cyclo-Dynamic Dataflow Into Pipelined Datapath." Information, Computing and Intelligent systems, no. 4 (October 2, 2024): 4–15. http://dx.doi.org/10.20535/2786-8729.4.2024.304965.

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An overview of high-level synthesis (HLS) systems for designing pipelined datapaths is presented in the paper. The goal is to explore methods of mapping algorithms to the pipelined datapaths implementing the cyclic data flow graphs with dynamic schedules. The cyclo-dynamic dataflow (CDDF) is selected as the very expressive model for describing a wide domain of the dataflow algorithms. CDDF is distinguished in that, the algorithm period depends on the calculated data and has a dynamic schedule. A set of mapping conditions is formulated that provide the deadlock-free schedule of CDDF when it is

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11

Alachiotis, Nikolaos, and Alexandros Stamatakis. "A Vector-Like Reconfigurable Floating-Point Unit for the Logarithm." International Journal of Reconfigurable Computing 2011 (2011): 1–12. http://dx.doi.org/10.1155/2011/341510.

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The use of reconfigurable computing for accelerating floating-point intensive codes is becoming common due to the availability of DSPs in new-generation FPGAs. We present the design of an efficient, pipelined floating-point datapath for calculating the logarithm function on reconfigurable devices. We integrate the datapath into a stand-alone LUT-based (Lookup Table) component, the LAU (Logarithm Approximation Unit). We extended the LAU, by integrating two architecturally independent, LAU-based datapaths into a larger component, the VLAU (vector-like LAU). The VLAU produces 2 results/cycle, whi

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12

Putra, Agfianto Eko, Oskar Natan, and Jazi Eko Istiyanto. "Optimizing FPGA Resource Allocation for SHA-3 Using DSP48 and Pipelining Techniques." IIUM Engineering Journal 26, no. 1 (2025): 240–53. https://doi.org/10.31436/iiumej.v26i1.3328.

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Deploying SHA-3 on FPGA devices requires significant resource allocation; however, the resulting throughput still needs improvement. This study employs the DSP48 module on the Xilinx FPGA to address this issue and implements an eight-stage pipeline methodology to minimize latency. The implementation design comprises a datapath and controller module, utilizing a Xilinx Artix-7-100T series FPGA as the hardware. This method makes use of FPGA resources like Look-Up Tables (LUT), Look-Up Table Random Access Memory (LUTRAM), Flip-Flops (FF), Block RAM (BRAM), Digital Signal Processing (DSP), Input/O

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13

Titus, Dr Anita. "Datapath Optimization in AES using Pipelined Architecture." International Journal for Research in Applied Science and Engineering Technology 8, no. 8 (2020): 940–44. http://dx.doi.org/10.22214/ijraset.2020.31056.

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14

Cekli, Serap, and Ali Akman. "Enhanced SPIHT Algorithm with Pipelined Datapath Architecture Design." Electrica 19, no. 1 (2019): 29–36. http://dx.doi.org/10.26650/electrica.2018.15101.

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15

Cappuccino, G., G. Cocorullo, P. Corsonello, and S. Perri. "High speed self-timed pipelined datapath for square rooting." IEE Proceedings - Circuits, Devices and Systems 146, no. 1 (1999): 16. http://dx.doi.org/10.1049/ip-cds:19990271.

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16

Arató, Péter, lstván Béres, Andrzej Rucinski, Robert Davis, and Roy Torbert. "A high-level datapath synthesis method for pipelined structures." Microelectronics Journal 25, no. 3 (1994): 237–47. http://dx.doi.org/10.1016/0026-2692(94)90015-9.

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17

Xianwu Xing and Ching Chuen Jong. "Multivoltage Multifrequency Low-Energy Synthesis for Functionally Pipelined Datapath." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 17, no. 9 (2009): 1348–52. http://dx.doi.org/10.1109/tvlsi.2008.2002684.

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18

Nabi, Syed Waqar, and Wim Vanderbauwhede. "Automatic Pipelining and Vectorization of Scientific Code for FPGAs." International Journal of Reconfigurable Computing 2019 (November 18, 2019): 1–12. http://dx.doi.org/10.1155/2019/7348013.

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There is a large body of legacy scientific code in use today that could benefit from execution on accelerator devices like GPUs and FPGAs. Manual translation of such legacy code into device-specific parallel code requires significant manual effort and is a major obstacle to wider FPGA adoption. We are developing an automated optimizing compiler TyTra to overcome this obstacle. The TyTra flow aims to compile legacy Fortran code automatically for FPGA-based acceleration, while applying suitable optimizations. We present the flow with a focus on two key optimizations, automatic pipelining and vec

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19

Sergiyenko, A. M., V. A. Romankevich, and A. A. Serhienko. "Genetic Programming of Application-Specific Pipelined Datapaths." Èlektronnoe modelirovanie 42, no. 2 (2020): 25–40. http://dx.doi.org/10.15407/emodel.42.02.025.

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20

Arató, Péter, Zoltán Ádám Mann, and András Orbán. "Time-constrained scheduling of large pipelined datapaths." Journal of Systems Architecture 51, no. 12 (2005): 665–87. http://dx.doi.org/10.1016/j.sysarc.2005.02.001.

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21

Hong-Shin Jun and Sun-Young Hwang. "Design of a pipelined datapath synthesis system for digital signal processing." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2, no. 3 (1994): 292–303. http://dx.doi.org/10.1109/92.311638.

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22

Koch, Andreas. "Efficient Integration of Pipelined IP Blocks into Automatically Compiled Datapaths." EURASIP Journal on Embedded Systems 2007 (2007): 1–9. http://dx.doi.org/10.1155/2007/65173.

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23

Koch, Andreas. "Efficient Integration of Pipelined IP Blocks into Automatically Compiled Datapaths." EURASIP Journal on Embedded Systems 2007, no. 1 (2007): 065173. http://dx.doi.org/10.1186/1687-3963-2007-065173.

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24

Sergiyenko, A. M., and I. V. Mozghovyi. "Hardware Decompressor Design." Èlektronnoe modelirovanie 45, no. 5 (2023): 113–28. http://dx.doi.org/10.15407/emodel.45.05.113.

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The common lossless compression algorithms were analyzed, and the LZW algorithm was selected for the hardware implementation. To express parallelism, this algorithm is represented as a cyclo-dynamic dataflow (CDDF). A hardware synthesis method for designing pipelined datapath is proposed, which optimizes CDDF considering the features of the FPGA primitives and maps it to hardware using VHDL language description. Using this method, an LZW de¬compressor is developed, which exhibits a high performance-to-hardware cost ratio. The de¬com¬¬¬pressor can be utilized in communication channels and other

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25

Jin, Zheming, and Jason D. Bakos. "A Heuristic Scheduler for Port-Constrained Floating-Point Pipelines." International Journal of Reconfigurable Computing 2013 (2013): 1–9. http://dx.doi.org/10.1155/2013/849545.

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We describe a heuristic scheduling approach for optimizing floating-point pipelines subject to input port constraints. The objective of our technique is to maximize functional unit reuse while minimizing the following performance metrics in the generated circuit: (1) maximum multiplexer fanin, (2) datapath fanout, (3) number of multiplexers, and (4) number of registers. For a set of systems biology markup language (SBML) benchmark expressions, we compare the resource usages given by our method to those given by a branch-and-bound enumeration of all valid schedules. Compared with the enumeratio

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26

Han, Liang, Jie Chen, and Xiaodong Chen. "Power optimization for the datapath of a 32-bit reconfigurable pipelined DSP processor." Journal of Electronics (China) 22, no. 6 (2005): 650–57. http://dx.doi.org/10.1007/bf02687846.

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27

Yoo, Hee-Jin, Ju-Young Oh, Jun-Yong Lee, and Do-Soon Park. "A Scheduling Approach using Gradual Mobility Reduction for Synthesizing Pipelined Datapaths." KIPS Transactions:PartA 9A, no. 3 (2002): 379–86. http://dx.doi.org/10.3745/kipsta.2002.9a.3.379.

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28

Jin, Seunghun, Dongkyun Kim, Thuy Tuong Nguyen, Daijin Kim, Munsang Kim, and Jae Wook Jeon. "Design and Implementation of a Pipelined Datapath for High-Speed Face Detection Using FPGA." IEEE Transactions on Industrial Informatics 8, no. 1 (2012): 158–67. http://dx.doi.org/10.1109/tii.2011.2173943.

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29

Nummer, Muhammad, and Manoj Sachdev. "Experimental Results for Slow-speed Timing Characterization of High-speed Pipelined Datapaths." Journal of Electronic Testing 27, no. 1 (2010): 9–17. http://dx.doi.org/10.1007/s10836-010-5186-3.

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30

Guo, Wei, KwangHyok Ri, Luping Cui, and Jizeng Wei. "An Area-Efficient Unified Architecture for Multi-Functional Double-Precision Floating-Point Computation." Journal of Circuits, Systems and Computers 24, no. 10 (2015): 1550151. http://dx.doi.org/10.1142/s0218126615501510.

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In this paper, we propose a unified architecture for computation of double-precision floating-point division, reciprocal, square root, inverse square root and multiplication with a significant area reduction. First, a double-precision multiplication-based divider, the common datapath shared with these arithmetic computations, is optimized by a modified Goldschmidt algorithm to achieve better area efficiency. In this algorithm, a linear-degree minimax approximation instead of second-degree is used to obtain a 15-bit precision estimate of the reciprocal so that we can get a rather small lookup t

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31

Chowdhury, Shubhajit Roy, Dipankar Chakrabarti, and Hiranmay Saha. "FPGA realization of a smart processing system for clinical diagnostic applications using pipelined datapath architectures." Microprocessors and Microsystems 32, no. 2 (2008): 107–20. http://dx.doi.org/10.1016/j.micpro.2007.12.001.

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32

Salehi, Sayed Ahmad, Rasoul Amirfattahi, and Keshab K. Parhi. "Pipelined Architectures for Real-Valued FFT and Hermitian-Symmetric IFFT With Real Datapaths." IEEE Transactions on Circuits and Systems II: Express Briefs 60, no. 8 (2013): 507–11. http://dx.doi.org/10.1109/tcsii.2013.2268411.

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33

Yin, Xiao-Bo, Feng Yu, and Zhen-Guo Ma. "Resource-Efficient Pipelined Architectures for Radix-2 Real-Valued FFT With Real Datapaths." IEEE Transactions on Circuits and Systems II: Express Briefs 63, no. 8 (2016): 803–7. http://dx.doi.org/10.1109/tcsii.2016.2530862.

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34

Wilson, T. C., N. Mukherjee, M. K. Garg, and D. K. Banerji. "An ILP Solution for Optimum Scheduling, Module and Register Allocation, and Operation Binding in Datapath Synthesis." VLSI Design 3, no. 1 (1995): 21–36. http://dx.doi.org/10.1155/1995/23249.

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We present an integrated and optimal solution to the problems of operator scheduling, module and register allocation, and operator binding in datapath synthesis. The solution is based on an integer linear programming (ILP) model that minimizes a weighted sum of module area and total execution time under very general assumptions of module capabilities. In particular, a module may execute an arbitrary combination of operations, possibly using different numbers of control steps for different operations. Furthermore, operations may be implemented by a variety of modules, possibly requiring differe

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35

Livramento, Vinícius Dos S., Bruno G. Moraes, Brunno A. Machado, Eduardo Boabaid, and José Luiz Güntzel. "Evaluating the Impact of Architectural Decisions on the Energy Efficiency of FDCT/IDCT Configurable IP Cores." Journal of Integrated Circuits and Systems 7, no. 1 (2012): 23–36. http://dx.doi.org/10.29292/jics.v7i1.353.

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The development of mobile multimedia devices follows the platform-based design methodology in which IP cores are the building blocks. In the context of mobile devices there is a concern of battery lifetime which leads to the need of energy-efficient IP cores. This paper presents four energy-efficient FDCT/IDCT configurable IP cores. These architectures are based on Massimino’s algorithm, which was chosen due to its high accuracy and parallelism. The four architectures were built by combining fully-combinational or pipelined datapaths, using either a single or two 1-D DCT blocks with a transpos

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36

Josipović, Lana, Shabnam Sheikhha, Andrea Guerrieri, Paolo Ienne, and Jordi Cortadella. "Buffer Placement and Sizing for High-Performance Dataflow Circuits." ACM Transactions on Reconfigurable Technology and Systems 15, no. 1 (2022): 1–32. http://dx.doi.org/10.1145/3477053.

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Commercial high-level synthesis tools typically produce statically scheduled circuits. Yet, effective C-to-circuit conversion of arbitrary software applications calls for dataflow circuits, as they can handle efficiently variable latencies (e.g., caches), unpredictable memory dependencies, and irregular control flow. Dataflow circuits exhibit an unconventional property: registers (usually referred to as “buffers”) can be placed anywhere in the circuit without changing its semantics, in strong contrast to what happens in traditional datapaths. Yet, although functionally irrelevant, this placeme

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37

Soliman, Mostafa I., and Elsayed A. Elsayed. "Simultaneous Multithreaded Matrix Processor." Journal of Circuits, Systems and Computers 24, no. 08 (2015): 1550114. http://dx.doi.org/10.1142/s0218126615501145.

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This paper proposes a simultaneous multithreaded matrix processor (SMMP) to improve the performance of data-parallel applications by exploiting instruction-level parallelism (ILP) data-level parallelism (DLP) and thread-level parallelism (TLP). In SMMP, the well-known five-stage pipeline (baseline scalar processor) is extended to execute multi-scalar/vector/matrix instructions on unified parallel execution datapaths. SMMP can issue four scalar instructions from two threads each cycle or four vector/matrix operations from one thread, where the execution of vector/matrix instructions in threads

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38

John, Elwyn G., Z. Ghassemlooy, Malcolm Woolfson, et al. "Book Reviews: A Guide to Microsoft Excel for Scientists and Engineers, Fiber Bragg Gratings, Signal Detection Theory, Analog BiCMOS Design: Practices and Pitfalls, High Level Synthesis of Pipelined Datapaths, Electronic Control of Switched Reluctance Machines, Power Quality Primer." International Journal of Electrical Engineering & Education 39, no. 2 (2002): 175–80. http://dx.doi.org/10.7227/ijeee.39.2.9.

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39

Mohd Hakimi Zohari, Mohd Shamian Zainal, and Azlina Bahari. "Design and Implementation of a MIPS Datapath." International Journal of Advanced Research in Science, Communication and Technology, December 10, 2024, 512–16. https://doi.org/10.48175/ijarsct-22669.

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Finally, the integration of these individual components culminates in the execution of the complete MIPS datapath. The MIPS (Microprocessor without Interlocked Pipeline Stages) architecture serves as a widely recognized and utilized instruction set architecture. Implementing the complete datapath involves orchestrating the flow of instructions through the CPU, from instruction fetch to execution and memory access, showcasing the culmination of our efforts in crafting a functional and efficient processor. In essence, this project not only provides a hands-on experience in HDL-based digital desi

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40

Wenjun, Wang. "Performance Enhancement with Speculative-Trace Capping at Different Pipeline Stages in Simultaneous Multi-Threading Processors." November 1, 2016. https://doi.org/10.5281/zenodo.1193984.

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Simultaneous Multi-Threading (SMT) processors improve system performance by allowing concurrent execution of multiple independent threads with sharing key datapath components and better utilization of resources. Speculative execution allows modern processors to fetch continuously and reduce the delays of control instructions. However, a significant amount of resources is usually wasted due to miss-speculation, which could have been used by other valid instructions, and such a waste is even more pronounced in an SMT system. In order to minimize the waste of resources, a speculative trace cappin

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41

Kashima, Ryota, Ikki Nagaoka, Tomoki Nakano, Masamitsu Tanaka, Taro Yamashita, and Akira Fujimaki. "Lowering Latency in a High-Speed Gate-Level-Pipelined Single Flux Quantum Datapath Using an Interleaved Register File." IEEE Transactions on Applied Superconductivity, 2023, 1–6. http://dx.doi.org/10.1109/tasc.2023.3249131.

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42

Hafiz, ul Azad, V.Lazic Dragan, and Shahid Waqar. "FPGA Based Longitudinal and Lateral Controller Implementation for a Small UAV." October 22, 2010. https://doi.org/10.5281/zenodo.1081221.

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This paper presents implementation of attitude controller for a small UAV using field programmable gate array (FPGA). Due to the small size constrain a miniature more compact and computationally extensive; autopilot platform is needed for such systems. More over UAV autopilot has to deal with extremely adverse situations in the shortest possible time, while accomplishing its mission. FPGAs in the recent past have rendered themselves as fast, parallel, real time, processing devices in a compact size. This work utilizes this fact and implements different attitude controllers for a small UAV in F

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43

"Energy-Efficient and High-throughput Implementations of Lightweight Block Cipher." International Journal of Innovative Technology and Exploring Engineering 9, no. 2S (2019): 35–41. http://dx.doi.org/10.35940/ijitee.b1022.1292s19.

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Security in resource-constrained devices has drawn the great attentions to researchers in recent years. To make secure transmission of critical information in such devices, lightweight cryptography algorithms come in light to large extend. KLEIN has been popular lightweight block cipher used to overcome such issues. In this paper, different architectures of KLEIN block cipher are presented. One of designs enhances the efficiency with regard to the throughput at the expense of a larger area. In order to make such designs, the pipelined registers are placed on different positions in datapath alg

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