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1
Glaser, Ulrich. "Complex ESD protection elements and issues in decananometre CMOS technologies /". Zürich : ETH, 2007. http://e-collection.ethbib.ethz.ch/show?type=diss&nr=16960.
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Pan, Zhihao [Verfasser]. "Modeling and optimization of discrete ESD protection devices / Zhihao Pan". München : Verlag Dr. Hut, 2015. http://d-nb.info/1074063724/34.
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Cao, Yiqun [Verfasser], Stephan [Akademischer Betreuer] Frei y Bernd [Gutachter] Deutschmann. "High-voltage ESD structures and ESD protection concepts in smart power technologies / Yiqun Cao ; Gutachter: Bernd Deutschmann ; Betreuer: Stephan Frei". Dortmund : Universitätsbibliothek Dortmund, 2019. http://d-nb.info/1200209605/34.
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Cui, Qiang. "On-Chip Electro-Static Discharge (ESD) Protection for Radio-Frequency Integrated Circuits". Doctoral diss., University of Central Florida, 2013. http://digital.library.ucf.edu/cdm/ref/collection/ETD/id/5620.
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Electrostatic Discharge (ESD) phenomenon is a common phenomenon in daily life and it could damage the integrated circuit throughout the whole cycle of product from the manufacturing. Several ESD stress models and test methods have been used to reproduce ESD events and characterize ESD protection device's performance. The basic ESD stress models are: Human Body Model (HBM), Machine Model (MM), and Charged Device Model (CDM). On-chip ESD protection devices are widely used to discharge ESD current and limit the overstress voltage under different ESD events. Some effective ESD protection devices were reported for low speed circuit applications such as analog ICs or digital ICs in CMOS process. On the contrast, only a few ESD protection devices available for radio frequency integrated circuits (RF ICs). ESD protection for RF ICs is more challenging than traditional low speed CMOS ESD protection design because of the facts that: (1) Process limitation: High-performance RF ICs are typically fabricated in compound semiconductor process such as GaAs pHEMT and SiGe HBT process. And some proved effective ESD devices (e.g. SCR) are not able to be fabricated in those processes due to process limitation. Moreover, compound semiconductor process has lower thermal conductivity which will worsen its ESD damage immunity. (2) Parasitic capacitance limitation: Even for RF CMOS process, the inherent parasitic capacitance of ESD protection devices is a big concern. Therefore, this dissertation will contribute on ESD protection designs for RF ICs in all the major processes including GaAs pHEMT, SiGe BiCMOS and standard CMOS. The ESD protection for RF ICs in GaAs pHEMT process is very difficult, and the typical HBM protection level is below 1-kV HBM level. The first part of our work is to analyze pHEMT's snapback, post-snapback saturation and thermal failure under ESD stress using TLP-like Sentaurus TCAD simulation. The snapback is caused by virtual bipolar transistor due to large electron-hole pairs impacted near drain region. Post-snapback saturation is caused by temperature-induced mobility degradation due to III-V compound semiconductor materials' poor thermal conductivity. And thermal failure is found to be caused by hot spot located in pHEMT's InGaAs layer. Understanding of these physical mechanisms is critical to design effective ESD protection device in GaAs pHEMT process. Several novel ESD protection devices were designed in 0.5um GaAs pHEMT process. The multi-gate pHEMT based ESD protection devices in both enhancement-mode and depletion-mode were reported and characterized then. Due to the multiple current paths available in the multi-gate pHEMT, the new ESD protection clamp showed significantly improved ESD performances over the conventional single-gate pHEMT ESD clamp, including higher current discharge capability, lower on-state resistance, and smaller voltage transient. We proposed another further enhanced ESD protection clamp based on a novel drain-less, multi-gate pHEMT in a 0.5um GaAs pHEMT technology. Based on Barth 4002 TLP measurement results, the ESD protection devices proposed in this chapter can improve the ESD level from 1-kV (0.6 A It2) to up to 8-kV (> 5.2 A It2) under HBM. Then we optimized SiGe-based silicon controlled rectifiers (SiGe SCR) in SiGe BiCMOS process. SiGe SCR is considered a good candidate ESD protection device in this process. But the possible slow turn-on issue under CDM ESD events is the major concern. In order to optimize the turn-on performance of SiGe SCR against CDM ESD, the Barth 4012 very fast TLP (vfTLP) and vfTLP-like TCAD simulation were used for characterization and analysis. It was demonstrated that a SiGe SCR implemented with a P PLUG layer and minimal PNP base width can supply the smallest peak voltage and fastest response time which is resulted from the fact that the impact ionization region and effective base width in the SiGe SCR were reduced due to the presence of the P PLUG layer. This work demonstrated a practical approach for designing optimum ESD protection solutions for the low-voltage/radio frequency integrated circuits in SiGe BiCMOS process. In the end, we optimized SCRs in standard silicon-based CMOS process to supply protection for high speed/radio-frequency ICs. SCR is again considered the best for its excellent current handling ability. But the parasitic capacitance of SCRs needs to be reduced to limit SCR's impact to RF performance. We proposed a novel SCR-based ESD structure and characterize it experimentally for the design of effective ESD protection in high-frequency CMOS based integrated circuits. The proposed SCR-based ESD protection device showed a much lower parasitic capacitance and better ESD performance than the conventional SCR and a low-capacitance SCR reported in the literature. The physics underlying the low capacitance was explained by measurements using HP 4284 capacitance meter. Throughout the dissertation work, all the measurements are mainly conducted using Barth 4002 transimission line pulsing (TLP) and Barth 4012 very fast transmission line pulsing (vfTLP) testers. All the simulation was performed using Sentaurus TCAD tool from Synopsys.Ph.D.
Doctorate
Electrical Engineering and Computer Science
Engineering and Computer Science
Electrical Engineering
5
Diatta, Marianne Amemagne. "Fiabilité des diodes de protection ESD soumises à des décharges électrostatiques répétitives". Toulouse 3, 2012. http://thesesups.ups-tlse.fr/4126/.
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La sensibilité des composants vis-à-vis des décharges électrostatiques (ESD) reste d'actualité avec la réduction des dimensions technologiques. En effet, les développements industriels et la sévérité de l'environnement subi par les applications électroniques qui sont devenues de plus en plus portatives mènent aujourd'hui au durcissement des conditions de fiabilité requises par les clients. Des spécifications initialement limitées aux systèmes électroniques se voient désormais étendues aux circuits intégrés pour atteindre les composants discrets. Afin de garantir d'excellents niveaux de fiabilité ESD notamment en répétitif, la méthodologie qui a été mise en œuvre consiste à comprendre des mécanismes de dégradation en ESD répétitives à travers les moyens de caractérisation physique, électrique et de simulation électrothermique. En effet, une nouvelle spécification client exige non seulement une immunité ESD de 15 kV pour une norme de type IEC 61000-4-2 mais aussi réclame une garantie de la non dégradation de ses fonctionnalités suite à la répétition de 1000 décharges de 15 kV sur le circuit intégré. Ainsi, la diode bidirectionnelle très souvent localisée en entrée et en sortie des circuits intégrés et permettant ainsi d'assurer leur protection vis-à-vis des décharges électrostatiques (ESD) pouvant surgir durant la durée de vie du système constitue le composant à la base de notre étude. Les investigations physiques de la défaillance ont permis de redessiner le scénario de dégradation en définissant la nature du défaut et sa génération, d'origine structurale pour ainsi décrire son évolution jusqu'à la défaillance. Associer la simulation électrothermique aux résultats expérimentaux permet de confirmer des phénomènes physiques tels que les phénomènes d'électro-thermo-migration surgissant durant une ESD. A l'issue de ces analyses, l'optimisation de la fiabilité de la diode en endurance est confirmée grâce à la suppression du défaut initial par l'amélioration du processus de fabricationThe sensitiveness of components towards electrostatic discharges (ESD) remains a key point in the frame of shrinked technologies. Indeed, industrial developments associated to a harsh environment for more and more smart electronic applications lead to aggressive reliability requirements by customer. Hence, specifications initially dedicated to electronic systems extends to integrated circuits then discrete components. In fact, customers require, in addition to the 15kV robustness for IEC 61000-4-2 norm, to withstand ESD reliability level by specifying immunity of the integrated circuit after applying 1000 discharges of 15kV level. To guarantee this ESD reliability level, especially in a repetitive mode, the methodology developed in this study consists in the understanding of failure mechanisms through physical and electrical characterizations associated to electro-thermal simulations. In integrated circuits, bidirectional diodes often localized at the input and output ensure a protection towards ESD that could occurs during system lifetime. In this context, the study particularly focuses on this discrete protection diode. Physical investigations on repetitive ESD failures describe the failure mechanism from structural defect creation to destruction. Moreover, gathering electro-thermal simulations to experimental results confirms appearance of electro-thermo-migration physical phenomenon during repetitive ESD. As a conclusion, removing the structural defects through a metal barrier considerably improves the ESD endurance and fully satisfy customer requirements while preserving intrinsic performances
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Lim, Tek Fouy. "Dispositifs de protection contre les décharges électrostatiques pour les applications radio fréquences et millimétriques". Thesis, Grenoble, 2013. http://www.theses.fr/2013GRENT033/document.
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Ces travaux s'inscrivent dans un contexte où les contraintes vis-à-vis des décharges électrostatiques sont de plus en plus fortes, les circuits de protection sont un problème récurrent pour les circuits fonctionnant à hautes fréquences. La capacité parasite des composants de protection limite fortement la transmission du signal et peut perturber fortement le fonctionnement normal d'un circuit. Les travaux présentés dans ce mémoire font suite à une volonté de fournir aux concepteurs de circuits fonctionnant aux fréquences millimétriques un circuit de protection robuste présentant de faibles pertes en transmission, avec des dimensions très petites et fonctionnant sur une très large bande de fréquences, allant du courant continu à 100 GHz. Pour cela, une étude approfondie des lignes de transmission et des composants de protection a été réalisée à l'aide de simulations électromagnétiques et de circuits. Placés et fragmentées le long de ces lignes de transmission, les composants de protection ont été optimisés afin de perturber le moins possible la transmission du signal, tout en gardant une forte robustesse face aux décharges électrostatiques. Cette stratégie de protection a été réalisée et validée en technologies CMOS avancées par des mesures fréquentielles, électriques et de courant de fuiteAdvanced CMOS technologies provide an easier way to realize radio-frequency integrated circuits (RFICs). However, the lithography dimension shrink make electrostatic discharges (ESD) issues become more significant. Specific ESD protection devices are embedded in RFICs to avoid any damage. Unfortunately, ESD protections parasitic capacitance limits the operating bandwidth of RFICs. ESD protection size dimensions are also an issue for the protection of RFICs, in order to avoid a significant increase in production costs. This work focuses on a broadband ESD solution (DC-100 GHz) able to be implemented in an I/O pad to protect RFICs in advanced CMOS technologies. Thanks to the signal transmission properties of coplanar / microstrip lines, a broadband ESD solution is achieved by implementing ESD components under a transmission line. The silicon proved structure is broadband; it can be used in any RF circuits and fulfill ESD target. The physical dimensions also enable easy on-chip integration
7
SALCEDO, Javier. "DESIGN AND CHARACTERIZATION OF NOVELDEVICES FOR NEW GENERATION OF ELECTROSTATICDISCHARGE (ESD) PROTECTION STRUCTURES". Doctoral diss., University of Central Florida, 2006. http://digital.library.ucf.edu/cdm/ref/collection/ETD/id/2812.
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The technology evolution and complexity of new circuit applications involve emerging reliability problems and even more sensitivity of integrated circuits (ICs) to electrostatic discharge (ESD)-induced damage. Regardless of the aggressive evolution in downscaling and subsequent improvement in applications' performance, ICs still should comply with minimum standards of ESD robustness in order to be commercially viable. Although the topic of ESD has received attention industry-wide, the design of robust protection structures and circuits remains challenging because ESD failure mechanisms continue to become more acute and design windows less flexible. The sensitivity of smaller devices, along with a limited understanding of the ESD phenomena and the resulting empirical approach to solving the problem have yielded time consuming, costly and unpredictable design procedures. As turnaround design cycles in new technologies continue to decrease, the traditional trial-and-error design strategy is no longer acceptable, and better analysis capabilities and a systematic design approach are essential to accomplish the increasingly difficult task of adequate ESD protection-circuit design. This dissertation presents a comprehensive design methodology for implementing custom on-chip ESD protection structures in different commercial technologies. First, the ESD topic in the semiconductor industry is revised, as well as ESD standards and commonly used schemes to provide ESD protection in ICs. The general ESD protection approaches are illustrated and discussed using different types of protection components and the concept of the ESD design window. The problem of implementing and assessing ESD protection structures is addressed next, starting from the general discussion of two design methods. The first ESD design method follows an experimental approach, in which design requirements are obtained via fabrication, testing and failure analysis. The second method consists of the technology computer aided design (TCAD)-assisted ESD protection design. This method incorporates numerical simulations in different stages of the ESD design process, and thus results in a more predictable and systematic ESD development strategy. Physical models considered in the device simulation are discussed and subsequently utilized in different ESD designs along this study. The implementation of new custom ESD protection devices and a further integration strategy based on the concept of the high-holding, low-voltage-trigger, silicon controlled rectifier (SCR) (HH-LVTSCR) is demonstrated for implementing ESD solutions in commercial low-voltage digital and mixed-signal applications developed using complementary metal oxide semiconductor (CMOS) and bipolar CMOS (BiCMOS) technologies. This ESD protection concept proposed in this study is also successfully incorporated for implementing a tailored ESD protection solution for an emerging CMOS-based embedded MicroElectroMechanical (MEMS) sensor system-on-a-chip (SoC) technology. Circuit applications that are required to operate at relatively large input/output (I/O) voltage, above/below the VDD/VSS core circuit power supply, introduce further complications in the development and integration of ESD protection solutions. In these applications, the I/O operating voltage can extend over one order of magnitude larger than the safe operating voltage established in advanced technologies, while the IC is also required to comply with stringent ESD robustness requirements. A practical TCAD methodology based on a process- and device- simulation is demonstrated for assessment of the device physics, and subsequent design and implementation of custom P1N1-P2N2 and coupled P1N1-P2N2//N2P3-N3P1 silicon controlled rectifier (SCR)-type devices for ESD protection in different circuit applications, including those applications operating at I/O voltage considerably above/below the VDD/VSS. Results from the TCAD simulations are compared with measurements and used for developing technology- and circuit-adapted protection structures, capable of blocking large voltages and providing versatile dual-polarity symmetric/asymmetric S-type current-voltage characteristics for high ESD protection. The design guidelines introduced in this dissertation are used to optimize and extend the ESD protection capability in existing CMOS/BiCMOS technologies, by implementing smaller and more robust single- or dual-polarity ESD protection structures within the flexibility provided in the specific fabrication process. The ESD design methodologies and characteristics of the developed protection devices are demonstrated via ESD measurements obtained from fabricated stand-alone devices and on-chip ESD protections. The superior ESD protection performance of the devices developed in this study is also successfully verified in IC applications where the standard ESD protection approaches are not suitable to meet the stringent area constraint and performance requirement.Ph.D.
School of Electrical Engineering and Computer Science
Engineering and Computer Science
Electrical Engineering
8
Courivaud, Bertrand. "Développement et réalisation de nouvelles structures de protection contre les décharges électrostatiques". Thesis, Toulouse 3, 2015. http://www.theses.fr/2015TOU30273/document.
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Le cadre de cette étude se focalise sur le développement de protections contre les décharges électrostatiques (ESD) externes aux composants électroniques à protéger. Pour des raisons applicatives, ou l'encombrement devient une préoccupation majeure, ces protections ESD doivent répondre à des contraintes de taille toujours plus difficiles à satisfaire tout en gardant les mêmes performances en robustesse. Ce travail présente un nouveau concept de structure de protection ESD bidirectionnel basé sur une technologie industrielle originellement dédié à la réalisation de capacités à haute densité d'intégration. Le procédé technologique possède une étape de fabrication de tranchées profonde qui est mise à profit dans cette étude pour la réalisation de diodes tridimensionnelles. L'optimisation de la configuration de ces structure a été menée par une étude théorique à l'aide des outils de simulation TCAD afin de mieux appréhender le fonctionnement physique et d'apporter des règles de conception. De nombreux résultats expérimentaux sont présentés et des comparaisons seront également menées afin de quantifier l'apport de cette nouvelle technologie. La meilleure configuration permet de garantir une réduction de 25% de la taille des structures tout en garantissant un niveau de robustesse élevéAs part of this study focuses on the development of external protection against electrostatic discharge (ESD) to the electronic components to protect. For many applicative reasons where taken area becomes a major concern, the ESD protection must meet size constraints increasingly difficult to satisfy while keeping the same performance in robustness. This work presents a new concept of bi-directional ESD protection structure based on industrial technology originally dedicated to achieving high-density integration capabilities. The technological process has a deep trench production step which is used in this study for the realization of three-dimensional diodes. Optimizing configuration of the structure was conducted by a theoretical study using TCAD simulation tools to better understand the physical functioning and provide design rules. Many experimental results are presented and comparisons will also be conducted to quantify the contribution of this new technology. The best configuration ensures a 25% reduction in the size of structures while ensuring a high level of robustness
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Solaro, Yohann. "Conception, fabrication et caractérisation de dispositifs innovants de protection contre les décharges électrostatiques en technologie FDSOI". Thesis, Grenoble, 2014. http://www.theses.fr/2014GRENT098/document.
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L’architecture FDSOI (silicium sur isolant totalement déserté) permet une amélioration significative du comportement électrostatique des transistors MOSFETs pour les technologies avancées et est employée industriellement à partir du noeud 28 nm.L’implémentation de protections contre les décharges électrostatiques (ESD pour« Electro Static Discharge ») dans ces technologies reste un défi. Alors que l’approche standard repose sur l’hybridation du substrat SOI (gravure de l’oxyde enterré : BOX)permettant de fabriquer des dispositifs de puissance verticaux, nous nous intéressons ici à des structures dans lesquelles la conduction s’effectue latéralement, dans le film de silicium. Dans ces travaux, des approches alternatives utilisant des dispositifs innovants(Z²-FET et BBC-T) sont proposées. Leurs caractéristiques statiques, quasi-statiques et transitoires sont étudiées, par le biais de simulations TCAD et de caractérisations électriquesFDSOI architecture (Fully Depleted Silicon On Insulator) allows a significantimprovement of the electrostatic behavior of the MOSFETs transistors for the advancedtechnologies. It is industrially employed from the 28 nm node. However, theimplementation of ESD (Electrostatic Discharges) protections in these technologies isstill a challenge. While the standard approach relies on SOI substrate hybridization (byetching the BOX (buried oxide)), allowing to fabricate vertical power devices, we focushere on structures where the current flows laterally, in the silicon film. In this work,alternative approaches using innovative devices (Z²-FET and BBC-T) are proposed. Theirstatic, quasi-static and transient characteristics are studied in detail, with TCADsimulations and electrical characterizations
10
Lu, Hsueh-Meng y 呂學銘. "New ESD Protection Circuits". Thesis, 2004. http://ndltd.ncl.edu.tw/handle/22693499839469841539.
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碩士國立臺灣科技大學
電子工程系
92
Due to the area-efficient, the SCR has become the best choice for ESD protection circuits. However, the behaviors of latchup and higher trigger voltage are the limitations for SCR’s application. Therefore, it is needed to pay much attention to design better ESD protection circuits in deep-submicron CMOS IC. In this thesis, we have proposed two new ESD protection circuits based on SCR structure. The performance of these protection circuits is really excellent when ESD event happened. One of the protection circuits is a highly latchup-immune stacked-MOSFET with silicon controlled rectifier (SM-SCR) device. The latchup effect could be avoided by using the stacked-MOSFET to turn on/off the SCR. Meanwhile, a zener diode and gate-coupled transistor can lower SM-SCR trigger voltage. The other protection circuit is a highly latchup-free ESD protection circuit with silicon controlled rectifier (LFSCR) device to demonstrate the effective ESD protection effect. The mechanism is to turn on/off the SCR by two MOSFETs during an ESD event. During the ESD event, the PMOS transistor is utilized to turn on SCR and the NMOS transistor to turn off SCR. Therefore the latchup effect can be easily eliminated by this device. Besides, the purpose of the zener diode and gate-coupled transistor could lower the trigger voltage. The implementation of these two on-chip protection circuits has been fabricated through National Science Council Chip-Implementation-Center (CIC). These two ESD protection circuits have been applied for patents in R.O.C. and U.S.A.
11
Yeh, Shih-Ping y 葉士平. "ESD Protection Technology for LCM". Thesis, 2003. http://ndltd.ncl.edu.tw/handle/13313551003104927055.
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碩士逢甲大學
電子工程所
91
This thesis will discuss Liquid Crystal Display module (LCM) Electro-Static Discharge(ESD) protection techniques. In order to up-grade the protection capability of LCM ESD, Also to build up LCM ESD protection design rule. This thesis will also survey ESD protection techniques in the component level and system level. Such as : Human body model(HBM)、Machine model(MM)、Charge device model(CDM)、Air discharge model、Contact discharge model, and to compare the speciality and experiment method between component level and system level for which based on the capability of integrated circuits protection. Add special LCM ESD protection design to verify and find out the best design conditions for increase LCM ESD protection. In addition to build up LCM ESD standards, We will also build up testing equipment for LCM in the ESD protection. It is also hope the proposed testing equipment and the test procedure can be applied in the industry as a dedicate ESD standard for LCMS. The experiment condition is base on the LCM for mobil phone. The constructure is Liquid crystal display(LCD)、Driver IC and Flexiable Printed Circuit board(FPC). Different protection design such as : Power protectind design、Resist protection design、Guard-Ring protection design、Induction protection design and shield protection design and so on. Judging from the above testing design. It is work on the improvement of ESD protection, will make LCMs to simulate the above protection design and build up mobile phone and ESD testing equipment. It is to be mentioned in this thesis under single protection design for LCM ESD. The performance is not as good as a multi protection design. So, it is proved that ESD protection design works on overall protection program. The ESD protection mentioned in this thesis is patent pending. The last in this thesis pointed out the best design of LCM ESD protection, LCM ESD level standard and LCM ESD testing equipment and build up the standard for LCM ESD protection design and experiment.
12
Jyh, Song Hung y 宋弘智. "ESD Protection Circuit for RF Circuits". Thesis, 2005. http://ndltd.ncl.edu.tw/handle/23574758446776708309.
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碩士大葉大學
電機工程學系碩士班
93
In this thesis, a electrostatic discharge(ESD) protection circuit has been designed for radio frequency(RF) power amplifier of DCS 1800 system. The TSMC 0.18um RF model, and Synopsys technology company's EDA tool have been used to simulation the class E Power Amplifier's RF parameter, and then, utilize HSPICE to simulate the ESD protection circuit. Finally, the ESD protection circuit has been added to class E power amplifier and to obtain the effect of ESD circuit on RF parameter, then adjust ESD protection circuit parameter to have less effect on RF parameters and can pass two thousand voltage of human body model(HBM) ESD stress.
13
董順萍. "ESD Protection of Handset Video Products". Thesis, 2006. http://ndltd.ncl.edu.tw/handle/44856322892750950042.
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Lai, Yu-Hsuan y 賴玉瑄. "ESD Protection Design for Broadband Circuits". Thesis, 2019. http://ndltd.ncl.edu.tw/handle/7ed5x8.
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Lin, Che-Shih y 林哲仕. "Study on Modeling of ESD Protection Devices for Circuit-Level ESD Simulation". Thesis, 2007. http://ndltd.ncl.edu.tw/handle/96451142963494812486.
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碩士國立交通大學
電機學院微電子奈米科技產業專班
95
In addition to high performance, low cost, and low power, reliability is also an important issue in the development of VLSI technologies. Damage caused by ESD (Electro-static Discharge) is a serious threat to VLSI reliability. It is well know that ESD failures constitute a major portion of customer returns, so it is important to provide ESD protection in the IC chip against ESD damages If an ESD stress current flows into internal circuits, it can cause internal damage. Therefore, it is necessary to predict ESD immunity, which depends on the circuit design and layout. At present, trial-and-error approaches still dominate in ESD design, which result resource-consuming iteration. ESD simulations for the protection circuits are effective for solving this problem. The purpose of thesis is to construct an ESD circuit simulation system based on the SPICE circuit simulator. Through the SPICE simulation, we can reduce design cycle. In our ESD protection network, we choose the diodes, BJT, and NMOS as ESD protection devices. We will model those devices corresponding to the experiment and implement the models to the ESD circuit simulation system.
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Liu, Rui-Hong y 劉睿閎. "ESD Protection Designs for 2.4GHz T/R Switch Front-End Circuits". Thesis, 2015. http://ndltd.ncl.edu.tw/handle/92182912861687902240.
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碩士國立交通大學
電子工程學系 電子研究所
104
As the CMOS technology develops so fast, radio-frequency integrated circuits (RF ICs) has been widely implemented in CMOS process. It has the advantage of a high integration and a low cost. Electrostatic discharge (ESD) has been one of the most serious reliability issues of CMOS processes, so ESD protection design is very important. However, undesirable parasitic effect is induced by the ESD protection design in RFICs. Consequently a successful RF ESD protection design needs well ESD protection ability and small parasitic effect. In this thesis, two RF ESD protection designs for T/R switch front-end circuit are proposed. The first one can reduce the parasitic effect and sustain ESD stress. The second one can sustain ESD stress without extra ESD protection device. Both ESD protection designs are applied to 2.4GHz T/R switch front-end circuit. An RF ESD protection design for traditional T/R switch front-end circuit is also proposed in this thesis. The number of the ESD protection devices is reduced in this design. Besides, silicon-controlled rectifier (SCR) is embedded in T/R switch, and the detection circuit, which is used in power-rail ESD clamp circuit, can sent trigger signals to trigger the SCR. The embedded SCR and parasitic diode can provide ESD discharge paths. Moreover, this ESD protection designs are applied to 2.4GHz traditional T/R switch front-end circuit.
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Lee, Chien-Ming y 李健銘. "ESD PROTECTION DESIGN FOR RADIO FREQUENCY CIRCUITS". Thesis, 2002. http://ndltd.ncl.edu.tw/handle/52615812726859233645.
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碩士國立交通大學
電子工程系
90
To reduce the parasitic effect of the ESD protection circuit devoted to RF integrated circuits, there are three major designs proposed in this thesis. In the first part, the two-port GSG measurement setup in the radio-frequency region (~GHz) is used to measure the power gain S21 and noise figure from different ESD devices in 0.25-µm CMOS process. Therefore, we can get the relationship between RF performance and ESD level among different ESD devices. The most suitable ESD device for RF application can be selected from the measured data. The second part presents a state-of-art ESD protection design for RF circuit with a human-body-model (HBM) ESD robustness of 8kV. By including a turn-on efficient power-rails ESD clamp circuit into the RF circuit, the ESD protection devices of the RF input pin can be operated in the forward-biased conduction, rather than the traditional junction breakdown condition. Therefore, the dimension of ESD devices for the RF input pin can be further downsized to reduce the input capacitance loading for the RF signal. This design has been successfully applied in a 900-MHz RF receiver and fabricated in a 0.25-µm CMOS process with a thick top metal layer. The experimental results have confirmed that its ESD robustness is as high as 8kV under the HBM ESD test. In the third part, a new structure of ESD protection circuit for RF application is proposed. The series LC-tank is used to block the signal loss and noise figure from the ESD protection devices to the RF input pin. The inductor is made by the top thick metal, which is suitable to conduct ESD current. The experimental results have shown that the RF performance of ESD protection circuit with LC-tank is superior to that of the traditional ESD protection circuit with double diodes. The ESD protection circuit with LC-tank is more suitable for RF application when the operation frequency becomes higher. The research results of this thesis have been applied 3 U.S. patents. Moreover, the contents of this thesis had also published three conference papers. One paper had been presented in the 2002 IEEE RFIC Symposium, the second paper has been accepted by the 2002 VLSI Design/CAD Symposium, and the third paper has been submitted to 2002 Taiwan ESD Conference.
18
Chen, Ming Hum y 陳銘輝. "The ESD Protection Design of Lateral DMOSFETs". Thesis, 2006. http://ndltd.ncl.edu.tw/handle/33355042408370259206.
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碩士大葉大學
電機工程學系碩士班
94
In recent years, many electric systems, such as automatic electronics, power switches, power rectifiers, and display drivers, have widely used power MOSFETs . In the future, the electric industry will develop power MOSFETs into high voltage, high current, and high speed switch modules. However, the problems of ESD still exist and are even more serious than intelligent circuit in low voltage process. Because electrical static discharge (ESD) problems are getting more and more serious, design of traditional ESD devices mostly utilizes trial and error, experimental measurements, or equal circuit simulations with SPICE to acquire proper protection devices. This research used computer simulation software TSUPREM-4 and MEDICI to simulate and improve the electrical property of device and to design a set of ESD protection circuits. Besides, this study also used the comparison results of the SCR layout parameters to make the electrical property of device performance meet the Design Window range and to reach the optimum of the ESD protection.
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Tsai, Ming-Yuan y 蔡明圜. "An ESD Protection Design of LCD Drivers". Thesis, 2007. http://ndltd.ncl.edu.tw/handle/26217304903479450127.
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碩士國立聯合大學
電子工程學系碩士班
95
In recent years, industries of LCD (Liquid Crystal Display) be progressed very quickly. When dots per inch (dpi), brightness and responding speed of LCDs are improved in every generation, the LCD driver IC must develop in the trend of high frequency and high voltage. Thus, the LCD driver IC must be met with high speed scanning and fast driving properties. By using the high-voltage property of LDMOS to act as a high-voltage devices in LCD driver ICs, in which it will be protected with an adjusting parameter of SCR device. The process simulator (TSUPRE-4) and device simulator (MEDICI) are used to simulate and evaluate the electrical property of high-voltage power device and to design an ESD protection element in this thesis. Eventually, a suitable trigger voltage and high holding voltage of SCR is used to act as an ESD protector which is very conformable for the request of LCD driver ICs.
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Yeh, Chun-Liang y 葉俊良. "Design and Analysis of ESD Protection Circuit". Thesis, 2005. http://ndltd.ncl.edu.tw/handle/74348641225871249510.
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碩士逢甲大學
電子工程所
93
In this proposal, we would be introducing a biasing circuit, which clamps the gate voltage when threshold reaches the maximum range. On the other hand, we use an N-WELL resistor to increase the resistance between gate and drain to allow ESD current flow to the wide bulk. This can improve the ESD protection level.
21
Tsai, Ming-Hsien y 蔡銘憲. "Design of Electrostatic Discharge (ESD) Protection for RF Front-End Integrated Circuits". Thesis, 2011. http://ndltd.ncl.edu.tw/handle/63142812027175306133.
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博士國立清華大學
電子工程研究所
99
By co-design methodology, this study focuses on ESD protection design techniques for RF front-end integrated circuits. In a wide frequency range (from a few GHz to millimeter wave up to V-band), the proposed circuits achieve excellent RF characteristics and high ESD protection level simultaneously. The design concept is to treat the ESD protection devices as a part of the input matching network to obtain the required ESD robustness without degrading the RF performance. For RF low-noise amplifiers (LNAs) operating at 5.8 GHz, three ESD protection topologies (dual-diode, modified-SCR, and modified-SCR with dual-diode) are investigated. We propose an ESD network with multiple ESD current paths, demonstrating a 4.3-A transmission line pulse (TLP) failure level, corresponding to a 6.5-kV human body model (HBM) protection level. In addition, a wideband LNA (2.6?{6.6 GHz) with shallow-trench-isolation (STI) diodes is realized. We propose a co-design methodology for the wideband LNA with ESD protection, demonstrating a 4-kV HBM ESD performance and no degradation on RF performance. Also, the chip area of ESD protection is much smaller compared to the published distributed ESD protection technique for wideband LNA applications. For millimeter-wave LNAs, the K-band and V-band LNAs using RF junction varactors with scalable models for ESD protection and noise optimization simultaneously are designed and realized. We propose of using the gate-source junction varactor used for noise optimization and charge device model (CDM) protection simultaneously, which has not been reported previously. A 24-GHz ESD-protected LNA presents a NF of 2.9 dB and a power gain of 15.2 dB, demonstrating a 2.7-A (corresponding to a 4-kV HBM) and an 11.4-A ESD protection levels using transmission line pulse (TLP) and very fast transmission line pulse (VFTLP) tests, respectively. In addition, the V-band LNA achieves a NF of 5.2 dB and a peak power gain of 10.9 dB at 51 GHz, achieving an over 2-kV ESD protection, and only 0.8-dB degradation for both NF and power gain compared with the reference design. Finally, an analog front-end circuit with dual-directional SCR ESD protection is designed and realized for passive UHF-band RFID tag. We propose a symmetrical dual-direction ESD protection technique, which is suitable for large signal swing of RFID tag application. The measured result shows ESD levels of 3.0-kV HBM and 200-V MM, respectively. The proposed ESD protection embedded in RFID tag becomes a must for yield improvement during antenna assembly or testing process.
22
Lubana, Sumanjit Singh. "CDM Robust & Low Noise ESD protection circuits". Thesis, 2009. http://hdl.handle.net/10012/4200.
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In spite of significant progress during last couple of decades, ESD still affects production yields, manufacturing costs, product quality, product reliability and profitability. The objective of an ESD protection circuit is to create a harmless shunting path for the static electricity before it damages the sensitive electronic circuits. As the devices are scaling
down, while ESD energy remains the same, VLSIs are becoming more vulnerable to ESD
stress. This higher susceptibility to ESD damage is due to thinner gate oxides and shallower junctions. Furthermore, higher operating frequency of the scaled technologies enforces lower
parasitic capacitance of the ESD protection circuits. Hence, increasing the robustness of the ESD protection circuits with minimum additional parasitic capacitance is the main challenge in state of the art CMOS processes. Furthermore with scaling, the integration of analog blocks such as ADC, PLL’s, DLL’s, oscillator etc. on digital chips has provided cheap system on chip (SOC) solutions. However, when analog and digital chip are combined into single mixed-signal chip, on-chip noise coupling from the digital to the analog circuitry through ESD protection circuits becomes a big concern. Thus, increasing supply noise isolation while ensuring the ESD protection robustness is also a big challenge. In this thesis, several ESD protection circuits and devices have been proposed to address the critical issues like increased leakage current, slower turn-on time of devices, increased
susceptibility to power supply isolation etc. The proposed ESD protection circuits/devices have been classified into two categories: Pad based ESD protection in which the ESD protection circuits are placed in the I/O pads, and Rail based ESD in which ESD protection circuit is placed between power supplies. In our research, both these aspects have been investigated. The Silicon Controlled Rectifier (SCR) based devices have been used for Pad ESD protection as they have highest ESD protection level per unit area. Two novel devices Darlington based SCR (DSCR) and NMOS Darlington based SCR (NMOS-DSCR) having faster turn-on time, lower first breakdown voltage and low capacitance have been proposed.
The transient clamps have been investigated and optimized for Rail based ESD protection. In this research, we have addressed the issue of leakage current in transient clamps. A methodology has been purposed to reduce the leakage current by more than
200,000 times without having major impact on the ESD performance. Also, the issue of noise
coupling from digital supply to analog supply through the ESD protection circuits has been addressed. A new transient clamp has been proposed to increase the power supply noise isolation. Finally, a new methodology of placement of analog circuit with respect to transient clamp has been proposed to further increase the power supply noise isolation.
23
Shih, Pi-Chia y 石弼嘉. "Transient Detection Circuit for System-Level ESD Protection". Thesis, 2005. http://ndltd.ncl.edu.tw/handle/d62dg9.
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蒙國軒. "ESD PROTECTION DESIGN FOR RADIO-FREQUENCY POWER AMPLIFIER". Thesis, 2007. http://ndltd.ncl.edu.tw/handle/td8ydz.
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碩士國立交通大學
電子工程系所
96
The aim of this thesis is to design the ESD protection circuits which are suitable in radio-frequency (RF) power amplifiers (PA). The ESD protection capability and the influence on the performance of the RF PA circuit after inserting the ESD protection circuit needs to be considered simultaneously. This thesis includes two RF PA ESD protection strategies which have been verified through two individual chips fabricated in standard 0.13-μm CMOS process. The first RF PA ESD protection strategy is to use an inductive ESD clamp which can be co-designed with the RF PA output matching network. An inductive device can distinguish ESD event which occupies the lower frequency spectrum from the normal RF signals. It acts as the low impedance discharging path for ESD current and provides specific impedance for RF signal. A MIMCAP in series of the signal line can block out the ESD current from directly penetrating into the active devices in RF PA core. The measurement results have verified this ESD protection strategy and proved that the proposed ESD protection technique indeed provides excellent ESD robustness of up to 8kV HBM ESD level and 400V MM ESD level. The second RF PA ESD protection strategy is to use capacitive ESD devices with low parasitic capacitances. Waffle-structured SCR and diodes are utilized to provide maximum discharging peripheral within a given layout area for minimizing the parasitic capacitance. The waffle-structured SCR is designed with ESD detection and trigger circuit to provide the best ESD protection capability while contributing minimal parasitic capacitance to the RF PA. The measurement results have verified the effectiveness of the proposed ESD protection strategy and proved that this ESD protection technique indeed provides excellent ESD robustness of up to 8kV HBM ESD level and 800V MM ESD level. Further, the measurement results also verify that an unprotected RF PA can not survive any single ESD zapping. RF PA circuitry is in urgent need of ESD protection with low parasitic effect.
25
CHANG, CHIH-YUAN y 張志遠. "Study on ESD Protection for IPS Liquid Crystals". Thesis, 2009. http://ndltd.ncl.edu.tw/handle/99024248921427015391.
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碩士逢甲大學
電機工程所
97
The problem has been studied for a long time that the electro-static has an influence of IC destruction or image sticking on LCD, especially the TFT-LCD which has been widely used now. Because its resistance from LC is higher, therefore, it’s difficult to remove the induced charges when it suffers from high anti-static voltage. Consequently, the time of image sticking will be very essential. This study will focus on doping a very small amount of nano-ITO doping into TFT-IPS LC, understand the impact on anti-ESD of LC cell ,and measure the characteristics of optics and electricity under the normal operating circumstance will be investigated. Through the experimental results, we could understand that doped nano-particles help removing the induced charges and enhancing the liquid crystal cell anti-ESD ability. But it has no influence on the optical and electrical properties of LC cells under the normal operating conditions. In comparison with TFT-TN LC, the high-resistance LC with doped nano-particles have similar effect about anti-ESD improvement. In addition, we also focus on the observation of the precipitation properties of nano-ITO. Through the intensive investigation, we found that the larger nano-particles are blocked near the injection hole, only the smaller particles would be transferred in the LC cell and without any precipitation.
26
Chien, Tuo-Hsin y 簡鐸欣. "Study on the High Performance ESD Protection Device". Thesis, 2006. http://ndltd.ncl.edu.tw/handle/65438849621718397285.
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Chen, Guan-Jhong y 陳冠中. "Vehicle HV Device Design & ESD protection Development". Thesis, 2009. http://ndltd.ncl.edu.tw/handle/26144657812673295297.
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碩士國立聯合大學
電子工程學系碩士班
97
In recent years, the automobile electron industry development unceasing forward progress, after all it represented the huge opportunity, average each household family has one an automobile at least. In the automobile electron part, no matter what is started by the vehicle power, however, the automobile electronic components increase greatly and the original 12V vehicle power is seem to be not enough. Therefore, the vehicle association develops the 12V/42V double electrical power system. However the HV process results in latch-up issues in ESD protection circuit under the high voltage situation, and this protection circuit will be tailed to protect the core circuit due to the longer trigger time. Then, in this work, we will focus on the investigation of HV 42V LDMOS especially in the vehicle application. Meanwhile, the output pin & power pin ESD protections will be studied in this thesis.
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Lee, Chun-Kuan y 李俊寬. "Reduction of Radiated Electric Fields for ESD Protection". Thesis, 2009. http://ndltd.ncl.edu.tw/handle/60736125153108478409.
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碩士元智大學
通訊工程學系
97
The measurement of radiated electric fields near the gap between two screws embedded in an acrylic bar discharged with an electrostatic discharge (ESD) gun was first conducted in an anechoic chamber. The finite-difference time-domain (FDTD) method was also used to calculate the radiated electric fields at frequencies of 80 MHz~1.0 GHz. It is shown that the measurement data makes a good agreement with the simulation results. From simulation results and measurement data, it is found that the radiated electric field decreases sharply as the frequency increases from 80 MHz to 1.0 GHz. After checking the validity of the FDTD method with measurement data, the FDTD method was then used to study the reduction of radiated electric fields produced by ESD events for the electromagnetic interference (EMI) immunity design. From the study of EMI immunity, it is found that the radiated ESD wave is a near-field phenomenon since the radiated electric field decreases dramatically as the distance from the test bar increases. It is also found that the maximum electric field radiated at a distance of 4 mm from the test bar can reach to 100 V/m at 80 MHz for an air-filled test bar. This high value of electric field may cause serious damage to integrated circuits. It is also found that the magnitude of radiated electric field decreases sharply if the air-filled test bar is filled with properly insulating materials.
29
Tsai, Shiang-Yu y 蔡翔宇. "ESD Protection Design for Radio-Frequency Integrated Circuits". Thesis, 2012. http://ndltd.ncl.edu.tw/handle/27794458231011003592.
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碩士國立交通大學
電子研究所
101
For the consideration of high integration and low cost, radio-frequency integrated circuits (RF ICs) have been fabricated in CMOS processes. Electrostatic discharge (ESD) is one of the most serious reliability issues of CMOS processes, and it also bothers RF IC designers now. A successful RF ESD protection design needs well ESD protection ability and small parasitic effect, since RF ICs are very sensitive to any extra parasitic effect. In this thesis, two RF ESD protection designs are proposed and verified. One is for RF circuits operating in 60 GHz. With the help of inductor and capacitor, the parasitic capacitance of ESD protection device can be effectively decreased and acceptable ESD level can be required. The other one is for RF power amplifier (PA). A Zener-diode-triggered silicon-controlled rectifier (ZTSCR) is used as an ESD protection device. In addition, two 2.4 GHz CMOS PAs with the proposed ZTSCR and power-rail ESD clamp circuit are designed as ESD-protected PAs to verify their ESD level. According to the experimental results, the ESD protection designs have high ESD robustness without degrading the RF performances.
30
Lan, Tzong-Hsiang y 藍宗祥. "The Study of ESD Protection Technologyfor Consumer Electronics". Thesis, 2005. http://ndltd.ncl.edu.tw/handle/00226740271099327045.
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碩士逢甲大學
資訊電機工程碩士在職專班
93
Abstract The thesis discuss that ESD destroy IC chip directly from circuit for wireless communication products and pocket electronic devices. For example, Cellular Mobile Phone、PDA、Smart Phone、MP3 player …, etc. In order to avoid breaking by ESD during go on for a long time and mass production, the paper focuses on the analysis and research of which be affect by ESD easily. Increasing resists ESD ability, basis on not only available ability but also special present ESD ideas for cellular phone in article. Find the best design way and prove it. This thesis includes four topics as follows: 1. Liquid crystal display module. 2. Naked keypad. 3. Flexible print circuit board. 4. Printed circuit board layout. Those methods mentioned in this thesis have been efficiently to prevent ESD and had applied for patents. I believe these ideas included design blueprint in advance will solve work, time and cost in the future.
31
Kuo, Bing-Jye y 郭秉捷. "ESD protection circuit design for broadband RF circuits". Thesis, 2004. http://ndltd.ncl.edu.tw/handle/66271258825451743916.
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碩士國立交通大學
電子工程系
92
The aim in this thesis is to design the ESD protection circuits which are suitable in broadband RF circuits. The ESD protection ability and the influence to the performance of the broadband RF circuit after inserting the ESD protection circuit needs to be considered simultaneously. This thesis includes three topics, which were verified through 3 individual chips. In the first topic, a new distributed ESD protection structure is proposed to achieve both good ESD and RF performance. The proposed decreasing-size distributed ESD (DS-DESD) protection circuit is constructed by arranging ESD protection stages with decreasing device-size and separating them by the coplanar waveguides with ground shield (CPWG). The scheme is not only beneficial to the broadband RF performance, but also to the ESD protection ability (human-body-model (HBM) ESD protection level over 8 kV). In the second topic, as a π model in ac analysis, the proposed π-model distributed ESD (π-DESD) protection circuit, composed of one pair of ESD components near the I/O pin, the other pair close to the core circuit, and a CPWG connecting these two pairs, can successfully achieve both the great ESD protection ability (HBM ESD level over 8 kV) and excellent broadband RF impedance match. In the third topic, two distributed ESD protection structures are presented and applied to DAs. Fabricated in a standard 0.25-μm CMOS process, the DA with the first ES-DESD protection structure, contributing extra 300 fF parasitic capacitance to the circuit, can sustain the HBM ESD level of 5.5 kV, the machine-model (MM) ESD level of 325 V and the charged-device-model (CDM) ESD level of 500 V, and exhibits the flat-gain of 4.7 ± 1 dB over the bandwidth from 1 to 10 GHz. With the same amount of the parasitic capacitance, the DA with the second DS-DESD protection achieves a better ESD robustness, the HBM ESD level over 8 kV, the MM ESD level of 575 V and the CDM ESD level of 650 V, and performs the flat-gain of 5.0 ± 1.1 dB over the bandwidth from 1 to 9 GHz. With these two proposed ESD protections, the broadband performances of the DAs are acceptable, yet the ESD protection abilities are excellent.
32
Altolaguirre, Federico Agustin y 艾飛. "Advanced ESD Protection Design for Nanoscale CMOS Processes". Thesis, 2016. http://ndltd.ncl.edu.tw/handle/12568380960145843350.
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博士國立交通大學
電機資訊國際學程
104
In order to achieve lower power consumption, higher operating speed, and higher integration capability, the CMOS features were continually scaled down with lower operating voltage, thinner gate oxide thickness, and smaller channel length in CMOS technology. However, when the CMOS technologies reached nanoscale dimensions, the gate leakage started becoming a serious issue. When transistors are fabricated with gate oxide of only a few nanometers thick, the gate-oxide-silicon direct tunneling current increases drastically, and thus it cannot longer be ignored. Combined with the increasingly low breakdown voltage, also as result of the thinner the gate oxide, the ESD protection design has become ever more challenging. Traditional ESD protection designs rely heavily in the use of large MOS transistors, used as ESD clamp and also as capacitors (used to detect ESD-like transients). Because of the large gate leakage current, such designs become very inefficient and undesirable for low-power applications. Moreover, some designs may become inoperative due to large voltage drops in the internal circuitry as result of the gate leakage. Previous research effort was focused on the reduction of the leakage current to acceptable levels. Some designs were proposed that effectively reduce the leakage current of the ESD protection circuits, but with an increase in the required silicon area as side effect. As result, due to the increase in fabrication cost per area in the advanced CMOS processes and enlarged area of the ESD protection circuits, ESD protection became more expensive. Therefore, research effort needs to be focused towards area minimization as well as leakage current reduction. Within the whole-chip ESD protection design scheme, the ESD clamp circuit will provide an effective ESD current discharging path under ESD stresses. In a good ESD protection arrangement, the ESD robustness is mainly decided by the ESD clamp circuit. However, the traditional design suffered the serious gate leakage issue in nanoscale CMOS processes due to a large capacitor used to detect the fast transient characteristic of ESD stresses. This capacitor also resulted in very large silicon footprints. Chapter 2 presents a level sensitive ESD detection circuit which does not use such capacitor, thus solving the leakage current and large silicon footprint issues. In addition, the ESD clamp trigger inverter was improved by adding diodes in series with the trigger transistors in order to further reduce the leakage current and increase the gate oxide reliability of such transistors, at the expense of a little area overhead due to the extra diodes added to the circuit. In addition to the level sensitive ESD detection circuit presented in Chapter 2, a transient sensitive ESD detection circuit is introduced in Chapter 3. In this case, the capacitor area is reduced by using a circuital technique known as capacitance boosting, which uses a current mirror connected in series to the capacitor to amplify its current, thus also amplifying the equivalent capacitance. By using this technique and mathematical analysis, the required silicon area of the ESD detection circuit can be minimized. In addition, a technique to fabricate an SCR with embedded trigger is presented, which can further reduce the silicon footprint of the ESD clamp circuit. Nowadays system-on-chip (SoC) ICs integrate circuits with different voltage levels. To ensure adequate ESD protection between the different IC blocks, ESD clamps with bidirectional functionality are often required. Typically, back-to-back diode (strings) were used to achieve this functionality, at the expense of large silicon footprint and somehow large leakage currents in the diode strings. Chapter 4 presents a bidirectional ESD protection circuit based on a dual SCR, which uses a novel symmetrical ESD detection and trigger circuit to control the dual SCR. This circuit is designed with focus on leakage current reduction as well as keeping a small silicon footprint. Typical ICs use different voltages for the IO and internal circuits. In addition, the ground lines are separated to avoid noise coupling between IO and internal circuits. As a result, these two power domains are separated, and thus the interface circuits become sensitive to ESD-related failure. Therefore, besides the ESD protection elements in each power domain, extra ESD protection elements are added between the power domains, thus increasing the required silicon area. Chapter 5 presents an ESD protection device embedding 4 SCRs that can fully protect the interface between two separated power domains, thus reducing the silicon footprint of the ESD protection elements.
33
Lin, Li Wei y 林立偉. "Study on whole-chip IC ESD protection circuit". Thesis, 2002. http://ndltd.ncl.edu.tw/handle/48787282088194238285.
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碩士國立臺灣科技大學
電子工程系
90
There are two main parts in this thesis. First, we study the characteristics of ESD protection at various temperatures and how to solve the ESD problem in a whole chip. Then, we concentrate our efforts on the tuning capacitors or varactors which are the commonly used devices in RF IC. As the VLSI operation speed has become more and more higher, the damages resulted by ESD have become a serious problem for integrated circuits. Therefore, to design a better ESD protection circuit can improve the qualities and yields of integrated circuits greatly. These ESD protection circuits are designed by the computer-aided IC layout software and fabricated through National Science Council Chip-Implementation-Center. In addition, because varactors are widely used in radio frequency circuits, we analyze the C-V characteristics of general inversion-mode and accumulation-mode MOS capacitors. By simulation of MEDICI, we can obtain the tuning C-V curves and design circuits to improve tuning voltage range in this way.
34
Fu, Wei-Hao y 傅偉豪. "Component-Level and System-Level ESD Protection Design". Thesis, 2017. http://ndltd.ncl.edu.tw/handle/k7229y.
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Feng, Yao-Wu y 馮耀武. "ESD Characteristics of Diffusion Resistor and its Application in On-chip ESD Protection Design". Thesis, 2009. http://ndltd.ncl.edu.tw/handle/10028854190621163628.
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碩士國立交通大學
電機學院碩士在職專班電子與光電組
97
The high current conduction in silicided N+ diffusion resistor and non-silicided N+ diffusion resistor under the 100nsec pulse condition had been characterized and modeled carefully in this work. We find the resistances of both types resistors change with the square root of the stress time. It induces the current decreasing and voltage increasing with the stress time. The root cause of the non-linear IV characteristics of the diffusion resistor under high current stress can be well explained by the Joule-heating induced the resistance change. In additional, we also find that these two diffusion resistors during high current stress will appear some different characteristics. Due to these different characteristics, the silicided device cannot use the same layout as the silicided blocking device on ESD protection design.
36
Chuang, Che-Hao y 莊哲豪. "ESD Protection Design with TVS (Transient Voltage Suppressor) to Meet System-Level ESD Specifications". Thesis, 2018. http://ndltd.ncl.edu.tw/handle/4h429h.
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LI, CHENG-TAO y 李承道. "The Near Field Measurement Technology for System Level ESD Testing and Optimization of ESD Protection". Thesis, 2018. http://ndltd.ncl.edu.tw/handle/8n3m95.
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碩士國立高雄大學
電機工程學系碩博士班
106
Consumer electronics products become more versatile and smaller in size, and the feature size of circuits becomes smaller, too. The main reason why the ability of resisting electrostatic discharge is weak is that the size of circuit is smaller. In the system level electrostatic discharge testing, the testing results of the Class B and the Class C are temporary failures. For engineers who design system level electrostatic discharge it is difficult to find broken circuit directly and it delay the schedule of new products development. If it can quickly find the location of broken circuit or discharge path by a detection method, it will not reduce the cost of product only. It can design guild rule for electrostatic discharge. For the above situation, this paper develops the time domain electrostatic discharge near field system. It combines time domain instrument with near field system to observe the magnetic field of DUT with time. In this paper, the circuit which has slot pattern is used to verify the measured results and observed the slot for impacting return current. After all, by researching the location of ferrite bead for optimizing electrostatic and signal integrity. In the future, it provides a new electrostatic discharge testing to find discharge path directly and establish the design guild for electrostatic discharge and power/signal integrity optimization.
38
Chang, Tai-Hung y 張台宏. "On Chip ESD Protection Design In A Power Chip". Thesis, 2000. http://ndltd.ncl.edu.tw/handle/28290813888272543142.
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碩士國立交通大學
電子工程系
88
The damages to CMOS VLSI circuits caused by static electronics is a very serious issue to CMOS VLSI design technologies. Especially, as the the technology is getting progress, the techniques that are used to improve the operation speed of CMOS circuits such as short channel length, thinner gate oxides, utilization of polyside and silicide, as well as the techniques to reduce the Hot-carrier effects such as LDD(Lightly Doped Drain) dramatically degrade the barring ability of ESD circuits. Due to the semiconductor process difference between high power CMOS circuits and low power CMOS circuits, we first implement a test chip with various high power CMOS process devices, then we measure all the characteristics that are related to ESD of the devices on the test chip. By analyzing these device characteristics, we can charactrize the effectiveness of ESD protection circuits and proposed new ESD protection circuits that are more efficient, especially for circuits with high power CMOS process. The ESD protection circuits we proposed can safely protect the CMOS circuits and make the ESD level confined to industrial application standard.
39
Liu, Xi-Hong y 劉士弘. "Floating-Anode ESD Protection Device for High-Voltage IC". Thesis, 2006. http://ndltd.ncl.edu.tw/handle/07134481359924710152.
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碩士清雲科技大學
電子工程研究所
94
A floating-anode SCR and lateral SCR fabricated in 0.6 CMOS process were investigated by the device simulation tool. These simulated electrical characteristics conform to the experimental results successfully. The I-V result of the floating-anode SCR indicates its 15.6V holding-voltage (Vh) has latch-up free immunity as compared with the lateral SCR and also a good 4KV ESD performance. And most importantly, the key factor in the operation of this floating anode SCR is the floating P+ anode. The hot spot had occurred near the anode of the floating-anode SCR because both electron and hole current flow through this electrode. The actual operation of the floating-anode SCR is controlled by the buried SCR in series with a reverse-biased diode as well as parasitic NPN BJT in the substrate. Additionally, the gate-coupled floating-electrode SCR (GCFSCR) is developed based on the floating-anode SCR. The anode or cathode will be floated during IC normal operation and it leads the GCFSCR to avoid turn-on accidentally. Hence, the holding voltage will raise and the latchup immunity be improved. The RC circuit is similar to a low-pass or high-pass filter, it can be used to differentiate the frequency response of the ESD or latchup noise.
40
Huang, Yeh-Jen y 黃曄仁. "HIGH-VOLTAGE ESD PROTECTION DEVICES DESIGN IN BCD PROCESS". Thesis, 2007. http://ndltd.ncl.edu.tw/handle/up2z2g.
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碩士國立交通大學
電機學院微電子奈米科技產業專班
96
The high-voltage (HV) ESD (Electrostatic Discharge, ESD) protection devices including the LDMOS power transistor, MOSFET, SCR (Silicon Controlled Rectifier), BJT (Bipolar Junction Transistor), diode and FOD (Field Oxide Device). The LDMOS in BCD (Bipolar CMOS DMOS) process can be the output current driver and ESD protection device, simultaneously. Therefore, it is applied in the fields of LCD driver, power management IC and motor electronics, etc. The MOSFET, SCR, BJT, diode and FOD are for the ESD protection device only. The SCR is a current-triggered device and it suffers the high trigger voltage and low holding voltage issues in HV ESD protection. It is necessary to add the trigger circuit and modify the layout parameter to reduce the trigger voltage and increase the holding voltage to protect the internal circuits and avoid the latchup effect. The various trigger methods to reduce the trigger voltage will be introduced first. The methods are parasitic initial-on PMOS-triggered device, native-NMOS-triggered SCR, dual-direction SCR trigger circuit, gate-couple, substrate trigger, dummy-gate structure and self-substrate-trigger. In addition, the application fields and turn-on resistance of smart power integrated circuit technology will be also introduced to discuss the reason of the VMOS, UMOS and LDMOS can be the output current driver. Then, to investigate the turn-on mechanism and the double-snapback characteristic of the LD-NMOS. The first research of this thesis is to discuss the ESD performance of HV LD-NMOS, HV LD-PMOS, HV NFOD, HV dual-direction SCR and HV NSCR by layout modification in 0.25�慆 18V BCD process. In TLP (Transmission Line Pulse) measurement, the ESD performance of LD-NMOS, NFOD and NSCR can be improved by increasing the N+ edge to contact spacing of the drain side due to the current path change. Unfortunately, the It2 (Secondary Breakdown Current) value can be improved a little by larger device total width of LD-PMOS. By layout modification, the holding voltage of dual-direction SCR can be controlled to over the operation voltage. But, the holding voltage of dual-direction SCR measured by 370A is different from the data measured by the TLP system is found. The second research of this thesis is to discuss the ESD performance of the small and large LD-NMOS devices with the PSB (P type Sub Body) layer. Due to the failure mechanism of the LD-NMOS is due to the snapback characteristic. The PSB layer is added to reduce the base resistance of the parasitic BJT and increase the trigger voltage of the LD-NMOS. Once the β gain decreased, the turn-on uniformity can be improved. The holding and trigger voltage can be both increased by the PSB layer in small LD-NMOS device; The It2 value can be increased by the PSB layer in large LD-NMOS device substantially.
41
Lin, Chun-Ting y 林俊廷. "A Design and Implementation for the USB2.0 ESD Protection". Thesis, 2011. http://ndltd.ncl.edu.tw/handle/60853189604245957592.
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碩士聖約翰科技大學
電機工程系碩士在職專班
99
In this thesis, we propose a design and implementation for the USB2.0 Electro-Static Discharge protection, abbreviated as DIUEP. There are some special features in the proposed DIUEP a.) power trace protection b.) signal trace protection c.) GND protection as well as the integration protection. Numerous test have been made and the results show that the improvements are around 40.10％ for the ESD test, 38.74％ for the USB signal trace D+ test, 41.15％ for the USB signal trace D- test, and 39.49％ for the GND test.
42
Chaung, Chien-Hui y 莊健暉. "ESD Protection Design for Mixed-Voltage I/O Circuits". Thesis, 2001. http://ndltd.ncl.edu.tw/handle/52219117072347606058.
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碩士國立交通大學
電子工程系
89
ABSTRACT To improve ESD robustness of the stacked-NMOS device in the mixed-voltage I/O circuit, there are two new designs proposed in this thesis. In the first part, a substrate-triggering technique has been used to improve the protection efficiency of the stacked-NMOS device in the mixed-voltage I/O circuit. From the experimental measurement results, the second breakdown current (It2) of the substrate-triggered stacked-NMOS can be effectively increased when the substrate current is increased. The substrate-triggering technique can further lower the trigger voltage of the stacked-NMOS device to ensure effective protection for the mixed-voltage I/O circuit. The on-chip ESD protection circuit designed with the substrate-triggering technique for 2.5V/3.3V tolerant mixed-voltage IC has been fabricated and verified in a 0.25-µm salicide CMOS process. Experimental results have shown that the ESD robustness of the mixed-voltage I/O circuit can be improved 160% by this substrate-triggering design. In the second part, a new ESD protection circuit, by using the stacked-NMOS triggered silicon controlled rectifier (SNTSCR) as the ESD clamp device, is designed to protect the mixed-voltage I/O buffer of CMOS IC’s. Without using the thick gate oxide, the SNTSCR has a lower trigger voltage and a low holding voltage to effectively protect the mixed-voltage I/O circuits with an improved ESD level. The proposed ESD protection circuit has been verified for 3.3V/5V tolerant mixed-voltage IC in a 0.35-µm CMOS process. Experimental results have proven that the HBM ESD level of the mixed-voltage I/O buffer can be successfully increased from the original ~2kV to become 8kV by using this new ESD protection circuit. The research results of this thesis have been applied 3 U.S. patents, and a paper has been accepted by the 2001 EOS/ESD Symposium.
43
Huang, Chia-Shih y 黃佳世. "ESD Protection of Capacitive Touch Panel for Tablet PC". Thesis, 2011. http://ndltd.ncl.edu.tw/handle/42643161326632465853.
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碩士國立雲林科技大學
電機工程系碩士班
99
The age of semiconductor nano-meter process is coming, the electronic components are becoming smaller and smaller. The consumer electronic products trend emphasizes light-weight and small-size. However, the problem of electromagnetic susceptibility has become more serious. Generally speaking, the products should not only obtain electromagnetic compatibility certification, but also comply with various susceptibility tests. The electromagnetic discharge test are law-regulation at European Union area and are requested by Japan, Taiwan, USA law。 Based on small size characteristic, the handhold products unexpected shutdown resulted from poor ESD protection design frequently. In this thesis, the circuit of capacitance- type touch panel used on tablet PC is the studying case to analyze small size product ESD issues. Followed by IEC 61000-4-2, we analyses the coupling paths of control signal to explore the effects of several solutions including Transient Voltage Suppression, Multilayer Varistor and mechanic modification.
44
葉宗立. "A MOS transistor with islanded drain for ESD protection". Thesis, 2001. http://ndltd.ncl.edu.tw/handle/30659850913352586418.
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碩士國立清華大學
電子工程研究所
89
In order to ensure IC products can go to the market smoothly and on time, function faultless and reliability are very important. But as we know, the key point is if they can pass ESD testing or not. Although some advanced processes help prompting IC performance with processes scaling down, it pays the expense of reducing ESD performance also. How to invent novel devices or circuits to provide a whole chip ESD protection in deep sub-micron technology is the main point in this thesis. In this thesis, we propose the novel islanded drain NMOS transistor for ESD protection and I/O pad. Without any additional process steps and mask numbers, the novel structure utilizes islands to change current path in NMOS drain diffusion region to increase drain ballast resistance in salicide process. So it can promote GGNMOS transistor turn on more uniformly. In addition to increasing ballast resistance, the island structure also increases GIDL current and the area of impact ionization current. ESD performance of the novel structure indeed apparently be improved under such a lot of effects. Moreover, the novel islanded drain structure also can substantially reduce layout area to achieve ESD testing requirement. So the value of drain series resistance and capacitance apparently be decreased. The characteristic will be helpful in high frequency application. This thesis also discusses the influence of GIDL in ESD protection. In aspect of simulation and experiment, it proves GIDL current indeed improving ESD protection ability of devices.
45
Chiu, Yan-Lian y 邱彥璉. "On-Chip ESD Protection Design for Output Driver Applications". Thesis, 2016. http://ndltd.ncl.edu.tw/handle/71703819228828214352.
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碩士國立臺灣師範大學
電機工程學系
104
With the continuous evolution of semiconductor integrated circuits (ICs) process, electrostatic discharge (ESD) events are likely to cause internal electronic components of the wafer suffered irreversible damage. All microelectronic products must meet the reliability specifications. Therefore, ESD must be taken into consideration. In the application of integrated circuit, several novel ESD protection devices are designed in this work. By designing the structure, this work has been fabricated in 0.18-μm 1.8V/3.3V CMOS process. In the experimental results, this design can achieve large swing tolerance and endure 2kV human-body-model (HBM) test. In order to verify the protection ability of ESD protection device on the circuits, a novel design of stacked-device output driver with embedded silicon-controlled rectifier (SCR) is proposed to improve the ESD robustness. This work has been fabricated in 0.18-um 1.8V/3.3V CMOS process. Besides, the transient behaviors of the proposed design during normal operation are not degraded. Therefore, the proposed design can be used to improve the ESD robustness of stacked-device output driver. Keywords: electrostatic discharge (ESD), output driver, silicon-controlled rectifier (SCR).
46
Lin, Meng-Ting y 林孟霆. "On-Chip ESD Protection Design for 24-GHz LNA". Thesis, 2017. http://ndltd.ncl.edu.tw/handle/6m7439.
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Chandrasekhar, Vinay. "Analysis and design of CMOS RF LNAs with ESD protection". Thesis, 2002. http://hdl.handle.net/1957/32159.
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An analysis that accounts for the effect of standard electrostatic discharge
(ESD) structures on critical LNA specifications of noise figure, input matching and
gain is presented. It is shown that the ESD structures degrade LNA performance
particularly for higher frequency applications. Two LNAs, one with ESD protection
and one without, which operate at 2.4 GHz have been fabricated in a 0.l5��m CMOS
process. The LNAs feature one of the best reported performances for CMOS LNAs
to date. The LNA with ESD protection achieves a gain of 12dB, a NF of 2.77dB
and an IIP3 of 2.4dBm with a power consumption of 4.65mW. The LNA without
ESD protection achieves a gain of 14dB, a NF of 2.36dB and an 11P3 of -2.2dBm
with a power consumption of 4.65mW.Graduation date: 2002
48
Jan, Yi-Lun y 詹奕倫. "Investigation of ESD Protection Devices in High-speed Digital System". Thesis, 2005. http://ndltd.ncl.edu.tw/handle/87315823281225181571.
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碩士國立中山大學
通訊工程研究所
93
In the trends of high clock rate, lower voltage, small volume, and portable requirement for present electric products, the noise immunity of high speed digital circuit becomes a critical factor for system designer. ESD problem becomes more and more important for electric products because of the triboelectricity caused by human body and synthetic material. It’s an important issue for designer to understand the ESD phenomena in grounding and floating system accurately. In this thesis, a reliable setup for the ESD measurement is proposed both in grounding and floating systems. ESD behavior and protection devices are studied in detail and a corresponding SPICE model is built up for simulation validation.
49
Jeff, Liao y 廖健富. "ESD Protection Circuit Design for Power Pins in Integrated Circuits". Thesis, 2005. http://ndltd.ncl.edu.tw/handle/55907770429366446991.
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碩士大葉大學
電機工程學系碩士班
93
In order to protect IC from the damage from ESD during the producing of IC, there are special circuits which can prevent ESD damage in the IC. This ESD protection circuits provide anther pathway to relief ESD electric current. Therefore, ESD electric current will not enter IC and no damage will be done. In this paper, we will present ESD protection circuits. First, there kinds of ESD models and motheds of ESD testing are mentioned. Then, we introduce ESD protection circuits. Last and the most important, we mimic and analize the VCC of RC with HSPICE.
50
Chen, Szu Han y 陳思瀚. "ESD Protection Circuit for High Gain Low Noise Amplifier Applications". Thesis, 2010. http://ndltd.ncl.edu.tw/handle/24359832594332861870.
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碩士長庚大學
電子工程學系
98
The major cause of most damaged devices or systems is electrostatic discharge(ESD). This damage will impact the characteristics of IC circuits. The device reliability is one of the most important key point when we design the IC circuit. We expect to design ESD protection circuit to protect low noise amplifier circuit of RF front-end receiver. The ESD protection circuit of this thesis is designed with four serial diodes with discharging circuit and the low noise amplifier is designed with common source. In this thesis, low noise amplifier with ESD protection circuit has a gain of 21 dB and noise figure of 3.3 dB. Input and output return losses are -29 dB and -18 dB, respectively. Power consumption is 11.7 mW. The frequency and voltage of operation are 5GHz and 1 volt, respectively. All of the circuits are simulated by Agilent Advanced Design System (ADS) and fabricated with TSMC 0.18µm 1P6M CMOS process which supplied from CIC.