Artículos de revistas: "Protection ESD"

1

Mohan, N. y A. Kumar. "Modeling ESD protection". IEEE Potentials 24, n.º 1 (febrero de 2005): 21–24. http://dx.doi.org/10.1109/mp.2005.1405797.

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2

Lee, J. H., S. C. Huang, Y. H. Wu y K. H. Chen. "1 fF ESD protection device for gigahertz high-frequency output ESD protection". Electronics Letters 47, n.º 18 (2011): 1021. http://dx.doi.org/10.1049/el.2011.1904.

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3

Li, Cheng, Zijin Pan, Weiquan Hao, Xunyu Li, Runyu Miao y Albert Wang. "Graphene-Based ESD Protection for Future ICs". Nanomaterials 13, n.º 8 (20 de abril de 2023): 1426. http://dx.doi.org/10.3390/nano13081426.

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On-chip electrostatic discharge (ESD) protection is required for all integrated circuits (ICs). Conventional on-chip ESD protection relies on in-Si PN junction-based device structures for ESD. However, such in-Si PN-based ESD protection solutions pose significant challenges related to ESD protection design overhead, including parasitic capacitance, leakage current, and noises, as well as large chip area consumption and difficulty in IC layout floor planning. The design overhead effects of ESD protection devices are becoming unacceptable to modern ICs as IC technologies continuously advance, which is an emerging design-for-reliability challenge for advanced ICs. In this paper, we review the concept development of disruptive graphene-based on-chip ESD protection comprising a novel graphene nanoelectromechanical system (gNEMS) ESD switch and graphene ESD interconnects. This review discusses the simulation, design, and measurements of the gNEMS ESD protection structures and graphene ESD protection interconnects. The review aims to inspire non-traditional thinking for future on-chip ESD protection.

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4

Li, Hongyu, Victor Khilkevich, Tianqi Li, David Pommerenke, Seongtae Kwon y Wesley Hackenberger. "Nonlinear capacitors for ESD protection". IEEE Electromagnetic Compatibility Magazine 1, n.º 4 (2012): 38–46. http://dx.doi.org/10.1109/memc.2012.6397056.

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5

Lin, Lin, Lijie Zhang, Xin Wang, Jian Liu, Hui Zhao, He Tang, Qiang Fang et al. "Novel Nanophase-Switching ESD Protection". IEEE Electron Device Letters 32, n.º 3 (marzo de 2011): 378–80. http://dx.doi.org/10.1109/led.2010.2099100.

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6

Chen, Shen Li, Min Hua Lee y Tzung Shian Wu. "Source-End Layout Influences on MOSFET ESD Protection Devices in a 0.35um 5V Process". Advanced Materials Research 694-697 (mayo de 2013): 1454–58. http://dx.doi.org/10.4028/www.scientific.net/amr.694-697.1454.

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An nMOS transistor in input/output pad as the ESD protection element is usually in the form of multi-finger layout. This paper will show simple but effective ways to improve an nMOSFET’s ESD robustness or LU immunity for use in I/O pads, i.e., the source-end layout influences on the protection components in ESD/LU capabilities of the input/output pads will be investigated. In other words, they are used to increase the effective ESD or LU capability of the ESD protection elements. Here, the different source-end layout types will be carried out the important snapback parameters. We focus on exploring the secondary breakdown current (It2) and holding voltage (Vh) for the ESD discharge capability and the latch-up immunity, hopefully, it does effectively enhance ESD/LU robustness.

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7

Soldner, W., M. Streibl, U. Hodel, M. Tiebout, H. Gossner, D. Schmitt-Landsiedel, J. H. Chun, C. Ito y R. W. Dutton. "RF ESD protection strategies: Codesign vs. low-C protection". Microelectronics Reliability 47, n.º 7 (julio de 2007): 1008–15. http://dx.doi.org/10.1016/j.microrel.2006.11.007.

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8

Pan, Zijin, Xunyu Li, Weiquan Hao, Runyu Miao y Albert Wang. "On-chip ESD Protection Design Methodologies by CAD Simulation". ACM Transactions on Design Automation of Electronic Systems 29, n.º 1 (15 de noviembre de 2023): 1–41. http://dx.doi.org/10.1145/3593808.

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Electrostatic discharge (ESD) can cause malfunction or failure of integrated circuits (ICs) . On-chip ESD protection design is a major IC design-for-reliability (DfR) challenge, particularly for complex chips made in advanced technology nodes. Traditional trial-and-error approaches become unacceptable to practical ESD protection designs for advanced ICs. Full-chip ESD protection circuit design optimization, prediction, and verification become essential to advanced chip designs, which highly depends on CAD algorithm and simulation that has been a constant research topic for decades. This paper reviews recent advances in CAD-enabled on-chip ESD protection circuit simulation design technologies and ESD-IC co-design methodologies. Key challenges of ESD CAD design practices are outlined. Practical ESD protection simulation design examples are discussed.

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9

Kwon, Sang-Wook, Seung-Gu Jeong, Jeong-Min Lee y Yong-Seo Koo. "Design of Destruction Protection and Sustainability Low-Dropout Regulator Using an Electrostatic Discharge Protection Circuit". Sustainability 15, n.º 13 (26 de junio de 2023): 10126. http://dx.doi.org/10.3390/su151310126.

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In terms of sustainable power semiconductors, the embedding of an electrostatic discharge (ESD) protection circuit in an integrated circuit (IC) is an important aspect. In order for the semiconductor circuit to operate continuously or stably, a sufficient protection circuit against external surges must be configured. The purpose of this thesis is not only to effectively operate the low-dropout (LDO) regulator according to the load current, but to also secure high reliability against ESD situations by embedding an ESD protection circuit at the IC level. Moreover, the existence and nonexistence of an ESD protection circuit at the IC level is directly related to reliability. The proposed LDO regulator has high reliability against ESD situations using an embedded silicon controlled rectifier (SCR)-based ESD protection circuit in the I/O clamp and power clamp. The results revealed that the LDO regulator can not only effectively control the output voltage according to the load current, but it can also stably maintain the output voltage against the ESD surge. Moreover, the proposed LDO regulator with an embedded ESD protection circuit implemented in a 0.13 μm BCD process maintained an undershoot voltage of 21 mV and overshoot voltage of 19 mV for a load current of 300 mA.

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10

Chang, Chun-Rong, Zih-Jyun Dai y Chun-Yu Lin. "π-Shape ESD Protection Design for Multi-Gbps High-Speed Circuits in CMOS Technology". Materials 16, n.º 7 (23 de marzo de 2023): 2562. http://dx.doi.org/10.3390/ma16072562.

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CMOS integrated circuits are vulnerable to electrostatic discharge (ESD); therefore, ESD protection circuits are needed. On-chip ESD protection is important for both component-level and system-level ESD protection. In this work, on-chip ESD protection circuits for multi-Gbps high-speed applications are studied. π-shaped ESD protection circuit structures realized by staked diodes with an embedded silicon-controlled rectifier (SCR) and resistor-triggered SCR are proposed. These test circuits are fabricated in CMOS technology, and the proposed designs have been proven to have better ESD robustness and performance in high-speed applications.

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11

Chen, G., H. Feng, H. Xie, R. Zhan, Q. Wu, X. Guan, A. Wang et al. "Characterizing Diodes for RF ESD Protection". IEEE Electron Device Letters 25, n.º 5 (mayo de 2004): 323–25. http://dx.doi.org/10.1109/led.2004.826531.

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12

Voldman, S., R. Schulz, J. Howard, V. Gross, S. Wu, A. Yapsir, D. Sadana et al. "CMOS-on-SOI ESD protection networks". Journal of Electrostatics 42, n.º 4 (enero de 1998): 333–50. http://dx.doi.org/10.1016/s0304-3886(97)00156-3.

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13

Hyvonen, Sami, Sopan Joshi y Elyse Rosenbaum. "Comprehensive ESD protection for RF inputs". Microelectronics Reliability 45, n.º 2 (febrero de 2005): 245–54. http://dx.doi.org/10.1016/j.microrel.2004.05.012.

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14

Vassilev, Vesselin. "Advances in ESD protection for ICs". Microelectronics Reliability 53, n.º 2 (febrero de 2013): 183. http://dx.doi.org/10.1016/j.microrel.2013.01.002.

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15

Chen, Shen Li y Der Ann Fran. "Improvement on ESD Protection of Output Driver in DC Brushless Fan ICs by the FOD Protection Block". Advanced Materials Research 850-851 (diciembre de 2013): 449–53. http://dx.doi.org/10.4028/www.scientific.net/amr.850-851.449.

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In this paper, ESD improvements of an output driver that driving a large current in DC brushless fan ICs under HBM ESD stress is investigated. In order to improve ESD robustness, some protection blocks will be designed and implemented by the layout parameters and structures tuning. From the preliminary ESD testing result, it was found that the positive Pad-to-VSS (PS) zapping mode of the original DUT is weakest for the output driver of DC brushless fan ICs during an HBM zapping. After a systematic improvement, it is found that the FOD structure of adding protection circuits can effectively protect the whole-chip ESD damage, as compared with the original DUT; the values of ESD failure threshold (VESD) are increased > 57%, which allows output driver devices more robust in the ESD immunity.

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16

Chen, Qi, Rui Ma, Wei Zhang, Fei Lu, Chenkun Wang, Owen Liang, Feilong Zhang et al. "Systematic Characterization of Graphene ESD Interconnects for On-Chip ESD Protection". IEEE Transactions on Electron Devices 63, n.º 8 (agosto de 2016): 3205–12. http://dx.doi.org/10.1109/ted.2016.2582140.

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17

Kannan, Sukeshwar, Bruce Kim, Friedrich Taenzler, Richard Antley y Ken Moushegian. "Novel ESD Protection Scheme for Testing High Voltage LDMOS". International Symposium on Microelectronics 2012, n.º 1 (1 de enero de 2012): 000683–86. http://dx.doi.org/10.4071/isom-2012-wa52.

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This paper presents a novel protection circuit for Electrostatic Discharge (ESD) for testing high-voltage devices using Silicon Controlled Rectifiers (SCRs). ESD related issues lead to test equipment damage, hence efficient protection techniques play a very critical role in testing high voltage devices. High-Voltage Laterally-Diffused MOSs (HV-LDMOSs) is extensively used for high voltage applications due to its advantages over other metal oxide semiconductor structures. In high voltage devices ESD protection is generally provided between the drain and source terminals. We have implemented SCRs as the ESD protection circuit for the drain connection in HV-LDMOSs. We have developed ESD stress models using conventional techniques such as human body, machine and charged device models for the high-voltage devices and implement SCRs as protection circuit in the high-voltage DIBs. Simulation has been completed to obtain the ESD stress data of the device. This ESD stress model data can be used to automate our testing process by incorporating the novel ESD protection scheme on a newly developed test software tool.

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18

Chen, Shen Li y Guan Jhong Chen. "Evaluating nMOSFET ESD Protection Designs: An Overview". Applied Mechanics and Materials 268-270 (diciembre de 2012): 1357–60. http://dx.doi.org/10.4028/www.scientific.net/amm.268-270.1357.

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This work is referring to the various singer-finger/ multi-finger nMOSFET structures stressed by electrostatic discharge (ESD) zapping, and to evaluate the high current distributions in different ESD protection schemes. Eventually, these efforts can be used in many integrated circuits implementations. By using the TCAD and HSpice, due to the internal parasitic resistance differences in each one finger, which will obviously result in the non-uniform turned on phenomena. Meanwhile, with different interior parasitic capacitor in each nMOSFET structure, which will be inflected the device high-current-injection behavior, i.e., ESD immunity level.

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19

Wang, Jing Min y Chun Ting Lin. "Employing Ceramic Products to Design an Electrostatic Discharge Protection for High-Speed Signal Lines". Applied Mechanics and Materials 389 (agosto de 2013): 205–10. http://dx.doi.org/10.4028/www.scientific.net/amm.389.205.

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With the advance of microelectronics technologies and integrated circuits (ICs) processes, the electrostatic discharge (ESD) has become one of the most important reliability issues in IC products. But treating the ESD-related problems is a real challenge. The paper focuses on the influence of the using of Universal Serial Bus (USB) in plugging and/or unplugging impact arisen from ESD and also proposes an ESD protection design to improve the ESD robustness. This work utilizes off-chip protection along with the commercial ceramic products to achieve effective ESD protection. The impact of the ESD stress applied at the connector pins of USB is evaluated. The protection design for the high-speed signal lines is easily to implement and achieves the following attractive features: (1) Power trace protection, (2) Signals traces protection, (3) GND protection, and (4) Shield protection. Numerous tests have been made to demonstrate the effectiveness of the work.

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20

Lee, Jian-Hsing, Shao-Chang Huang, Hung-Der Su y Ke-Horng Chen. "Semiself-Protection Scheme for Gigahertz High-Frequency Output ESD Protection". IEEE Transactions on Electron Devices 58, n.º 7 (julio de 2011): 1914–21. http://dx.doi.org/10.1109/ted.2011.2143717.

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21

Yao, Bin, Yijun Shi, Hongyue Wang, Xinbin Xu, Yiqiang Chen, Zhiyuan He, Qingzhong Xiao et al. "A Novel Bidirectional AlGaN/GaN ESD Protection Diode". Micromachines 13, n.º 1 (15 de enero de 2022): 135. http://dx.doi.org/10.3390/mi13010135.

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Despite the superior working properties, GaN-based HEMTs and systems are still confronted with the threat of a transient ESD event, especially for the vulnerable gate structure of the p-GaN or MOS HEMTs. Therefore, there is still an urgent need for a bidirectional ESD protection diode to improve the ESD robustness of a GaN power system. In this study, an AlGaN/GaN ESD protection diode with bidirectional clamp capability was proposed and investigated. Through the combination of two floating gate electrodes and two pF-grade capacitors connected in parallel between anode or cathode electrodes and the adjacent floating gate electrodes (CGA (CGC)), the proposed diode could be triggered by a required voltage and possesses a high secondary breakdown current (IS) in both forward and reverse transient ESD events. Based on the experimental verification, it was found that the bidirectional triggering voltages (Vtrig) and IS of the proposed diode were strongly related to CGA (CGC). With CGA (CGC) increasing from 5 pF to 25 pF, Vtrig and IS decreased from ~18 V to ~7 V and from ~7 A to ~3 A, respectively. The diode’s high performance demonstrated a good reference for the ESD design of a GaN power system.

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22

Liu, Shuyang. "Research on Design Method of Low Voltage ESD Protection for Chips based on CMOS Technology". Frontiers in Science and Engineering 3, n.º 12 (22 de diciembre de 2023): 29–40. http://dx.doi.org/10.54691/52vq1z60.

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As integrated circuit technology continuously evolves towards nanometre scales, the susceptibility of chips to Electrostatic Discharge (ESD) under low voltage conditions has significantly increased, posing greater challenges for ESD protection design. Traditionally, ESD protection strategies have centred on high-voltage applications, employing complex and cumbersome circuits and components to enhance tolerance. However, these methods often underperform in low-voltage CMOS processes due to excessive leakage currents, increased chip area, and an inability to meet the requirements of low power consumption and high integration of devices. This study introduces a novel universal framework for low-voltage ESD protection design methods applicable to various CMOS technology standards. The framework not only compares the merits and demerits of existing mainstream ESD protection devices, ESD testing methodologies, and ESD protection networks, but also introduces an innovative analytical paradigm to holistically consider the interplay among these three facets within low-voltage ESD protection design, thereby offering fresh insights for theoretical and practical research. This universal architecture, while ensuring compatibility, also demonstrates exceptional efficiency, which represents it can be easily and swiftly applicable to different CMOS technology standards.

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23

Song, Bo Bae y Yong Seo Koo. "Highly Robust AHHVSCR-Based ESD Protection Circuit". ETRI Journal 38, n.º 2 (1 de abril de 2016): 272–79. http://dx.doi.org/10.4218/etrij.16.2515.0037.

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24

Nikolaidis, T. y C. Papadas. "SCR ESD protection with reduced trigger voltage". Electronics Letters 39, n.º 7 (2003): 608. http://dx.doi.org/10.1049/el:20030405.

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25

Galal, S. y B. Razavi. "Broadband esd protection circuits in cmos technology". IEEE Journal of Solid-State Circuits 38, n.º 12 (diciembre de 2003): 2334–40. http://dx.doi.org/10.1109/jssc.2003.818568.

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26

Wang, Li, Xin Wang, Zitao Shi, Rui Ma, Jian Liu, Zhongyu Dong, Chen Zhang et al. "Dual-Direction Nanocrossbar Array ESD Protection Structures". IEEE Electron Device Letters 34, n.º 1 (enero de 2013): 111–13. http://dx.doi.org/10.1109/led.2012.2222337.

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27

Johnsson, David, Dionyz Pogany, Joost Willemen, Erich Gornik y Matthias Stecher. "Avalanche Breakdown Delay in ESD Protection Diodes". IEEE Transactions on Electron Devices 57, n.º 10 (octubre de 2010): 2470–76. http://dx.doi.org/10.1109/ted.2010.2058790.

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28

Stockinger, Michael, James W. Miller, Michael G. Khazhinsky, Cynthia A. Torres, James C. Weldon, Bryan D. Preble, Martin J. Bayer, Matthew Akers y Vishnu G. Kamat. "Advanced rail clamp networks for ESD protection". Microelectronics Reliability 45, n.º 2 (febrero de 2005): 211–22. http://dx.doi.org/10.1016/j.microrel.2004.05.009.

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29

Keppens, Bart, Markus P. J. Mergens, Cong Son Trinh, Christian C. Russ, Benjamin Van Camp y Koen G. Verhaege. "ESD protection solutions for high voltage technologies". Microelectronics Reliability 46, n.º 5-6 (mayo de 2006): 677–88. http://dx.doi.org/10.1016/j.microrel.2005.10.009.

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30

Shigyo, N., H. Kawashima y S. Yasuda. "ESD protection device design using statistical methods". Solid-State Electronics 46, n.º 12 (diciembre de 2002): 2117–22. http://dx.doi.org/10.1016/s0038-1101(02)00239-3.

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31

Elmer, György. "Possible application of memristors in ESD protection". Journal of Electrostatics 71, n.º 3 (junio de 2013): 373–76. http://dx.doi.org/10.1016/j.elstat.2012.11.008.

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32

Fried, Rafael, Yaron Blecher y Shimon Friedman. "Structures for ESD protection in CMOS processes". Microelectronics Reliability 37, n.º 7 (julio de 1997): 1111–20. http://dx.doi.org/10.1016/s0026-2714(96)00260-0.

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33

Dong, S., M. Li, W. Guo, Y. Han, D. Huang y B. Song. "Complementation SCR for RF IC ESD protection". Electronics Letters 46, n.º 3 (2010): 210. http://dx.doi.org/10.1049/el.2010.2567.

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34

Wang, A. Z. H., H. Feng, R. Zhan, H. Xie, G. Chen, Q. Wu, X. Guan, Z. Wang y C. Zhang. "A Review on RF ESD Protection Design". IEEE Transactions on Electron Devices 52, n.º 7 (julio de 2005): 1304–11. http://dx.doi.org/10.1109/ted.2005.850652.

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35

Duvvury, Charvaka y Robert Rountree. "A synthesis of ESD input protection scheme". Journal of Electrostatics 29, n.º 1 (diciembre de 1992): 1–19. http://dx.doi.org/10.1016/0304-3886(92)90003-c.

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36

Croft, Gregg D. "On chip ESD protection using SCR pairs". Journal of Electrostatics 31, n.º 2-3 (diciembre de 1993): 177–97. http://dx.doi.org/10.1016/0304-3886(93)90008-u.

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37

Chen, Shen Li y Chien Chin Tseng. "The SCR Protection Circuit Evaluation in HV DEMOS Devices". Applied Mechanics and Materials 256-259 (diciembre de 2012): 2923–26. http://dx.doi.org/10.4028/www.scientific.net/amm.256-259.2923.

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The electrostatic discharge (ESD) failure of power drain-extended MOS (DEMOS) devices, the protection circuit SCR, and a DEMOS with SCR protection circuit will be investigated in this paper. The ESD immunity of the DEMOS was very poor under the human-body model (HBM) testing. Here we discuss how to design an ESD good SCR device. Eventually, the ESD immunity of DEMOS test sample with an SCR circuit can significantly improve device ESD performance.

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38

Chen, Shen Li y Chien Chin Tseng. "The SCR Protection Circuit Evaluation in HV DEMOS Devices". Advanced Materials Research 614-615 (diciembre de 2012): 1438–41. http://dx.doi.org/10.4028/www.scientific.net/amr.614-615.1438.

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The electrostatic discharge (ESD) failure of power drain-extended MOS (DEMOS) devices, the protection circuit SCR, and a DEMOS with SCR protection circuit will be investigated in this paper. The ESD immunity of the DEMOS was very poor under the human-body model (HBM) testing. Here we discuss how to design an ESD good SCR device. Eventually, the ESD immunity of DEMOS test sample with an SCR circuit can significantly improve device ESD performance.

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39

Wang, Xin, He Tang, Lin Lin, Jian Liu, Qiang Fang, Hui Zhao, Albert Wang et al. "Co-design of ESD protection and UWB RF front-end ICs". Science China Information Sciences 54, n.º 10 (15 de septiembre de 2011): 2209–20. http://dx.doi.org/10.1007/s11432-011-4416-3.

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40

Lv, Zhixing, Nan Yan y Bingliang Bao. "Pin-pin ESD protection for electro-explosive device under severe human body ESD". Microelectronics Reliability 75 (agosto de 2017): 37–42. http://dx.doi.org/10.1016/j.microrel.2017.06.004.

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41

Son, Minoh y Changkun Park. "Cell-Based ESD Diodes with a Zigzag-Shaped Layout to Enhance the ESD Survival Level". Journal of Circuits, Systems and Computers 26, n.º 02 (3 de noviembre de 2016): 1750023. http://dx.doi.org/10.1142/s0218126617500232.

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In this study, we propose cell-based diodes which are laid out with a zigzag shape as electrostatic discharge (ESD) protection elements to enhance the ESD survival level of the diodes. Generally, diodes are regarded as simple ESD protection devices in integrated circuits. During ESD events, the P–N junction of the ESD diode acts as a thermal source. In this study, we investigate a distributed layout method which relies on a cell-based ESD diode to prevent an excessive increase in the temperature at the P–N junction. However, although the distributed layout enhances the ESD survival levels of the ESD diode, the required area increases compared that of a typical layout. Thus, we propose a zigzag layout technique for the cell-based diode to reduce the area and obtain a high ESD survival level. To verify the feasibility of the zigzag layout techniques for cell-based diodes, we designed ESD diodes using 110[Formula: see text]nm RF CMOS technology. The experimental results successfully demonstrate the feasibility of the proposed method.

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42

Yang, Jian Hong, Lin Jiao Zhang y Fei Hu Zhao. "The Characteristics of ESD Protection Device Based on Static Induction Thyristors". Applied Mechanics and Materials 303-306 (febrero de 2013): 1803–7. http://dx.doi.org/10.4028/www.scientific.net/amm.303-306.1803.

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A novel structure of ESD protection device based on the static induction thyristors (SITh) was in further investigation. Detailed analysis of the negative resistance characteristics of SITh was presented, especially its blocking and conducting states that satisfy the requirements in ESD events. The characteristics of SITh for ESD protection were obtained using the Time Domain Reflectometer (TDR) type of Transmission Line Pulse (TLP) testing system. The results illustrate that SITh for ESD protection has the following advantages: 1) It has a strong ESD stress handing capability (3.75 kV); 2) Its second breakdown current is large enough (2.5 A) to release great ESD current; 3) DC leakage current of SITh is very small (1 μA); 4) SITh can break through the limitations of transitional trigger voltages, whose trigger voltage is dynamically adjustable as well; 5) The ESD response time can be controlled through optimizing device structure of SITh.

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43

Chen, Shen Li y Wen Ming Lee. "Power MOSFET Devices and ESD Reliability Evaluations". Applied Mechanics and Materials 268-270 (diciembre de 2012): 1361–64. http://dx.doi.org/10.4028/www.scientific.net/amm.268-270.1361.

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The electrostatic discharge (ESD) reliabilities in different power MOSFETs will be investigated in this paper. From the experimental results, ESD zap pulses at the gate terminal will cause electrons or holes trap in the gate oxide and loss the Si-SiO2 interface integrity, especially for the 100V nDEMOS, 200V nDEMOS, and IRF640, in which they do not have any ESD protection strategy. Electrons or holes trapped in the gate SiO2 layer will be caused the transconductance (Gm) or threshold voltage (Vth) of a MOSFET increasing or reduction, and which is resulted from electron mobility degradation. The RFW2N06RLE and RLD03N06CLE power VDMOS ICs, which with different kinds of ESD protection circuit, are less influenced by ESD pulses experimentally.

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44

Shrier, Karen. "Polymer Based Interposer offering Si Matched CTE + ESD Protection". Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2013, DPC (1 de enero de 2013): 000674–90. http://dx.doi.org/10.4071/2013dpc-tp14.

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For 2.5 D package integration interposers based on silicon have widely been investigated. However, their high cost adder to the package is a major drawback. An alternative interposer based on polymer- nanoparticle compound material is introduced. It can be manufactured in large volume by low cost processes. Depending on polymer layer structure a CTE varying between 0 to 8 ppm/ °C can be adjusted. A polymer system which has a CTE close to Si of 2.6 ppm/ °C is used for a thermally matched interposer. The material is less fragile than silicon or glass. Copper vias through the polymer substrate have been manufactured with a diameter of 2 um by laser drill. The manufactured thickness of the interposer varies between 200 um and as low as 85 um. In addition, by choice of appropriate nano particles the interposer can act as overvoltage protection element where regions between wires become conductive under high voltage conditions. This enables an intrinsic ESD protection implemented into the interposer protecting the stacked dies against ESD discharges as high as 15 kV IEC.

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45

Zhu, Zhihua, Zhaonian Yang, Xiaomei Fan, Yingtao Zhang, Juin Jei Liou y Wenbing Fan. "Optimization of Tunnel Field-Effect Transistor-Based ESD Protection Network". Crystals 11, n.º 2 (28 de enero de 2021): 128. http://dx.doi.org/10.3390/cryst11020128.

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The tunnel field-effect transistor (TFET) is a potential candidate for replacing the reverse diode and providing a secondary path in a whole-chip electrostatic discharge (ESD) protection network. In this paper, the ESD characteristics of a traditional point TFET, a line TFET and a Ge-source TFET are investigated using technology computer-aided design (TCAD) simulations, and an improved TFET-based whole-chip ESD protection scheme is proposed. It is found that the Ge-source TFET has a lower trigger voltage and higher failure current compared to the traditional point and line TFETs. However, the Ge-source TFET-based secondary path in the whole-chip ESD protection network is more vulnerable compared to the primary path due to the low thermal instability. Simulation results show that choosing the proper germanium mole fraction in the source region can balance the discharge ability and thermal failure risk, consequently enhancing the whole-chip ESD robustness.

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Chen, Shen Li y Chi Ling Chu. "ESD Robustness Designs for the HV Power DEMOS". Applied Mechanics and Materials 271-272 (diciembre de 2012): 1286–90. http://dx.doi.org/10.4028/www.scientific.net/amm.271-272.1286.

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Two kinds of efficient electrostatic discharge (ESD) protection circuits in lateral drain extended MOSFETs (DEMOSFETs) will be designed and investigated in this paper. One kind of these test samples is fabricated with an SCR structure, which has the lowest turned-on resistance when it is triggered by a high voltage of ESD event. The SCR circuit is the most efficient of all protection devices in terms of ESD performance per unit area. Furthermore, the other type of these DUTs is an SCR with RC-triggered structure, which will have a small trigger voltage (Vt1) under ESD event, and then it obtains a good ESD immunity level.

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47

LI Qing-shuo, 李卿硕, 吴倩 WU Qian y 王莎 WANG Sha. "TFT-LCD Module ESD Failure Analysis and Protection Research". Chinese Journal of Liquid Crystals and Displays 28, n.º 5 (2013): 711–15. http://dx.doi.org/10.3788/yjyxs20132805.0711.

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48

Nahm, Eui-Seok y Ey Goo Kang. "Study on the Design of Power MOSFET with ESD Protection Circuits". Journal of the Korean Institute of Electrical and Electronic Material Engineers 28, n.º 9 (1 de septiembre de 2015): 555–60. http://dx.doi.org/10.4313/jkem.2015.28.9.555.

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49

Chen, Shen Li y Der Ann Fran. "Implementation of ESD Protection for Output Driver ICs with SCR Circuits Techniques". Applied Mechanics and Materials 464 (noviembre de 2013): 139–44. http://dx.doi.org/10.4028/www.scientific.net/amm.464.139.

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In this paper, an output driver which drove a large current in DC brushless fan ICs was taken for the HBM ESD stress. The protection circuits of this IC were also designed to improve ESD robustness by various layout parameters and structures. From the ESD testing results, it was found that the positive Pad-to-VSS (PS) zapping mode was weakest for the output driver of DC brushless fan ICs during ESD stress. Eventually, protection circuits with a complementary low-voltage-triggered SCR (LVTSCR) were used to protect the whole-chip ESD stress. After a systematic improvement, an SCR structure of adding protection circuits can effectively protect the whole-chip ESD reliability, as compared with the original DUT; the ESD failure threshold (VESD) of PS mode is increased 314% in a best structure when an LVTSCR with the drain-tap S space is 4μm.

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50

Lin, Chien-Chun y Chun-Yu Lin. "ESD Research of SCR Devices under Harsh Environments". Materials 16, n.º 18 (13 de septiembre de 2023): 6182. http://dx.doi.org/10.3390/ma16186182.

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In prior technology, system-level electrostatic discharge (ESD) tests under environment change conditions mainly focused on testing the effect of a high-temperature environment. i.e., the effect on internal circuits of heat generated outside. However, few studies have explored the effect of ambient relative humidity changes on integrated circuits (ICs). Therefore, this study will analyze the performance of various ESD protection components under high ambient temperature and high ambient relative humidity. The ESD protection devices are tested for the ESD robustness of the silicon-controlled rectifiers (SCR) under a harsh environment and the measurement results are discussed and verified in the CMOS process.

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