Bibliografías temáticas / Software acceleration

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Literatura académica sobre el tema "Software acceleration"

Autor: Grafiati
Publicado: 25 de mayo de 2024
Última modificación: 31 de julio de 2025

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Artículos de revistas sobre el tema "Software acceleration"

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Long, Gary. "Acceleration Characteristics of Starting Vehicles." Transportation Research Record: Journal of the Transportation Research Board 1737, no. 1 (2000): 58–70. http://dx.doi.org/10.3141/1737-08.

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Acceleration characteristics of starting vehicles are needed for many transportation analysis and design purposes involving driveways, turning bays, intersecting streets, traffic signals, railroad crossings, simulation software, and so forth. Constant acceleration is sometimes assumed, or AASHTO Green Book values based on piecewise-constant accelerations are sometimes adopted. However, continuing research has shown that linearly decreasing acceleration rates better represent both maximum vehicle acceleration capabilities and actual motorist behavior. It is not acceleration that usually is cons
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An, Xiao Xue, Xiao Dong Chai, Wen Fa Zhu, and Xiao Wei Xu. "Software Design of the Track State Inspection System Based on LabVIEW." Advanced Materials Research 546-547 (July 2012): 1323–28. http://dx.doi.org/10.4028/www.scientific.net/amr.546-547.1323.

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This paper describes the software of the track state inspection system based on LABVIEW, which includes serial communication, data extraction, strap-down algorithm, acceleration integral and saving the results. Serial communication module uses VISA to program in order to realize communication between the IMU (inertial measurement unit)and upper computer. According to the output data format, data extraction module separates the signal of three axes’ accelerations and angular-rates by Match Pattern Function. Strap-down algorithm and acceleration integral modules are programmed by Math Script. Th
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Boroushak, Neda, Hasan Khoshnoodi, and Mostafa Rostami. "Investigation of the Head’s Dynamic Response to Boxing Punch Using Computer Simulation." Montenegrin Journal of Sports Science and Medicine 10, no. 1 (2021): 31–35. http://dx.doi.org/10.26773/mjssm.210305.

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Head injuries are dangerous injuries that are common in combat sports. Nevertheless, the mechanisms of concussion in sport have are not precisely known. Thus, this study aimed to investigate the dynamic response of the head based on linear and rotational accelerations in boxing using computer simulation. The ADAMS software model was used to determine the linear and rotational acceleration of boxing’s straight punch. The peak linear acceleration, average linear acceleration, peak rotational acceleration, and average rotational acceleration resulted from the straight punch to head were obtained:
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Edwards, M. D., and J. Forrest. "Software acceleration using programmable hardware devices." IEE Proceedings - Computers and Digital Techniques 143, no. 1 (1996): 55. http://dx.doi.org/10.1049/ip-cdt:19960066.

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Chun F. Ong and M. N. Marsono. "Heterogeneous Hardware Architecture with Linear Algebra Acceleration." ELEKTRIKA- Journal of Electrical Engineering 24, no. 1 (2025): 53–56. https://doi.org/10.11113/elektrika.v24n1.633.

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Linear algebra is essential in machine learning for dealing with large datasets. Linear algebra acceleration is directly related to the hardware used. Many works have proposed linear algebra accelerator architectures with the goal of improving energy efficiency and speed. The characterization of trade-offs in balancing acceleration and programmability of software routines is still insufficiently explored, particularly for edge analytics. Therefore, this paper proposes a heterogeneous hardware architecture consisting of a RISC-V system-on-chip and a linear algebra accelerator. Tested on Efinix
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Manor, Erez, Avrech Ben-David, and Shlomo Greenberg. "CORDIC Hardware Acceleration Using DMA-Based ISA Extension." Journal of Low Power Electronics and Applications 12, no. 1 (2022): 4. http://dx.doi.org/10.3390/jlpea12010004.

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The use of RISC-based embedded processors aimed at low cost and low power is becoming an increasingly popular ecosystem for both hardware and software development. High-performance yet low-power embedded processors may be attained via the use of hardware acceleration and Instruction Set Architecture (ISA) extension. Recent publications of AI have demonstrated the use of Coordinate Rotation Digital Computer (CORDIC) as a dedicated low-power solution for solving nonlinear equations applied to Neural Networks (NN). This paper proposes ISA extension to support floating-point CORDIC, providing effi
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Chen, Andrew, Rohaan Gupta, Anton Borzenko, Kevin Wang, and Morteza Biglari-Abhari. "Accelerating SuperBE with Hardware/Software Co-Design." Journal of Imaging 4, no. 10 (2018): 122. http://dx.doi.org/10.3390/jimaging4100122.

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Background Estimation is a common computer vision task, used for segmenting moving objects in video streams. This can be useful as a pre-processing step, isolating regions of interest for more complicated algorithms performing detection, recognition, and identification tasks, in order to reduce overall computation time. This is especially important in the context of embedded systems like smart cameras, which may need to process images with constrained computational resources. This work focuses on accelerating SuperBE, a superpixel-based background estimation algorithm that was designed for sim
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Edwards, M. D., J. Forrest, and A. E. Whelan. "Acceleration of software algorithms using hardware/software co-design techniques." Journal of Systems Architecture 42, no. 9-10 (1997): 697–707. http://dx.doi.org/10.1016/s1383-7621(96)00071-9.

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Gao, Yifan. "Research on Hardware Acceleration Optimisation Strategies for Deep Learning in Computer Vision." Highlights in Science, Engineering and Technology 111 (August 19, 2024): 554–59. http://dx.doi.org/10.54097/cnqx4b90.

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As deep neural network (DNN) models get larger and more complicated, the importance of hardware acceleration becomes more and more apparent. This paper discusses various hardware acceleration strategies for deep learning, especially in the area of computer vision. It explores the use of GPUs, FPGAs, and ASICs, detailing their respective strengths and weaknesses in accelerating DNNs. This paper argues that the future of DNN hardware acceleration lies in hybrid approaches that combine the advantages of different architectures. Software advances such as improved compilers and synthesis tools will
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Tang, Wenkai, and Peiyong Zhang. "GPGCN: A General-Purpose Graph Convolution Neural Network Accelerator Based on RISC-V ISA Extension." Electronics 11, no. 22 (2022): 3833. http://dx.doi.org/10.3390/electronics11223833.

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In the past two years, various graph convolution neural networks (GCNs) accelerators have emerged, each with their own characteristics, but their common disadvantage is that the hardware architecture is not programmable and it is optimized for a specific network and dataset. They may not support acceleration for different GCNs and may not achieve optimal hardware resource utilization for datasets of different sizes. Therefore, given the above shortcomings, and according to the development trend of traditional neural network accelerators, this paper proposes and implements GPGCN: a general-purp
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Tesis sobre el tema "Software acceleration"

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Borgström, Fredrik. "Acceleration of FreeRTOS withSierra RTOS accelerator : Implementation of a FreeRTOS software layer onSierra RTOS accelerator." Thesis, KTH, Data- och elektroteknik, 2016. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-188518.

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Today, the effect of the most common ways to improve the performance of embedded systems and real-time operating systems is stagnating. Therefore it is interesting to examine new ways to push the performance boundaries of embedded systems and real-time operating systems even further. It has previously been demonstrated that the hardware-based real-time operating system, Sierra, has better performance than the software-based real-time operating system, FreeRTOS. These real-time operating systems have also been shown to be similar in many aspects, which mean that it is possible for Sierra to acc
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Kulkarni, Pallavi Anil. "Hardware acceleration of software library string functions." Ann Arbor, Mich. : ProQuest, 2007. http://gateway.proquest.com/openurl?url_ver=Z39.88-2004&rft_val_fmt=info:ofi/fmt:kev:mtx:dissertation&res_dat=xri:pqdiss&rft_dat=xri:pqdiss:1447245.

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Thesis (M.S. in Computer Engineering)--S.M.U., 2007.<br>Title from PDF title page (viewed Nov. 19, 2009). Source: Masters Abstracts International, Volume: 46-03, page: 1577. Adviser: Mitch Thornton. Includes bibliographical references.
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Blumer, Aric David. "Register Transfer Level Simulation Acceleration via Hardware/Software Process Migration." Diss., Virginia Tech, 2007. http://hdl.handle.net/10919/29380.

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The run-time reconfiguration of Field Programmable Gate Arrays (FPGAs) opens new avenues to hardware reuse. Through the use of process migration between hardware and software, an FPGA provides a parallel execution cache. Busy processes can be migrated into hardware-based, parallel processors, and idle processes can be migrated out increasing the utilization of the hardware. The application of hardware/software process migration to the acceleration of Register Transfer Level (RTL) circuit simulation is developed and analyzed. RTL code can exhibit a form of locality of reference such that execut
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Samothrakis, Stavros Nikolaou. "Acceleration techniques in ray tracing for dynamic scenes." Thesis, University of Sussex, 1998. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.241671.

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Singh, Ajeet. "GePSeA: A General-Purpose Software Acceleration Framework for Lightweight Task Offloading." Thesis, Virginia Tech, 2009. http://hdl.handle.net/10919/34264.

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Hardware-acceleration techniques continue to be used to boost the performance of scientific codes. To do so, software developers identify portions of these codes that are amenable for offloading and map them to hardware accelerators. However, offloading such tasks to specialized hardware accelerators is non-trivial. Furthermore, these accelerators can add significant cost to a computing system. <p> Consequently, this thesis proposes a framework called GePSeA (General Purpose Software Acceleration Framework), which uses a small fraction of the computational power on multi-core architectures
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Zhu, Huanzhou. "Developing graph-based co-scheduling algorithms with GPU acceleration." Thesis, University of Warwick, 2016. http://wrap.warwick.ac.uk/92000/.

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On-chip cache is often shared between processes that run concurrently on different cores of the same processor. Resource contention of this type causes the performance degradation to the co-running processes. Contention-aware co-scheduling refers to the class of scheduling techniques to reduce the performance degradation. Most existing contention-aware co-schedulers only consider serial jobs. However, there often exist both parallel and serial jobs in computing systems. This thesis aims to tackle these issues. We start with modelling the problem of co-scheduling the mix of serial and parallel
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Yalim, Hacer. "Acceleration Of Direct Volume Rendering With Texture Slabs On Programmable Graphics Hardware." Master's thesis, METU, 2005. http://etd.lib.metu.edu.tr/upload/12606195/index.pdf.

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This thesis proposes an efficient method to accelerate ray based volume rendering with texture slabs using programmable graphics hardware. In this method, empty space skipping and early ray termination are utilized without performing any preprocessing on CPU side. The acceleration structure is created on the fly by making use of depth buffer efficiently on Graphics Processing Unit (GPU) side. In the proposed method, texture slices are grouped together to form a texture slab. Rendering all the slabs from front to back viewing order in multiple rendering passes generates the resulting volume ima
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Sherban, V. Yu. "Software components of the system for the kinematic and dynamic analysis of machines for sewing, textile and shoe industries." Thesis, Київський національний університет технологій та дизайну, 2017. https://er.knutd.edu.ua/handle/123456789/6655.

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Wang, Tsu-Han. "Real-time Software Architectures and Performance Evaluation Methods for 5G Radio Systems." Electronic Thesis or Diss., Sorbonne université, 2022. https://accesdistant.sorbonne-universite.fr/login?url=https://theses-intra.sorbonne-universite.fr/2022SORUS362.pdf.

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La thèse porte sur les architectures temps réel pour la radio-logicielle 5G. Afin de répondre aux exigences de performances de la 5G, une accélération des procédés critiques combinée à des méthodes d’ordonnancement de processus temps réels sont nécessaires. Dans les systèmes embarqués 5G, l'accélération équivaut à une combinaison judicieuse d'unités matérielles supplémentaires pour les fonctions les plus coûteuses en termes de calcul avec des composants logiciels pour des procédures de contrôle complexe ainsi que l’arithmétique simples. Des solutions entièrement logicielles apparaissent égalem
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Tell, Eric. "Design of Programmable Baseband Processors." Doctoral thesis, Linköping : Univ, 2005. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-4377.

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Libros sobre el tema "Software acceleration"

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Mourelle, Luiza de Macedo. Hardware/Software interfacing in a software acceleration environment. UMIST, 1997.

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Nikkhah, B. A hardware/software partitioning scheme for software acceleration. UMIST, 1997.

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Mizrakian, V. Software acceleration of image processing algorithms using hardware implementation. UMIST, 1997.

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Mizrakian, V. Software acceleration of image processing algorithms using hardware implementation. UMIST, 1997.

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Luigi, Carro, ed. Dynamic reconfigurable architectures and transparent optimization techniques: Automatic acceleration of software execution. Springer, 2010.

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Tin, Michael Yu Chak. ExamInsightfor MCP/MCSE certification: Microsoft internet security and acceleration (ISA) server 2000, enterprise edition exam 70-227. TotalRecall Publications, 2003.

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Tin, Michael Yu Chak. ExamWise for MCP/MCSE certification: Microsoft internet security and acceleration (ISA) server 2000, enterprise edition exam 70-227. TotalRecall Publications, 2003.

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United States. National Aeronautics and Space Administration., ed. A method to determine the kinematics of the lower limbs of a subject pedaling a bicycle using encoders and accelerometers. National Aeronautics and Space Administration, 1994.

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Federico, Carminati, Galli Carminati Giuliana, and SpringerLink (Online service), eds. From the Web to the Grid and Beyond: Computing Paradigms Driven by High-Energy Physics. Springer Berlin Heidelberg, 2012.

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Parkinson, John. 60 minute software: Strategies for accelerating the information systems delivery process. Wiley, 1996.

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Capítulos de libros sobre el tema "Software acceleration"

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Cattaruzza, Dario, Alessandro Abate, Peter Schrammel, and Daniel Kroening. "Sound Numerical Computations in Abstract Acceleration." In Numerical Software Verification. Springer International Publishing, 2017. http://dx.doi.org/10.1007/978-3-319-63501-9_4.

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Gulati, Kanupriya, and Sunil P. Khatri. "Automated Approach for Graphics Processor Based Software Acceleration." In Hardware Acceleration of EDA Algorithms. Springer US, 2010. http://dx.doi.org/10.1007/978-1-4419-0944-2_11.

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Schmid, Moritz, Christian Schmitt, Frank Hannig, et al. "Big Data and HPC Acceleration with Vivado HLS." In FPGAs for Software Programmers. Springer International Publishing, 2016. http://dx.doi.org/10.1007/978-3-319-26408-0_7.

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Leroux, Jérôme, and Grégoire Sutre. "Acceleration in Convex Data-Flow Analysis." In FSTTCS 2007: Foundations of Software Technology and Theoretical Computer Science. Springer Berlin Heidelberg, 2007. http://dx.doi.org/10.1007/978-3-540-77050-3_43.

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Beevi, F. H. Aysha, C. F. Pedersen, S. Wagner, and S. Hallerstede. "Lateral Fall Detection via Events in Linear Prediction Residual of Acceleration." In Ambient Intelligence - Software and Applications. Springer International Publishing, 2014. http://dx.doi.org/10.1007/978-3-319-07596-9_22.

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Šimková, Marcela, and Ondřej Lengál. "Towards Beneficial Hardware Acceleration in HAVEN: Evaluation of Testbed Architectures." In Hardware and Software: Verification and Testing. Springer Berlin Heidelberg, 2013. http://dx.doi.org/10.1007/978-3-642-39611-3_25.

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Wang, Yanwei, Bingbing Li, Lu Lu, Jiangwei Wang, Rengang Li, and Hongwei Kan. "Hardware-Software Co-design for Deep Neural Network Acceleration." In Communications in Computer and Information Science. Springer Nature Singapore, 2023. http://dx.doi.org/10.1007/978-981-99-4402-6_16.

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Liu, Yang, and Liang Deng. "Acceleration of CFD Engineering Software on GPU and MIC." In Algorithms and Architectures for Parallel Processing. Springer International Publishing, 2015. http://dx.doi.org/10.1007/978-3-319-27161-3_77.

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Yan, Jiong, Ji Wang, and Huo-wang Chen. "UML Based Statistical Testing Acceleration of Distributed Safety-Critical Software." In Parallel and Distributed Processing and Applications. Springer Berlin Heidelberg, 2004. http://dx.doi.org/10.1007/978-3-540-30566-8_52.

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Saremi, Razieh, Ye Yang, and Abdullah Khanfor. "Ant Colony Optimization to Reduce Schedule Acceleration in Crowdsourcing Software Development." In Human Interface and the Management of Information. Information in Intelligent Systems. Springer International Publishing, 2019. http://dx.doi.org/10.1007/978-3-030-22649-7_23.

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Actas de conferencias sobre el tema "Software acceleration"

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Sheng, Chenxing, Shuo Zhang, Yaping Liu, and Haifu Liao. "Regular expression implementation: a comprehensive review from software algorithms to hardware acceleration." In Fifth International Conference on Computer Communication and Network Security (CCNS 2024), edited by Zhiyong Xiong and Zhaolong Ning. SPIE, 2024. http://dx.doi.org/10.1117/12.3038176.

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Hazarika, Anakhi, Nikumani Choudhury, and Soumyajit Poddar. "Approximate Vedic Multiplier Architecture for Efficient CNN Acceleration on Embedded Devices." In 2024 IEEE 48th Annual Computers, Software, and Applications Conference (COMPSAC). IEEE, 2024. http://dx.doi.org/10.1109/compsac61105.2024.00071.

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Hu, Jie, Mingyue Zhang, Bo Liu, Yuechen Wu, and Yingfeng Chen. "A Language-guided Acceleration Method for Smoke Testing of Game Quests." In 2024 IEEE 35th International Symposium on Software Reliability Engineering Workshops (ISSREW). IEEE, 2024. https://doi.org/10.1109/issrew63542.2024.00039.

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Ghiglino, Pablo, Mandar Harshe, and Guillermo Sarabia. "A High Throughput Software Acceleration to On-Board Artificial Intelligence for Earth Observation." In IAF Earth Observation Symposium, Held at the 75th International Astronautical Congress (IAC 2024). International Astronautical Federation (IAF), 2024. https://doi.org/10.52202/078362-0030.

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Huang, Rongjie, Yan Xu, Hao Li, et al. "Study of FPGA-based PCB defect detection with collaborative hardware and software acceleration." In 4th International Conference on Automation Control. Algorithm and Intelligent Bionics, edited by Jing Na and Shuping He. SPIE, 2024. http://dx.doi.org/10.1117/12.3039338.

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Wu, Zhenyu, Maolin Wang, and Hayden Kwok-Hay So. "A Hardware-Software Design Framework for SpMV Acceleration with Flexible Access Pattern Portfolio." In 2025 IEEE International Symposium on High Performance Computer Architecture (HPCA). IEEE, 2025. https://doi.org/10.1109/hpca61900.2025.00068.

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Li, Shicheng, Xin Yao, Renhai Chen, Wenjie Feng, and Gong Zhang. "A Soft-Hard Collaborative CNN Inference Acceleration System Based on NP Cores of DPU." In 2024 IEEE International Conference on Embedded Software and Systems (ICESS). IEEE, 2024. https://doi.org/10.1109/icess64277.2024.00012.

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Wu, Shengfeng, Yue Wu, and Shiyi Xu. "Acceleration of Random Testing for Software." In 2013 IEEE 19th Pacific Rim International Symposium on Dependable Computing (PRDC). IEEE, 2013. http://dx.doi.org/10.1109/prdc.2013.15.

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Sredojevic, Ranko, Andrew Wright, and Vladimir Stojanovic. "Hardware-Software Codesign for Embedded Numerical Acceleration." In 2013 IEEE 21st Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM). IEEE, 2013. http://dx.doi.org/10.1109/fccm.2013.27.

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Turan, Furkan, Ruan de Clercq, Pieter Maene, Oscar Reparaz, and Ingrid Verbauwhede. "Hardware acceleration of a software-based VPN." In 2016 26th International Conference on Field Programmable Logic and Applications (FPL). IEEE, 2016. http://dx.doi.org/10.1109/fpl.2016.7577321.

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Informes sobre el tema "Software acceleration"

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Olsen, B. Accelerator Production of Tritium Software Management Plan. Office of Scientific and Technical Information (OSTI), 1998. http://dx.doi.org/10.2172/763183.

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Razdan, Rahul. Unsettled Issues Regarding Autonomous Vehicles and Open-source Software. SAE International, 2021. http://dx.doi.org/10.4271/epr2021009.

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As automobiles morph from stand-alone mechanical objects to highly connected, autonomous systems with increasing amounts of electronic components. To manage these complex systems, some semblance of in-car decision-making is also being built and networked to a cloud architecture. This cloud can also enable even deeper capabilities within the broader automotive ecosystem. Unsettled Issues Regarding Autonomous Vehicles and Open-source Software introduces the impact of software in advanced automotive applications, the role of open-source communities in accelerating innovation, and the important to
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Heuring, Vincent P., and William M. Waite. Accelerating the Transfer of Technology for Implementing Domain Specific Software Architectures. Defense Technical Information Center, 1993. http://dx.doi.org/10.21236/ada264017.

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Haddad, Ibrahim. A Guide to Enterprise Open Source. The Linux Foundation, 2022. https://doi.org/10.70828/bmzb6635.

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Open source software (OSS) has transformed our world and become the backbone of our digital economy and the foundation of our digital world. From the internet and the mobile apps we use daily to the operating systems and programming languages we use to build the future, OSS has played a vital role. It is the lifeblood of the technology industry. Organizations involved in building products or services involving software, regardless of their specific industry or sector, are likely to adopt OSS and contribute to open source projects deemed critical to their products and services. Organizations ar
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Waraniak, John. Unsettled Issues on Sensor Calibration for Automotive Aftermarket Advanced Driver-Assistance Systems. SAE International, 2021. http://dx.doi.org/10.4271/epr2021008.

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Many automotive industry safety advocates have been pushing for greater market penetration for active safety and advanced driver-assistance systems (ADAS), with the goal of ending deaths due to car crashes. However, there are far-reaching implications for the collision repair, specialty equipment, and performance aftermarket sectors—after a collision or modification, the ADAS system functionality must be preserved to maintain, driver, passenger, and road user safety. To do this, sensor recalibration and ADAS functional safety validation and documentation after repair, modification, or accessor
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Kerrigan, Susan, Phillip McIntyre, and Marion McCutcheon. Australian Cultural and Creative Activity: A Population and Hotspot Analysis: Bendigo. Queensland University of Technology, 2020. http://dx.doi.org/10.5204/rep.eprints.206968.

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Bendigo, where the traditional owners are the Dja Dja Wurrung people, has capitalised on its European historical roots. Its striking architecture owes much to its Gold Rush past which has also given it a diverse cultural heritage. The creative industries, while not well recognised as such, contribute well to the local economy. The many festivals, museums and library exhibitions attract visitors from the metropolitan centre of Victoria especially. The Bendigo Creative Industries Hub was a local council initiative while the Ulumbarra Theatre is located within the City’s 1860’s Sandhurst Gaol. Ma
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Calahorra-Jimenez, Maria, Nigel Blampied, Elhami Nasr, and Tariq Shehab. Survey of Building Information Modeling for Infrastructure (BIM4I). Mineta Transportation Institute, 2025. https://doi.org/10.31979/mti.2024.2453.

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The rapid development of information technologies is transforming how data and information are produced, shared, exchanged, and managed. This transformation is accelerating in state departments of transportation (DOTs) across the country due to the pressing need for efficient means of delivering transportation projects and an enhanced need for internal and external collaboration. A key driver for this transformation is the implementation of Building Information Modeling for Infrastructures (BIM4I). The primary objective of this research was to develop actionable recommendations for DOTs to fac
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Tao, Yang, Amos Mizrach, Victor Alchanatis, Nachshon Shamir, and Tom Porter. Automated imaging broiler chicksexing for gender-specific and efficient production. United States Department of Agriculture, 2014. http://dx.doi.org/10.32747/2014.7594391.bard.

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Extending the previous two years of research results (Mizarch, et al, 2012, Tao, 2011, 2012), the third year’s efforts in both Maryland and Israel were directed towards the engineering of the system. The activities included the robust chick handling and its conveyor system development, optical system improvement, online dynamic motion imaging of chicks, multi-image sequence optimal feather extraction and detection, and pattern recognition. Mechanical System Engineering The third model of the mechanical chick handling system with high-speed imaging system was built as shown in Fig. 1. This syst
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