Tesis sobre el tema "Threshold voltage monitor circuit"

Um monitor de tensão de limiar (VT0) é um circuito que, idealmente, entrega o valor do VT0 como uma tensão na saída, para uma determinada faixa de temperatura, sem a necessidade de polarização externa, configurações paramétricas, ajuste de curvas ou qualquer cálculo subsequente. Estes circuitos podem ser usados em sensores de temperatura, referências de tensão e corrente, dosímetros de radiação e outras aplicações, uma vez que a dependência do VT0 nas condições de operação é um aspecto bem modelado. Além disso, estes circuitos podem ser utilizados para monitoramento de processos de fabricação e para compensação da variabilidade do processo, uma vez que o VT0 é um parâmetro chave para o comportamento do transistor e sua modelagem. Nesta tese, são apresentadas três novas topologias de circuitos, duas são monitores de VT0 NMOS e a terceira é um monitor de VT0 PMOS. As três estruturas são topologias de circuito auto-polarizadas que não utilizam resistências, e apresentam alta rejeição a variações na alimentação, baixa sensibilidade de Linea, e permitem a extração direta da tensão de limiar para grandes intervalos de temperatura e de tensão de alimentação, com pequeno erro. Sua metodologia de projeto é baseada no modelo unificado controlado por corrente (UICM), um modelo MOSFET que é contínuo, desde o nível de inversão fraca a forte e para as regiões de operação de triodo e saturação. Os circuitos ocupam uma pequena área de silício, consomem apenas dezenas de nanowatts, e podem ser implementados em qualquer processo padrão CMOS digital, uma vez que só utilizam transistores MOS (não precisa de nenhum resistor). Os monitores de VT0 são utilizados em diferentes aplicações, a fim de investigar a sua funcionalidade e comportamento como parte de um sistema. As aplicações variam de uma tensão de referência, que apresenta um desempenho comparável ao estado da arte, para uma configuração que permite obter uma menor variabilidade com processo na saída de um circuito auto-polarizado que gera um tensão CTAT. Além disso, explorando a capacidade de funcionar como um gerador de corrente específica (ISQ) que os monitores de VT0 aqui apresentados oferecem, introduz-se um novo circuito auto-polarizado que gera um tensão CTAT, que é menos sensível a variações de processo, e pode ser usado em referências de tensão band-gap.
A threshold voltage (VT0) monitor is a circuit that ideally delivers the estimated VT0 value as a voltage at its output, for a given temperature range, without external biases, parametric setups, curve fitting or any subsequent calculation. It can be used in temperature sensors, voltage and current references, radiation dosimeters and other applications since the MOSFET VT0 dependence on the operation conditions is a very well modeled aspect. Also, it can be used for fabrication process monitoring and process variability compensation, since VT0 is a key parameter for the transistor behavior and modeling. In this thesis, we present three novel circuit topologies, two of them being NMOS VT0 monitors and the last one being a PMOS VT0 monitor. The three structures are resistorless self-biased circuit topologies that present high power supply rejection, low line sensitivity, and allow the direct extraction of the threshold voltage for wide temperature and power supply voltage ranges, with small error. Its design methodology is based on the Unified Current Control Model (UICM), a MOSFET model that is continuous from weak to strong inversion and from triode to saturation regions. The circuits occupy small silicon area, consume just tens of nanoWatts, and can be implemented in any standard digital CMOS process, since they only use MOS transistors (does not need any resistor). The VT0 monitors are used in different applications in order to prove their functionality, and behavior as part of a system. The applications vary from a reference voltage, that presents performance comparable with state-of-the-art works, to a configuration that allows to obtain a lower process variability, in the output of a self-biased circuit that generates a complementary to the absolute temperature (CTAT) voltage. In addition, exploiting the ability to operate as an specific current (ISQ) generator, that the VT0 monitors presented here offer, we introduced a new self-biased circuit that produces a CTAT voltage and is less sensitive to process variations, and can be used in band-gap voltage references.

La sensibilité accrue aux variations des procedés de fabrication, de tension, de température et de vieillissement (PVTA) dans les nœuds technologiques avancés d'integration est responsable d'une dégradation significative des spécifications des circuits integrés lors de la fabrication à grand volume. Celle-ci est devenue une préoccupation croissante dans la conception de circuits numériques, qui doit faire face aux exigences de plus en plus strictes des applications modernes en termes d'efficacité énergétique, de fiabilité et de sécurité. Dans ce travail de thèse, les techniques de surveillance de timing intégrée et de compensation sont explorées pour répondre efficacement à ces exigences contradictoires. Dans ce travail de thèse, les techniques proposées ont été étudiés séparément puis combinées dans 3 démonstrateurs SoC numériques fabriqués en technologie 28nm FD-SOI CMOS, dont l'un a été mesuré au moment de la rédaction de ce manuscrit.La surveillance de timing intégrée est proposée comme solution de conception pour permettre la compensation des variations PVTA, la surveillance de la sécurité en operation et la protection contre les attaques hardware en timing. Les moniteurs de timing de l'état de l'art ont été évalués dans la perspective d'une intégration dans des produits industriels, ce qui privilégie des caractéristiques telles que la reusabilité et les faibles coûts d'intégration. Les avantages identifiés de la surveillance de timing de registre à registre ont conduit à la mise en œuvre d'un circuit témoin reconfigurable (Tunable Replica Circuit en langue anglaise) avec une sensibilité de 3 mV/bit en 28nm FD-SOI CMOS, qui démontre un suivi rapide et précis des variations PVTA d'un SoC basé sur un ARM Cortex-R4F à travers des corners lent / typique / rapide, une plage de tension 0.5/1.2 V, une gamme de temperature -40/150°C, et de vieillissement jusqu'a fin de vie. Enfin, ce travail propose un nouveau moniteur de timing qui permet de surmonter les faiblesses des solutions existantes, en obtenant simultanément la reutilisabilité élevée et la large plage de surveillance des oscillateurs en anneau et l'acquisition rapide et précise des circuits témoins reconfigurables.L'exploration des techniques d'adaptation et de compensation commence par la détermination de leur champ d'application dans les produits industriels: l'amélioration des pires cas qui définissent les limites de spécifications du produit lors de la fabrication à grand volume. Dans cette perspective, la région d'application optimale des techniques de voltage scaling et de body biasing a été déterminée et leur impact sur les pires cas des SoC numériques a été évalué. Enfin, ces travaux montrent comment la surconsommation induite par l'application séparée de voltage scaling ou body biasing peut être atténuée par la combinaison des deux, en particulier dans les circuits avec une variété de points de performance opérationnelle (OPPs).Les avantages des techniques proposées ont été démontrés dans un SoC numérique qui optimise son énergie à travers d'une largeur de fréquence de 11X en combinant le voltage scaling adaptatif, body biasing adaptatif et le bias-in-memory-array avec un tunable replica circuit pour la sécurité, la régulation de puissance intégrée et la compensation. Grâce à l'application de ces techniques, le circuit proposé permet de surmonter les limites précédemment signalées et démontre une amélioration des performances de 21X, une Vmin inférieure de 120 mV et une durée de vie de 8X, pour les OPP de faible puissance, de moyenne et de haute performance respectivement.Les études présentées ici ont été incluses dans plusieurs chapitres d'un livre scientifique qui sera publié cette année. En outre, elles ont contribué à une nouvelle plateforme de technologie et de conception. Enfin, 3 publications dans des conférences de l'IEEE et 3 demandes de brevet ont résulté de ce travail de thèse
The increased sensitivity to Process, Voltage, Temperature, and Aging (PVTA) variations in scaled integrated circuits' technology nodes is responsible for a significant degradation in the products' specifications during high volume manufacturing. This has become a growing concern in digital circuit design, which has to cope with the increasingly stringent requirements of modern applications in terms of energy efficiency, reliability, and safety. In this thesis work, embedded timing monitoring and compensation techniques are explored to efficiently address these conflicting requirements. The proposed techniques are studied separately and then combined in 3 digital SoC demonstrators manufactured in 28nm FD-SOI CMOS technology, one of which has been measured at the time of this manuscript's writing.Embedded timing monitoring is proposed as a design solution to enable PVTA compensation, in-field safety monitoring and security protection against hardware timing attacks. The state-of-the-art timing monitors are evaluated from the perspective of an integration into industrial products, emphasizing features such as high reusability and low integration costs. The identified advantages of register-to-register timing monitoring have led to the implementation of a 3mV/bit tunable replica circuit in 28nm FD-SOI CMOS, which demonstrates a fast and accurate PVTA tracking of an ARM Cortex-R4F based SoC across slow/typical/fast process, 0.5/1.2V, -40/150ºC, and End Of Life (EOL) aging. Finally, this work proposes a novel timing monitor that overcomes the weaknesses of existing solutions, simultaneously achieving the high reusability and wide monitoring range of ring oscillators and the fast and accurate timing acquisition of tunable replica circuits.The exploration of adaptive and compensation techniques begins with the determination of their application scope in industrial designs: the improvement of the worst-case limiting corners that set the product's specifications during high volume manufacturing. Following this perspective, the optimal region of application of voltage scaling and body biasing techniques has been determined and their impact on the worst-case specifications of digital SoCs has been assessed. Finally, this work demonstrates how the power overhead induced by the separate application of voltage scaling or body biasing can be mitigated through the combination of both, specially in circuits with a variety of Operational Performance Points (OPPs).The benefits of the proposed techniques have been demonstrated in a digital SoC that optimizes its energy across 11X frequency-wide OPPs by combining adaptive voltage scaling, adaptive body biasing, and bias-in-memory-array with a tunable replica circuit for safety, embedded power regulation and compensation. Through the application of these techniques the proposed design overcomes previously reported limitations and demonstrates an improvement by 21X performance, 120mV lower Vmin, and 8X lifetime, the low-power, mid-, and high-performance OPPs respectively.The studies reported here have been included in several chapters of a scientific book to be published this year. Furthermore, they have contributed to a new technology and design platform. Finally, 3 IEEE conference publications and 3 patent applications have resulted from this thesis' work

Des développements technologiques récents concernant les photodiodes à effet avalanche (PDA) ont mené à la conception et la fabrication d'un tout nouveau module de détection de radiation TEP (tomographie d'émission par positrons) destiné à l'imagerie moléculaire préclinique. Il est basé sur une matrice de 8 par 8 scintillateurs LYSO (ortho-silicate de lutétium dopé au cérium, cerium-doped lutetium yttrium orthosilicate ) individuellement couplés aux pixels de deux matrices monolithiques de 4 par 8 PDA. Cette avancée, pouvant amener la résolution spatiale d'un scanner à passer sous la barrière du mm, exige la conception d'un tout nouveau système d'acquisition de données. En effet, il faut adapter le système de lecture individuelle de chacun des pixels du bloc de détection de façon à satisfaire la multiplication par ~8, relativement à une version antérieure (le LabPET[indice supérieur TM] I), de la densité de pixels du futur scanner LabPET[indice supérieur TM] II. Conséquemment, le traitement de signal numérique ne peut être exclusivement embarqué dans les matrices de portes logiques programmable (field-programmable gate array , FPGA) du système d'acquisition, en considérant les aspects monétaires, d'espace occupé et de puissance consommée de l'ensemble du projet LabPET[indice supérieur TM] II. De façon à s'adapter à cette nouvelle réalité, un nouveau circuit intégré à application spécifique (application specific integrated circuit, ASIC) à signaux mixtes avec 64 canaux d'acquisition, fabriqué avec la technologie TSMC CMOS 0,18 [micromètre], a été conçu. L'ASIC utilise la méthode de temps au-dessus d'un seuil (time over threshold , ToT), déjà implantée dans des applications de physique des hautes-énergies, de manière à extraire numériquement l'information relative à un rayonnement interagissant avec la matrice de détection (l'énergie, le temps et le numéro de pixel de l'événement). Dans le cadre de ce projet, une architecture complexe de machines à états-finis, cadencée par une horloge de 100 MHz, a été implantée et elle permet à l'ASIC d'identifier le taux anticipé de 3 000 événements par seconde par canal. Ceci est réalisé en calculant en temps réel le paramètre ToT tout en assurant la calibration adéquate de chacune des chaînes d'acquisition. Le circuit intégré peut caractériser jusqu'à 2 Mévénements/s malgré son unique lien différentiel à bas voltage (low-voltage differential signaling, LVDS) de transfert de données et consomme environ 600 mW. L'ASIC a été développé en suivant un processus de conception de circuits intégrés à signaux mixtes. Il permet notamment de minimiser et de vérifier l'impact des indésirables effets parasites sur la circuiterie analogique et numérique de l'ensemble avant que les dessins de masques ne soient envoyés vers la fonderie pour fabriquer le circuit désiré.

Description du dispositif permettant d'analyser des plaques de 2**(") de diametre a 1ok, avec de hautes resolutions laterales (20 et 1mu m), eventuellement a diverses energies. Realisation de cartographies a 300 et 10k: tres bonne correlation entre intensite de photoluminescence et defauts cristallins et chimiques; correspondance avec des mesures de resistivite electrique. Mise au point d'une procedure de qualification de l'homogeneite microscopique de gaas semi-isolant. Possibilite de prevoir la dispersion des tensions de seuil de transistors fet d'apres l'analyse du support de defaut, donc de classer et choisir les supports pour la realisation de circuits integres

碩士
國立臺灣大學
電機工程學研究所
88
This thesis reports two low-voltage low-power circuits which are designed by using PD SOI DTMOS techniques. In chapter 2, this thesis introduced a novel 0.7V two-port 6T SRAM memory cell structure with single-bit-line simultaneous read-and-write access (SBLSRWA) capability using partially-depleted SOI CMOS dynamic-threshold techniques. With an innovative approach by connecting the body terminal for an NMOS device in the latch and the write access pass transistor to write word line, this 6T memory cell can be used to provides SBLSRWA capability for 0.7V two-port SOI CMOS cache memory. In chapter 3, this thesis introduced a novel low-voltage content addressable memory (CAM) cell structure using partially-depleted SOI CMOS dynamic-threshold techniques. With a unique structure by dynamically controlling the bodies of transistors that compose XOR portion of CAM cell via two auxiliary transistors, this CAM cell can be used to provide faster compare capability for low voltage range SOI CMOS CAM applications.

碩士
國立交通大學
電機工程學系
102
This thesis proposes a DC-DC converter operation at 0.5 V. The circuit consists of four parts: a comparator, a digital control circuit, a switched capacitor and a digital circuit under test (DUT). The digital control circuit take the comparator output to control the switched capacitor operation to achieve the target voltage according to the reference voltage. It’s 2-phase interleaved converter can be configured into three topologies, which supports the output voltages of 0.25-0.45 V from the 0.5 V input supply, it has an efficiency between 59-79% for the load current of 100 µA. This converter is designed with all digital control without any static power consumption. At the load of 0.45 V and 100 µA, the switched capacitor consumes 57 µW. Among them, 45 µW is for the DUT with an efficiency of 79 %. The comparator and the digital control consume only 2 µW under lowest load power. It can be applied to implantable biomedical chip with low power consumption circuits. This chip is fabricated in TSMC GUTM 90 nm CMOS process, with high efficiency. The chip area is 1mm × 1mm.

A great research effort has been invested on finding alternatives to CMOS that have better process variation and subthreshold leakage. From possible candidates, FinFET is the most compatible with respect to CMOS and it has shown promising leakage and speed performance. This thesis introduces basic characteristics of FinFETs and the effects of FinFET physical parameters on their performance are explained quantitatively. I show how dual- V th independent-gate FinFETs can be fabricated by optimizing their physical parameters. Optimum values for these physical parameters are derived using the physics-based University of Florida SPICE model for double-gate devices, and the optimized FinFETs are simulated and validated using Sentaurus TCAD simulations. Dual-14, FinFETs with independent gates enable series and parallel merge transformations in logic gates, realizing compact low power alternative gates with competitive performance and reduced input capacitance in comparison to conventional FinFET gates. Furthermore, they also enable the design of a new class of compact logic gates with higher expressive power and flexibility than CMOS gates. Synthesis results for 16 benchmark circuits from the ISCAS and OpenSPARC suites indicate that on average at 2GHz and 75°C, the library that contains the novel gates reduces total power and the number of fins by 36% and 37% respectively, over a conventional library that does not have novel gates in the 32nm technology.

碩士
國立交通大學
電子研究所
100
Variation issue is one of the key design factors for robust current VLSI systems, and this kind of issue will affect the device threshold voltage (VTH) value. However, the VTH value is still associated with the device performance, stability and reliability, then when we talk about the variation issue that the VTH is the important indicator to reflect this phenomenon. So we want to create a measurement structure that can measure the device threshold voltage, then we can collect the voltage data to realize how the variation issue will affect this testing chip. We present an all-digital bit transistor characterization scheme for CMOS 6T SRAM array. The scheme employs an on-chip operational amplifier feedback loop to measure the individual threshold voltage (VTH) of 6T SRAM bit cell transistors (holding PMOS, pull-down NMOS, and access NMOS) in SRAM cell array environment. The measured voltage is converted to frequency with dual VCO and counter based digital read-out to facilitate data extraction, processing, and statistical analysis. A 512Kb test chip is implemented in 55nm 1P10M Standard Performance (SP) CMOS technology. Monte Carlo simulations indicate that the accuracy of the VTH measurement scheme is about 2-7mV at TT corner across temperature range from 85oC to -45oC, and post-layout simulations show the resolution of the digital read-out scheme is < 0.2mV per bit.

碩士
國立交通大學
電子工程系
88
Nowadays, many of the high-technology electronics industries are developing advanced communication and multimedia products. The requirements of these products, such as internet peripherals, mobile phone, and digital camera, become more and more. And certain circuits in these products act as the bridge between the real world and the digital processing units. The representation circuits like digital to analog converter (DAC) need that devices, such as transistors, resistors, capacitors, are best the same in parameters when they are being designed. However, there are not two things exactly the same. So, the research of the mismatch model becomes more and more important. Once we get the statistical properties of the mismatch, we can use it to compute the yield of some kind of analog/digital circuits such as to see if the design is worth of being implemented. Besides, we can also use it to improve the design rule of circuits in order to make the least effect of mismatch on circuits. This paper contains two major parts. The first part is about the development of mismatch model. Also discussed is the reasonable range of the parameters in the model equation. In the second part, we try to use the standard deviation of the threshold voltage to compute the yield in a precise DAC, and address the theory behind as well as its corection.

碩士
大同大學
電機工程研究所
90
In this thesis, we consider the high-speed operation of MOS transistors in the digital circuit, we analysis a new reduced swing logic style called dynamic current mode logic (DyCML) that reduces both gate and interconnect power dissipation. We also use the technique of feedback component in MCML (MOS current mode logic) to low voltage output swing and power dissipation. We usually consider the circuit in high-speed operation system, which can tolerate to threshold voltage fluctuation. By the computer simulations, we know that it can improve the bad part that threshold voltage fluctuation and reduce the output voltage swing as well as increase the efficiency and capacitance of the circuit by add the other component. As a result, CMOS 10-Gb/s can be used fitly.

碩士
國立臺灣大學
電機工程學研究所
89
This thesis reports several low-voltage dynamic logic circuits using partially-depleted (PD) SOI CMOS dynamic threshold (DTMOS) techniques. In chapter 2, two novel true single-phase-clocking (TSPC) latches using PD SOI COMS DTMOS technique for low-voltage CMOS VLSI circuits are proposed. Via controlling the body voltage dynamically, the 0.8V split-output PD-SOI TSPC latch using DTMOS techniques shows an 80% reduction in the switching time and the non-split-output latch has less slow clock problems as verified by MEDICI result. In chapter 3, a 0.7V Manchester carry look-ahead circuit using PD SOI DTMOS techniques suitable for low-voltage CMOS VLSI systems is reported. Using asymmetrical dynamic threshold pass-transistor (ADTPT) technique with the PD-SOI DTMOS dynamic logic circuit, this 0.7V PD-SOI DTMOS Manchester carry look-ahead has an improvement of 30% in the propagation delay time as compared to the conventional circuit based on two-dimensional device simulation MEDICI results.

碩士
國立交通大學
電子工程系
87
It is well known that scaling down both the supply voltage and threshold voltage is effective in reducing the power consumption while maintaining the high operation speed. However, it induces some problems, for instance, the standby power is increased dramatically. In order to cope with the problem, several circuit schemes are proposed. We classify those schemes into 3 classes: 1) Multiple Threshold voltage(MTCMOS) 2) Variable Threshold voltage with substrate bias controlling (VTCMOS) 3) combined MTCMOS and VTCMOS(MVCMOS). In addition, Silicon on Insulator (SOI) based technology is also discussed. In this thesis, we also proposed an improved RCSFF (Reduced Clock Swing Flip-Flop) circuit design which is applicable to both active and standby mode. The improved flip-flop is made of low-Vth devices to achieve high speed with serial cut-off high Vth MOSs. 6T SRAM cell is added to the flip-flop to hold the latched data in the standby mode. The 6T SRAM storage element is composed of high-Vth MOSs to suppress leakage current in standby mode. Finally, we adopted the improved RCSFF(Reduced Clock Swing Flip-Flop) circuit to design parallel, low power, high speed, and 2-stage pipelined multipliers with Modified Booth algorithm. From the architecture design, circuit design to floor plan and routing, high speed and low power consumption are our design guidelines. 16*16 bits and 32*32 bits multipliers are implemented to demonstrate the effectiveness of our techniques. From our simulation results, the low power consumption and high operation speed do achieve our expectation.

碩士
國立清華大學
電子工程研究所
102
Charge pump is a kind of DC-DC converter circuit which uses capacitors as energy store elements to create a higher output steady voltage. It’s widely used in voltage converter, power management system and phase lock loop because of its simple circuit structure and high power efficiency. Building the circuit model to do analysis work is helpful for circuit design and optimization. Dickson charge pump circuit is the fundamental and most widely used charge pump circuit. The conventional analytical model based on the Dickson charge pump is studied in this thesis. An improved Dickson charge pump model with an effective Vth parameter is derived in response to the drawbacks of the conventional model (as can’t be used to analysis the effect of MOS width on the circuit performance). The improved model can predict the steady-state output voltage more accurate. As linear capacitor is used as the charging capacitor in the charge pump circuit, the circuit area problem can’t be ignored. Larger circuit area leads to larger costs, so circuit area optimization work should be done on the design of charge pump circuit. In this thesis, to decrease the circuit area, a new design using varactor as the charging capacitor to replace of linear capacitor is derived. An improved area minimization work based on the effective threshold voltage Dickson charge pump model and varator charging capacitor is done on the Dickson charge pump circuit. Circuit which has been done by this area optimized work will have great area advantage compared to the conventional Dickson charge pump circuit which hasn’t been area optimized. In this thesis, all simulations are based on TSMC 0.18um CMOS model. The clock has an amplitude of -1.5V to 1.5V, of which frequency is 100 (KHz) and the duty cycle is 50%. The objective steady-state output voltage is 1.5 (V) and output current is 1 0(uA).

碩士
國立清華大學
電子工程研究所
101
The interconnect line width and spacing shrink with advanced technology. The reduction in line space increases the electric field in the dielectric between metal lines. Thus, time dependent dielectric breakdown (TDDB) needs to be investigated and resolved before the technology is fully qualified. Before the dielectric is completely breakdown, leakage current has been observed to increase (soft breakdown). During this time, the interconnect capacitance (Cmom) might have been changed. But, there is no good way of measuring the capacitance during soft breakdown. Yang has proposed a 4T differential ring oscillator as a real time capacitor monitor circuit [1] with high sensitivity. It magnifies the oscillation frequency change due to capacitance change with Miller effect. But the absolute capacitance is unknown using this method. Besides, it is desirable to observe soft breakdown in shorter time by higher voltage stress, but the I/O MOSFET might be unavailable while technology is in development. An accurate capacitance measurements method under process variation and higher voltage stress using core MOSFET circuit are presented in this thesis. For accurate measurement, the slope matching method is proposed to eliminate process variation using external reference capacitors (Cext). The Cext is connected to the output ports of differential pair. And the Cmom is connected in the same except with additional transmission gates on both ends. The slopes (dT/dC) for Cmom and Cext should be very close to each other if transmission gate is properly designed. Using two or more external reference capacitors provide reference slope (ΔTCext/ΔCext). And ΔTCmom is measured during TDDB soft-breakdown. ThusΔCmom is found by reference slope and measured ΔTCmom. The circuit design is based on TSMC 65LP technology. The core MOSFET based monitor circuit provides higher (2xVDD) stress on the target capacitor without gate oxide overstress. The circuit consists of proposed differential pair, two types of peripheral circuit, cascode core transmission gate and its control circuit. If the I/O MOSFET is taken into consideration, there are five types of monitor circuit. For easy observation, the sensitivity should be high. For accurate measurement, the slope offset of Cmom/Cext should be small. In the end, the best type of monitor circuit is chosen with highest (sensitivity/slope offset) under five corner simulations.

碩士
臺灣大學
電子工程學研究所
95
The threshold voltage of hydrogenated amorphous silicon thin-film transistor(a-Si:H TFT) increases with time due to bias stress. This causes the driving current and emitting brightness of organic light emitting diodes (OLED) to decay with time. Thus a new TFT voltage-programmed compensation pixel circuit for threshold voltage shift which consists of four transistors and one capacitor (4T1C) is proposed in this thesis. After a series of improvement in the design of the TFT structure and processing parameters, the TFT structure is optimized for the driving circuit of OLED. Both the simulation and experimental results reveal that the proposed 4T1C circuit can compensate the threshold voltage shift of the amorphous silicon TFT. Comparing to the traditional two transistors and one capacitor (2T1C) driving circuit, the new driving circuit gives a better compensation to the current degradation. In simulation, the theoretical current drop after a 30 minutes bias stress is in the range from 7% to 28 %, the current error of the proposed 4T1C driving circuit can be reduced to less than 3 %. The experimental results indicate that the degradation of OLED current of the proposed 4T1C driving circuit could be improved to less than half of the traditional 2T1C pixel.

abstract: Process variations have become increasingly important for scaled technologies starting at 45nm. The increased variations are primarily due to random dopant fluctuations, line-edge roughness and oxide thickness fluctuation. These variations greatly impact all aspects of circuit performance and pose a grand challenge to future robust IC design. To improve robustness, efficient methodology is required that considers effect of variations in the design flow. Analyzing timing variability of complex circuits with HSPICE simulations is very time consuming. This thesis proposes an analytical model to predict variability in CMOS circuits that is quick and accurate. There are several analytical models to estimate nominal delay performance but very little work has been done to accurately model delay variability. The proposed model is comprehensive and estimates nominal delay and variability as a function of transistor width, load capacitance and transition time. First, models are developed for library gates and the accuracy of the models is verified with HSPICE simulations for 45nm and 32nm technology nodes. The difference between predicted and simulated σ/μ for the library gates is less than 1%. Next, the accuracy of the model for nominal delay is verified for larger circuits including ISCAS'85 benchmark circuits. The model predicted results are within 4% error of HSPICE simulated results and take a small fraction of the time, for 45nm technology. Delay variability is analyzed for various paths and it is observed that non-critical paths can become critical because of Vth variation. Variability on shortest paths show that rate of hold violations increase enormously with increasing Vth variation.
Dissertation/Thesis
M.S. Electrical Engineering 2011

碩士
國立臺灣科技大學
光電工程研究所
102
Recently, active matrix organic light-emitting diode (AMOLED) has attracted a much attention due to its extraordinary properties, such as wide viewing angle, fast response time, high contrast ratio, high color saturation and self-emissive ability. However, luminance of AMOLED decayed after long time operation to lead short lifetime of product. Recently, using the reverse bias to prolong OLED lifetime is investigated. In the driving pixel circuit for AMOLED, low-temperature polycrystalline-silicon thin-film transistors (LTPS-TFTs) plays an important part due to its high current driving capability. Since the high current driving capability of LTPS-TFTs, the size of pixel circuit can be minimized to reach higher display quality. However, the various characteristic of LTPS-TFTs due to the excimer laser annealing process, which will further cause the non-uniform driving current under same gray-scale. Hence, many pixel circuit researches are proposed and this issue is effectively ameliorated. Thus, in this thesis, we want to design novel pixel circuits that not only compensate the non-uniformity of TFTs but also the OLED luminance degradation issue, and the high speed operation is also applied in the circuits. Recently, Metal Oxide TFT (a-IGZO TFT) is paid much attention because a-IGZO TFT has the current driving capability between LTPS-TFT and a-Si TFT and has great uniformity to fabricate large size display on fabrication process. However, a-IGZO TFT has non-uniform of electrical characteristics under long time operation which will further cause the non-uniform driving current under same gray-scale. Hence, many pixel circuit researches are proposed and this issue is effectively ameliorated. Thus, in this thesis, we want to design novel pixel circuits that can compensate the non-uniformity of TFTs and the stereo 3D effect is also applied in the circuits. The proposed pixel circuit is also applied the reverse bias to ameliorate OLED lifetime. Base on above reason, we proposed two compensating pixel circuits are driven by LTPS-TFTs and a-IGZO TFTs respectively and with high quality simultaneous emission (SE) driving scheme. The two proposed pixel circuits are 2.5T0.5C and 5T2C respectively. Through the parameter modulation, these two circuits achieved the performances what we expected and verified by AIM-SPICE. The first proposed pixel circuit is composed of an upper of pixel and a lower of pixel. In the 2.5T0.5C pixel circuit, the high speed driving is verified by simulator. The current error rate under various threshold voltage of TFT(ΔVTH = ±0.33 V) is less than 4%. To verify by simulation results, the magnitude of reverse bias which is applied to OLED is determined by the magnitude of driving current in the 2.5T0.5C pixel circuit. Hence, the reverse bias application in the proposed pixel circuit can ameliorate the OLED lifetime effectively. Base on the mention above, the proposed pixel circuit not only offers a stable current to maintain the image uniformity under high speed driving but also prolongs the OLED lifetime effectively. Furthermore, we simulated an assumed 30 inch display with all resistance and capacitance of signal lines. Simulation results demonstrate that the current error rate of four corners of display is less than 1.2%.。 In the 5T2C pixel circuit, the high speed 3D driving is verified by simulator. The current error rate of this pixel circuit under various threshold voltage of TFT(ΔVTH = ±3 V) and OLED (ΔVTH = +0.33 V) is less than 11%. Furthermore, we utilize a signal line which controls the switch as a signal of reverse bias. Hence, the reverse bias application in the proposed pixel circuit can ameliorate the OLED lifetime effectively. Due to the above simulation results, the capability of compensation is achieved as what we expected under high speed driving. Hence, we believed that the two proposed pixel circuits have excellent current driving capability to offer the stable current and prolong OLED lifetime effectively. It is suitable in large size and high resolution AMOLED displays.

Thin Film Transistors (TFTs) are widely used in large area electronics because they offer the advantage of low cost fabrication and wide substrate choice. TFTs have been conventionally used for switching applications in large area display arrays. But when it comes to designing a sensor actuator system on a flexible substrate comprising entirely of organic and inorganic TFTs, there are two main challenges – i) Fabrication of complementary TFT devices is difficult ii) TFTs have a drift in their threshold voltage (VT) on application of gate bias. Also currently there are no circuit simulators in the market which account for the effect of VT drift with time in TFT circuits. The first part of this thesis focuses on integrating the VT shift model in the commercially available AIM-Spice circuit simulator. This provides a new and powerful tool that would predict the effect of VT shift on nodal voltages and currents in circuits and also on parameters like small signal gain, bandwidth, hysteresis etc. Since the existing amorphous silicon TFT models (level 11 and level 15) of AIM-Spice are copyright protected, the open source BSIM4V4 model for the purpose of demonstration is used. The simulator is discussed in detail and an algorithm for integration is provided which is then supported by the data from the simulation plots and experimental results for popular TFT configurations. The second part of the thesis illustrates the idea of using negative feedback achieved via contact resistance modulation to minimize the effect of VT shift in the drain current of the TFT. Analytical expressions are derived for the exact value of resistance needed to compensate for the VT shift entirely. Circuit to realize this resistance using TFTs is also provided. All these are experimentally verified using fabricated organic P-type Copper Phthalocyanine (CuPc) and inorganic N-type Tin doped Zinc Oxide (ZTO) TFTs. The third part of the thesis focuses on building a robust amplifier using these TFTs which has time invariant DC voltage level and small signal gain at the output. A differential amplifier using ZTO TFTs has been built and is shown to fit all these criteria. Ideas on vertical routing in an actual sensor actuator interface using this amplifier have also been discussed such that the whole system may be “tearable” in any contour. Such a sensor actuator interface can have varied applications including wrap around thermometers and X-ray machines.