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Artículos de revistas sobre el tema "Threshold voltage monitor circuit"

Autor: Grafiati

Publicado: 4 de junio de 2021

Última modificación: 15 de febrero de 2022

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1

Bai, Fan Gyan y Ming San Ouyang. "Based on LPC2388 Mine Microseismic Monitor". Advanced Materials Research 846-847 (noviembre de 2013): 531–34. http://dx.doi.org/10.4028/www.scientific.net/amr.846-847.531.

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A new type of mine microseismic monitoring is introduced. The microseismic signal by these downhole sensors collecting, through the differential amplification circuit and filter processing circuit, enhance the potential to voltage A/D conversion chip required. The conversion result is read by ARM controller. The controller processes those data using wavelet denoising, and uses the Ethernet control circuit using TCP/IP protocol transmitte themto the PC. On the trap circuit, Butterworth low-pass filter circuit, wavelet threshold denoising have been simulated, the experimental results basically reached the design requirements.

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2

Olmos, Alfredo, Fabricio Ferreira, Fernando Paixão Cortes, Fernando Chavez y Marcelo Soares Lubaszewski. "A 2-Transistor Sub-1V Low Power Temperature Compensated CMOS Voltage Reference: Design and Application". Journal of Integrated Circuits and Systems 10, n.º 2 (28 de diciembre de 2015): 74–80. http://dx.doi.org/10.29292/jics.v10i2.408.

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This paper presents the design and application of a CMOS sub-1V voltage reference using a 2-transistor Self-Cascode MOSFET (SCM) structure able to get low power consumption, temperature compensation, and small area. An efficient design procedure applied to this simple topology relying on NMOS transistors with different threshold voltages allows attaining large immunity against bias current and supply voltage variations. The two transistors can operate in weak, moderate, or strong inversion making the design flexible in terms of area and power consumption. Implemented in a > 0.18mm standard CMOS technology, the circuit provides a 400mV voltage reference with a variation of ±0.18% from -20°C to 75°C (or less than 15ppm/°C), operates from 3.6V down to 800mV while biased with a 5nA resistor-less PTAT current source that varies ±30% over PVT, and consumes less than 20nA with an area of 0.01mm2. The same concept was used to create a temperature compensated voltage drop with regard to a monitored power supply voltage but using a 2-PMOS SCM structure with transistors of different threshold voltages. These two circuits were adopted as part of a Power Management (PM) system for RFID tag applications. The PM includes a LDO voltage regulator and a low voltage detector that require both the voltage reference and the low voltage monitor. The LDO regulated output voltage and the trip-point of the voltage detector vary +/-5.5% and +/-3.3%, respectively, over temperature, without trimming.

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3

Zhang, Xi, Tianshi Wang y Bocheng Bao. "A Detection Circuit for Improving the Unloading Transient Performance of the COT Controller". Electronics 10, n.º 19 (23 de septiembre de 2021): 2333. http://dx.doi.org/10.3390/electronics10192333.

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Fast load transient response and high light-load efficiency are two key features of the constant on-time (COT) control technique that has been widely used in numerous applications, such as for voltage regulators and point-of-load converters. However, when load step-down occurs during an on-time interval, the COT controller cannot respond until the COT interval expires. This delay causes an additional output voltage overshoot, resulting in unloading transient performance limitation. To eliminate the delay and improve the unloading transient response of the COT controller, a load step-down detection circuit is proposed based on capacitor current COT (CC-COT) control. In the detection circuit, the load step-down is monitored by comparing the measured capacitor current with the preset threshold voltage. Once the load step-down is monitored, the on-time is promptly truncated and the switch is turned off. With the proposed detection circuit, the CC-COT-controlled buck converter can monitor the load step-down without any delay and obtain less output voltage overshoot when the load step-down occurs during the on-time interval. PSIM circuit simulations are employed to demonstrate the feasibility of the detection circuit.

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4

Mehta, Nandish y Bharadwaj Amrutur. "Dynamic Supply and Threshold Voltage Scaling for CMOS Digital Circuits Using In-Situ Power Monitor". IEEE Transactions on Very Large Scale Integration (VLSI) Systems 20, n.º 5 (mayo de 2012): 892–901. http://dx.doi.org/10.1109/tvlsi.2011.2132765.

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5

Pejovic, Milic. "The gamma-ray irradiation sensitivity and dosimetric information instability of RADFET dosimeter". Nuclear Technology and Radiation Protection 28, n.º 4 (2013): 415–21. http://dx.doi.org/10.2298/ntrp1304415p.

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The gamma-ray irradiation sensitivity to radiation dose range from 0.5 Gy to 5 Gy and post-irradiation annealing at room and elevated temperatures have been studied for p-channel metal-oxide-semiconductor field effect transistors (also known as radiation sensitive field effect transistors or pMOS dosimeters) with gate oxide thicknesses of 400 nm and 1 mm. The gate biases during the irradiation were 0 and 5 V and 5 V during the annealing. The radiation and the post-irradiation sensitivity were followed by measuring the threshold voltage shift, which was determined by using transfer characteristics in saturation and reader circuit characteristics. The dependence of threshold voltage shift DVT on absorbed radiation dose D and annealing time was assessed. The results show that there is a linear dependence between DVT and D during irradiation, so that the sensitivity can be defined as DVT/D for the investigated dose interval. The annealing of irradiated metal-oxide-semiconductor field effect transistors at different temperatures ranging from room temperature up to 150?C was performed to monitor the dosimetric information loss. The results indicated that the dosimeters information is saved up to 600 hours at room temperature, whereas the annealing at 150?C leads to the complete loss of dosimetric information in the same period of time. The mechanisms responsible for the threshold voltage shift during the irradiation and the later annealing have been discussed also.

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6

Wang, Xiaoli, Haonan Zhou y Yong Song. "Infrared Infusion Monitor Based on Data Dimensionality Reduction and Logistics Classifier". Processes 8, n.º 4 (7 de abril de 2020): 437. http://dx.doi.org/10.3390/pr8040437.

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This paper presents an infrared infusion monitoring method based on data dimensionality reduction and a logistics classifier. In today’s social environment, nurses with hospital infusion work are under excessive pressure. In order to improve the information level of the traditional medical process, hospitals have introduced a variety of infusion monitoring devices. The current infusion monitoring equipment mainly adopts the detection method of infrared liquid drop detection to realize non-contact measurements. However, a large number of experiments have found that the traditional infrared detection method has the problems of low voltage signal amplitude variation and low signal-to-noise ratio (SNR). Conventional threshold judgment or signal shaping cannot accurately judge whether droplets exist or not, and complex signal processing circuits can greatly increase the cost and power consumption of equipment. In order to solve these problems, this paper proposes a method for the accurate measurement of droplets without increasing the cost, that is, a method combining data drop and a logistics classifier. The dimensionalized data and time information are input into the logistics classifier to judge the drop landing. The test results show that this method can significantly improve the accuracy of droplet judgment without increasing the hardware cost.

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7

Burghard, R. A. y Y. A. El-Mansy. "Depletion transistor threshold voltage as a process monitor". IEEE Transactions on Electron Devices 34, n.º 4 (abril de 1987): 940–42. http://dx.doi.org/10.1109/t-ed.1987.23023.

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8

Sahafi, A., J. Sobhi y Z. D. Koozekanani. "Pico Watt sub-threshold CMOS voltage reference circuit". IEICE Electronics Express 10, n.º 4 (2013): 20120945. http://dx.doi.org/10.1587/elex.10.20120945.

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9

Hu, Zhi Cheng, Zhi Hua Ning y Le Nian He. "A Low Temperature Coefficient, High Voltage Detection Circuit Used in Power over Ethernet". Advanced Materials Research 588-589 (noviembre de 2012): 839–42. http://dx.doi.org/10.4028/www.scientific.net/amr.588-589.839.

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A low temperature coefficient, high voltage detection circuit used in Power over Ethernet is proposed. This circuit realizes the detection comparison without utilizing an extra voltage reference circuit and comparator while the temperature coefficient of the threshold voltage is as low as that of a regular bandgap reference. The proposed detection circuit is implemented in CSMC 0.5μm 60V BCD process, Cadence Spectre simulation results show that the temperature coefficient of the threshold voltage is 66.5 ppm/°C over the temperature range of -40°C to 125°C, and the maximum variation of the threshold voltage is 2.7% under all corners.

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10

MANHAS, PARSHOTAM S. y K. PAL. "REALIZATION OF LOW-VOLTAGE DIFFERENTIAL VOLTAGE CURRENT CONVEYOR". Journal of Circuits, Systems and Computers 21, n.º 04 (junio de 2012): 1250031. http://dx.doi.org/10.1142/s0218126612500314.

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This paper presents floating gate MOSFET (FGMOS)-based second generation differential voltage current conveyor (DVCCII) at low voltage levels. In analog circuit design, the FGMOS transistors are very often used in low voltage circuits, where the reduction obtained in the transistor apparent threshold voltage is of great importance. The given circuit provides very high input impedance at its Y-terminals, low output impedance at X-terminal and high impedance at Z-terminals and consumes less power. This circuit is a powerful building block, especially for applications demanding differential or floating inputs. The circuit behavior has been verified using PSpice simulations for 0.5 μm technology and indicates the excellent performance.

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11

Thakral, Bindu, Arti Vaish y Rama Koteswara Rao Alla. "Design of Squarer Circuit in Sub-threshold Mode". International Journal of Engineering & Technology 7, n.º 2.11 (3 de abril de 2018): 38. http://dx.doi.org/10.14419/ijet.v7i2.11.11004.

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Historically, analog designs have been assumed as a voltage mode based signal processing. However, the necessity of high speed circuits operating at reduced supply voltage has lead to a development of new circuit topology referred as current-mode designs. For low power low voltage designs the applications using translinear principle based circuits has become an area of research and interest. It has wide application in nonlinear signal processing and to build basic active elements. Mode of MOS transistor used in analog circuit realization of is important parameter deciding the performance of the circuit. In this paper, a squarer circuit is proposed based on sub threshold-mode MOS transistors exhibiting the exponential current-voltage characteristic. The simulations have been performed on model files of TSMC 0.18 micrometer technology with the help of ELDO Simulator.

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12

Ferreira, Luís Henrique de Carvalho. "A low-voltage low-power threshold voltage monitor for CMOS process sensing". Analog Integrated Circuits and Signal Processing 68, n.º 1 (9 de diciembre de 2010): 51–57. http://dx.doi.org/10.1007/s10470-010-9572-7.

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13

HUANG-FU Lu-jiang, 皇甫鲁江, 郑灿 ZHENG Can, 李云飞 LI Yun-fei, 刘利宾 LIU Li-bin, 朱健超 ZHU Jian-chao y 陈义鹏 CHEN Yi-peng. "LTPS-TFT threshold voltage compensation pixel circuit for AMOLED". Chinese Journal of Liquid Crystals and Displays 32, n.º 8 (2017): 614–22. http://dx.doi.org/10.3788/yjyxs20173208.0614.

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14

Terada, Kazuo, Masatomo Eimitsu y Kouhei Fukeda. "A test circuit for measuring MOSFET threshold voltage mismatch". Solid-State Electronics 49, n.º 5 (mayo de 2005): 818–24. http://dx.doi.org/10.1016/j.sse.2005.01.024.

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15

Xu, Wei Jian y Tao Wu. "Design of Temperature Detection Alarm Circuit Based on Multisim". Applied Mechanics and Materials 457-458 (octubre de 2013): 1627–30. http://dx.doi.org/10.4028/www.scientific.net/amm.457-458.1627.

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This paper mainly describes the characteristics of the utilization of thermistor resistance changes with temperature. When temperature is too low or too high, the thermal resistance values change correspondingly. This causes its associating sensor voltage signal changes. The changes of the voltage signal will lead to the subtraction proportional operation and dual comparator threshold voltage change correspondingly. This appearance enables the double threshold voltage comparators output highly, so that the multivibrator starts emitting diode conduct. Therefore the alarm circuit works.

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16

Zhang, Yun Wu, Jing Zhu y Wei Feng Sun. "A Novel UVLO Circuit with Current-Mode Control Technique for DC-DC Converters". Advanced Materials Research 765-767 (septiembre de 2013): 2534–37. http://dx.doi.org/10.4028/www.scientific.net/amr.765-767.2534.

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A novel Under Voltage Lockout (UVLO) circuit featuring with fast response speed and low temperature coefficient threshold voltages is proposed in this paper. Compared with the conventional structure, the proposed circuit achieves the fast response ability thanks to the current-mode control technique is utilized. Meanwhile, this UVLO realizes hysteretic threshold by a feedback control path to improve the interference rejection capability. In addition, the threshold voltage varies slightly with the variation of the supply voltage and temperature by using a bandgap core. The proposed circuit implemented with 0.5μm BCD technology has an input high threshold voltage of 8.5V and a hysteresis of 1.5V, and start or shut off the power quickly. Test results verified that the proposed UVLO has the qualification to be applied to DC-DC converters.

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17

Fan, Ching-Lin, Hui-Lung Lai y Yan-Wei Liu. "An AMOLED AC-Biased Pixel Design Compensating the Threshold Voltage andI-RDrop". International Journal of Photoenergy 2011 (2011): 1–6. http://dx.doi.org/10.1155/2011/543273.

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We propose a novel pixel design and an AC bias driving method for active-matrix organic light-emitting diode (AM-OLED) displays using low-temperature polycrystalline silicon thin-film transistors (LTPS-TFTs). The proposed threshold voltage andI-Rdrop compensation circuit, which comprised three transistors and one capacitor, have been verified to supply uniform output current by simulation work using the Automatic Integrated Circuit Modeling Simulation Program with Integrated Circuit Emphasis (AIM-SPICE) simulator. The simulated results demonstrate excellent properties such as low error rate of OLED anode voltage variation (<0.7%) and low voltage drop ofVDDpower line. The proposed pixel circuit effectively enables threshold-voltage-deviation correction of driving TFT and compensates for the voltage drop ofVDDpower line using AC bias on OLED cathode.

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18

ANDREEV, BORIS, EDWARD L. TITLEBAUM y EBY G. FRIEDMAN. "SIZING CMOS INVERTERS WITH MILLER EFFECT AND THRESHOLD VOLTAGE VARIATIONS". Journal of Circuits, Systems and Computers 15, n.º 03 (junio de 2006): 437–54. http://dx.doi.org/10.1142/s0218126606003143.

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The maximum speed of synchronous circuits is generally constrained by the worst case propagation delay, which limits the system clock frequency. Various techniques exist to manage the circuit delay, trading off speed for other system resources. One such approach is to equalize the rise and fall delay times. The primary design parameter for equalizing these delay times is the ratio between the width of the PMOS and NMOS transistors, which determines the relationship between the currents passed along the pull-up and pull-down paths. The variation of the pull-up to pull-down ratio for different circuit parameters is discussed in this paper under the constraint of equal rise and fall delay times. It is shown that the short-circuit current and the Miller capacitance affect the ideal linear relationship between the CMOS inverter delay times and the load capacitance, requiring the pull-up to pull-down ratio to be adjusted as circuit parameters are varied. These effects are more pronounced in deep submicrometer technologies with significant parasitic MOSFET capacitances and threshold voltage variations. Based on analytic and experimental observations, circuit design guidelines are proposed to minimize the Miller effect.

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19

Kushwaha, Dinesh y D. K. Mishra. "Nano Power Current Reference Circuit consisting of Sub-threshold CMOS Circuits". Circulation in Computer Science 2, n.º 1 (24 de enero de 2017): 1–4. http://dx.doi.org/10.22632/ccs-2016-251-36.

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This paper proposes a low voltage CMOS Nano power current reference circuit and presents its performance with circuit simulation in 180- nm UMC CMOS technology. The proposed circuit consists of start-up, Bias-voltage, current-source sub-circuits with most of the MOSFETs operating in sub-threshold region. Simulation results shows that the circuit generates a stable reference current of 4-nA in supply voltage range 1 V- 1.8 V with line sensitivity of 0.203%/V.The temperature coefficient of the current was 7592ppm/°C at 1.8 V in the range of 0°C-100°C. The power dissipation was 380 NW at 1.8 V Supply. The proposed circuit would be suitable for use in sub-threshold –operated power-aware large-scale integration

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20

Huang, S., Peijun Liu, Quanzhen Duan, Yuemin Ding y Zhen Meng. "A −4–4 V Input Common-Mode Range Bidirectional Current Shunt Monitor". Journal of Circuits, Systems and Computers 29, n.º 14 (25 de marzo de 2020): 2050221. http://dx.doi.org/10.1142/s0218126620502217.

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This study describes a novel bidirectional current shunt monitor (CSM) circuit operating at both positive and negative common-mode (CM) voltages. The proposed CSM circuit mainly consists of two comparators, three error amplifiers, several current-mirror transistors and a few resistors. One comparator is used to detect current flowing direction, and the other one is utilized to ensure good operation of CSM circuit with both positive and negative CM voltages. The proposed CSM circuit has been implemented in SMIC 0.18[Formula: see text][Formula: see text]m standard CMOS process and its performances have been verified by simulations. The simulated results show that the proposed CSM circuit, at a supply voltage of 5[Formula: see text]V and with an input CM voltage range from [Formula: see text] to 4[Formula: see text]V, can sense a voltage difference of 4–40[Formula: see text]mV and keep a constant scaled gain of 100[Formula: see text]V/V. The gain error is less than 0.65% and the common-mode rejection ratio (CMRR) is higher than 130[Formula: see text]dB at 1[Formula: see text]kHz. Simulation results show that the output voltage of CSM circuit varies linearly with the CSM input sense voltage.

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21

Kim, Y. y H. Lee. "Voltage‐programmed AM‐OLED pixel circuit to compensate threshold voltage and mobility variations". Electronics Letters 49, n.º 13 (junio de 2013): 796–98. http://dx.doi.org/10.1049/el.2013.0735.

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22

Gong, Liang, Rui Ming Li, Qi Xiong y Shao Hua Zhou. "The Equivalent Circuit Model of Floating-Gate Single-Electron Memorizer". Applied Mechanics and Materials 416-417 (septiembre de 2013): 1721–25. http://dx.doi.org/10.4028/www.scientific.net/amm.416-417.1721.

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Based on the introduction of floating-gate silicon quantum dot single-electron memorizers structure and working principle, this paper builds corresponding lumping current and capacitance model to calculate the current with memory in the circumstance of linearity, saturation and sub-threshold. Taking advantage of the single-electron devices Threshold Voltage Shift educes different storage condition of nanostorage with different threshold voltage. The simulation shows, this model can precisely simulate memorys read and write state.

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23

Gupta, Maneesha, Richa Srivastava y Urvashi Singh. "Low Voltage Floating Gate MOS Transistor Based Differential Voltage Squarer". ISRN Electronics 2014 (9 de febrero de 2014): 1–6. http://dx.doi.org/10.1155/2014/357184.

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This paper presents novel floating gate MOSFET (FGMOS) based differential voltage squarer using FGMOS characteristics in saturation region. The proposed squarer is constructed by a simple FGMOS based squarer and linear differential voltage attenuator. The squarer part of the proposed circuit uses one of the inputs of two-input FGMOS transistor for threshold voltage cancellation so as to implement a perfect squarer function, and the differential voltage attenuator part acts as input stage so as to generate the differential signals. The proposed circuit provides a current output proportional to the square of the difference of two input voltages. The second order effect caused by parasitic capacitance and mobility degradation is discussed. The circuit has advantages such as low supply voltage, low power consumption, and low transistor count. Performance of the circuit is verified at ±0.75 V in TSMC 0.18 μm CMOS, BSIM3, and Level 49 technology by using Cadence Spectre simulator.

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24

Liu, Hai Bo y Yu Mei Wang. "Scheme of Protection and Monitor Underground High-Voltage Power Supply System Based on PROFINET". Applied Mechanics and Materials 668-669 (octubre de 2014): 741–44. http://dx.doi.org/10.4028/www.scientific.net/amm.668-669.741.

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Short circuit protection of high-voltage power lines in coal mine cannot realize selectivity with existing protection systems. To solve this problem, a scheme of protection and monitor underground based on PROFINET was proposed. The system is mainly composed of PROFINET network, monitor, controller, and integrated protector with PROFINET IO interface circuit. The system achieves protection and power monitoring network integration, completes the selectivity of short circuit protection, and can determine fault position quickly. Thus the troubleshooting time is cut and reliability of power supply network is improved. The simulation results show that the POROFINET real-time meets the requirement of protection and the system can realize short-circuit protection and power monitor function.

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25

Singhal, Sonal, Rohit Singh y Amit Kumar Singh. "Design of a Sub-0.4 V Reference Circuit in 0.18μm CMOS Technology". Advanced Materials Research 816-817 (septiembre de 2013): 882–86. http://dx.doi.org/10.4028/www.scientific.net/amr.816-817.882.

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This paper proposes a low power voltage reference generator in 0.18μm CMOS technology.The circuit presented here includes MOSFETs in sub threshold mode and uses the temperature dependence of threshold voltages and sub-threshold current of MOSFET to form a temperature-insensitive reference. An input supply voltage of 1.8 Volt is used for the circuit generating a total current of 1.33μA. By varying the device temperature over the range of-20°C to 100°C corresponding variation over the output voltage was found to lie in the range 397.8 to 400.2 mV. Thus a 0.6% variation in voltage over the considered range of temperature is obtained.

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26

Kim, Jin-Ho, Jongsu Oh, KeeChan Park y Yong-Sang Kim. "IGZO TFT gate driver circuit with large threshold voltage margin". Displays 53 (julio de 2018): 1–7. http://dx.doi.org/10.1016/j.displa.2018.03.003.

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27

Arnal, August, Carme Martínez-Domingo, Simon Ogier, Lluís Terés y Eloi Ramon. "Monotype Organic Dual Threshold Voltage Using Different OTFT Geometries". Crystals 9, n.º 7 (28 de junio de 2019): 333. http://dx.doi.org/10.3390/cryst9070333.

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It is well known that organic thin film transistor (OTFT) parameters can be shifted depending on the geometry of the device. In this work, we present two different transistor geometries, interdigitated and Corbino, which provide differences in the key parameters of devices such as threshold voltage (VT), although they share the same materials and fabrication procedure. Furthermore, it is proven that Corbino geometries are good candidates for saturation-mode current driven devices, as they provide higher ION/IOFF ratios. By taking advantage of these differences, circuit design can be improved and the proposed geometries are, therefore, particularly suited for the implementation of logic gates. The results demonstrate a high gain and low hysteresis organic monotype inverter circuit with full swing voltage at the output.

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28

Fu, Chao y Jing Hao. "High Voltage Circuit Breaker on-Line Monitoring System". Advanced Materials Research 898 (febrero de 2014): 668–71. http://dx.doi.org/10.4028/www.scientific.net/amr.898.668.

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The high voltage circuit breaker is an important power system equipment. The reliability of its running relationship with the safe operation of the entire power system. High voltage circuit breaker on-line monitoring system enables real-time monitoring of various parameters during the operation in which the circuit breaker, and the use of communication to achieve data transfer bus information. Through monitoring points, closing coil current signals to constitute the core of C8051F online monitoring unit via RS-485 serial bus will monitor information is uploaded to the master computer.

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29

Bae, Jina y Hyoungsik Nam. "Body-Effect-Free OLED-on-Silicon Pixel Circuit Based on Capacitive Division to Extend Data Voltage Range". Electronics 10, n.º 19 (26 de septiembre de 2021): 2351. http://dx.doi.org/10.3390/electronics10192351.

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This paper proposes an OLED pixel compensation circuit that copes with threshold voltage variation, narrow data voltage range, and body effect on a backplane of silicon-based transistors. It consists of six PMOS transistors and two capacitors. The data voltage range is extended by the capacitor division with two capacitors, and the connection of both source and gate nodes to the supply voltage makes the driving transistor free from the body effect. In addition, the reference voltage is used to initialize the gate node voltage of the driving transistor as well as to adjust the data voltage region. By the SPICE simulation, it is verified that the current error over the threshold voltage variations of ±10 mV is reduced to be −1.200% to 0.964% at the maximum current range of around 8 nA, and the data voltage range is extended to 3.4 V, compared to the large current error range from −21.46% to 27.36% and the data voltage range of 0.41 V in the basic 2T1C circuit. In addition, the body-effect-free circuit outperforms the latest 4T1C circuit of the current error range from −3.279% to 3.388%.

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30

Nagulapalli, R., K. Hayatleh, S. Barker, A. A. Tammam, P. Georgiou y F. J. Lidgey. "A 0.55 V Bandgap Reference with a 59 ppm/°C Temperature Coefficient". Journal of Circuits, Systems and Computers 28, n.º 07 (27 de junio de 2019): 1950120. http://dx.doi.org/10.1142/s0218126619501202.

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This paper presents a novel low power, low voltage CMOS bandgap reference (BGR) that overcomes the problems with the existing BJT-based reference circuits by using a MOS transistor operating in sub-threshold region. A proportional to absolute temperature (PTAT) voltage is generated by exploiting the self-bias cascode branch, while a Complementary to Absolute Temperature (CTAT) voltage is generated by using the threshold voltage of the transistor. The proposed circuit is implemented in 65[Formula: see text]nm CMOS technology. Post-layout simulation results show that the proposed circuit works with a supply voltage of 0.55[Formula: see text]V, and generates a 286[Formula: see text]mV reference voltage with a temperature coefficient of 59[Formula: see text]ppm/∘C. The circuit takes 413[Formula: see text]nA current from 0.55[Formula: see text]V supply and occupies 0.00986[Formula: see text]mm2 of active area.

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31

Sun, Wei Qiang y Shan Ren Nie. "A Threshold Speed Computation Algorithm in Adaptive DVS Scheduling". Applied Mechanics and Materials 519-520 (febrero de 2014): 1071–74. http://dx.doi.org/10.4028/www.scientific.net/amm.519-520.1071.

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Performance boosting of modern computing systems is constrained by the chip/circuit power dissipation. Dynamic voltage scaling (DVS) has been applied for reducing the energy consumption by dynamically changing the supply voltage. One can apply an adaptive scheme by computing a threshold speed of the supplied voltage, and adopting greedy online DVS scheduling algorithm when the voltage exceeds the threshold while choosing a conservative speed on the contrary. This paper presents an algorithm to determine the threshold speed. The proposed algorithm allows to obtaining the threshold speed for the adaptive DVS scheduling algorithm more efficiently.

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32

Wai, Rong Jong y Jun Jie Liaw. "Design of Clock and Ramp Generator Circuit Framework with 0.9V Low Operational Voltage". Applied Mechanics and Materials 284-287 (enero de 2013): 2502–8. http://dx.doi.org/10.4028/www.scientific.net/amm.284-287.2502.

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In this study, a new clock and ramp generator circuit framework with a 0.9V low operational voltage is designed for the voltage-mode/current-mode-controlled power management integrated chip of a DC-DC converter. In conventional clock and ramp generator circuit with operational amplifiers, its operational voltage is limited to be over 1.5V because of the problem of a higher threshold voltage in the metal-oxide-semiconductor field-effect transistor (MOSFET). As a result, it can not work well for a pulse-width-modulation DC-DC converter when a below 1V low-voltage single-cell clean-energy power source is applied. This newly-design clock and ramp generator circuit framework without operational amplifiers is investigated to cope with the limitation of the threshold voltage in the MOSFET. Therefore, the corresponding chip size and power consumption can be reduced. Moreover, this circuit still has the functions of adjustable clock frequency and ramp slope. In addition, numerical simulations by the HSPICE software and experimental results by a real chip fabricated in the TSMC 1P6M 0.18µm CMOS process are given to verify the effectiveness of the proposed circuit to produce the clock and ramp waveforms.

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33

WANG, YU, HUAZHONG YANG y HUI WANG. "SIGNAL-PATH-LEVEL DUAL-Vt ASSIGNMENT FOR LEAKAGE POWER REDUCTION". Journal of Circuits, Systems and Computers 15, n.º 02 (abril de 2006): 197–216. http://dx.doi.org/10.1142/s021812660600299x.

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Along with the fast development of dual-threshold voltage (dual-Vt) and multi-threshold technology, it is possible to use them to reduce static power in low-voltage high-performance circuits. In this paper, we propose a new method to realize CMOS digital circuits that are implemented with dual-Vt technology. We first present a new signal-path-level circuit model which effectively deals with the fact that there can be two threshold voltages assigned to a single gate. In order to assign proper threshold voltage to all the signal-paths in the circuit, our new algorithms introduce the concept of subcircuit extraction and include the hierarchy algorithms which are effective and fast. Experimental results show that our algorithms produce a significant reduction for the ISCAS85 benchmark circuits.

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34

Paul, P. John y Raj N. "Reliable Low Voltage Circuit Design Techniques". International Journal of Advanced Research in Engineering 3, n.º 4 (31 de diciembre de 2017): 32. http://dx.doi.org/10.24178/ijare.2017.3.4.32.

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In this paper, non-conventional circuit design techniques has been reviewed. The techniques discussed are widely used for realizing low voltage low power analog circuits. The discussed techniques in this paper are: Bulk Driven, Floating and Quasi-floating Gate followed by operating of Bulk Driven MOSFET in Floating and Quasi-floating Gate mode. In all the approach, the threshold voltage restriction is removed or reduced from the input signal path thereby reducing the power consumption. However, the adverse effect lies is terms of reduced performance parameters of MOSFET compared to conventional gate driven MOSFET parameters as shown in this paper through simulation results. The comparative analysis of MOSFET parameters results in encouragement of two approaches: Quasi-floating Gate and Bulk Driven Quasi-floating Gate MOSFET. Each of these approaches has its advantage in specific domains. Further in this paper, an Operational Transconductance Amplifier is proposed which use the Bulk Driven Quasi-floating Gate MOSFET technique and the same is amplifier under similar conditions is also realized using Bulk Driven MOSFET so as to highlight the advantage of Bulk Driven Quasi-floating Gate MOSFET over Bulk Driven MOSFET. All the performances metrics are achieved with the help of HSpice simulator using MOSFET models of 180nm technology provided by UMC.

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35

Ramasamy, S., B. Venkataramani y P. Meenatchisundaram. "A low power CMOS voltage reference circuit with sub threshold MOSFETs". International Journal of Information and Communication Technology 2, n.º 1/2 (2009): 94. http://dx.doi.org/10.1504/ijict.2009.026433.

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36

Huang, Xiaoming, Guang Yu y Chenfei Wu. "IGZO TFT-based circuit with tunable threshold voltage by laser annealing". Superlattices and Microstructures 111 (noviembre de 2017): 1172–76. http://dx.doi.org/10.1016/j.spmi.2017.08.027.

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37

Kushwah, Preeti, Saurabh Khandelwal y Shyam Akashe. "Multi-Threshold Voltage CMOS Design for Low-Power Half Adder Circuit". International Journal of Nanoscience 14, n.º 05n06 (octubre de 2015): 1550022. http://dx.doi.org/10.1142/s0219581x15500222.

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The new era of portable electronic devices demands lesser power dissipation for longer battery life and design compactability. Leakage current and leakage power are dominating factors which greatly affect the power consumption in low voltage and low power applications. For many numerical representations of binary numbers, combinational circuits like adder, encoder, multiplexer, etc. are useful circuits for arithmetic operation. A novel high speed and low power half adder cell is introduced here which consists of AND gate and OR gate. This cell shows high speed, lower power consumption than conventional half adder. In CMOS technology, transistors used have small area and low power consumption. It is used in various applications like adder, subtract or, multiplexer, ALU and microprocessors digital VLSI systems. As the scaling technology reduces, the leakage power increases. In this paper, multi threshold complementary metal oxide semiconductor (MTCMOS) technique is proposed to reduce the leakage current and leakage power. MTCMOS is an effective circuit level technique that increases the performance of a cell by using both low- and high-threshold voltage transistors. Leakage current is reduced by 85.37% and leakage power is reduced by 87.45% using MTCMOS technique as compared to standard CMOS technique. The half adder design simulation work was performed by cadence simulation tool at 45-nm technology.

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38

Liu, Peng Peng, Fang Yao, Zhi Gang Li y Yan Yan Luo. "Research on Voltage and Current Monitoring System for Circuit Breaker". Applied Mechanics and Materials 392 (septiembre de 2013): 389–93. http://dx.doi.org/10.4028/www.scientific.net/amm.392.389.

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This article develops the automatic test system of voltage and current dynamic waveform for circuit breaker. The system has the automatic monitoring, the storage and the display function of contact voltage and current waveform of circuit breaker in switching process. And then, it also designs the hardware and software of voltage and current dynamic monitoring system for miniature circuit breaker: the hardware circuit of this test system mainly consists of the detection circuit and the data acquisition circuit of current and voltage. And the software system, which mainly consists of control program, data acquisition program and data processing program, is programmed under the condition of LabVIEW. At last, it carries on the real-time monitor to the voltage and current waveform at the both ends of the circuit breaker, especially for the waveform during the switching process, which contributes to study the arc energy and contact wear of circuit breaker.

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39

Mitrović, Nikola, Danijel Danković, Zoran Prijić y Ninoslav Stojadinović. "Modeling of NBTI degradation in p-channel VDMOSFETs". Journal of Applied Engineering Science 18, n.º 4 (2020): 515–19. http://dx.doi.org/10.5937/jaes0-26760.

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This paper gives insight in reliability of p-channel VDMOSFET power transistors subjected to NBT stressing. Effects that lead to degradation of characteristics of these electronic circuits are presented, out of which threshold voltage shift with NBT stressing is further analysed. Measurements have been done and experimental results of the threshold voltage degradation of power transistors IRF9520 caused by different types of negative bias temperature stressing are shown. Stressing types, both static and pulsed, and their impact on transistors, especially on threshold voltage shifts have been explained in more details. An elementary equivalent electrical circuit is designed and proposed with the goal to model impact of both types of stressing, and also to calculate and estimate reliability of the circuit under specified stress. All of the elements of the modeling circuit and their dependencies are explained. Example of modeling from the experimental data is given together with the comparison between measured and modeled results. Differences between obtained results are discussed.

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40

Cai, Zhikuang y Chao Chen. "A 0.6 V temperature-stable CMOS voltage reference circuit with sub-threshold voltage compensation technique". IEICE Electronics Express 15, n.º 18 (2018): 20180760. http://dx.doi.org/10.1587/elex.15.20180760.

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41

Gong, Shu Qiu, Ming Tang y Li Yan Cui. "Analysis and Design of IGBT Driving and Protection Circuit for Photovoltaic Grid-Connected Inverter". Applied Mechanics and Materials 130-134 (octubre de 2011): 4118–21. http://dx.doi.org/10.4028/www.scientific.net/amm.130-134.4118.

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For the characteristics of high frequency of switching devices in the photovoltaic inverter and complexity of circuit topology, the insulated gate bipolar transistor driving protection circuit is designed which is suitable for photovoltaic inverter. The circuit which is based on thick film structure of M57962L has isolated power supply and threshold voltage regulator circuits. The control and regulation can be achieved precisely for the threshold voltage of over current protection. The internal structure of M57962L has been analyzed here. The process of slow turn off action is observed practically. For the circuit periphery parameters of M57962L, the general calculation methods are given according to various models and the level of protection for IGBT. The practical application shows that the method is correct and effective.

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42

Ghavami, Behnam. "Spatial correlation-aware statistical dual-threshold voltage design of template-based asynchronous circuits". COMPEL - The international journal for computation and mathematics in electrical and electronic engineering 37, n.º 3 (8 de mayo de 2018): 1189–203. http://dx.doi.org/10.1108/compel-03-2016-0118.

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Purpose Power consumption is a top priority in high-performance asynchronous circuit design today. The purpose of this study is to provide a spatial correlation-aware statistical dual-threshold voltage design method for low-power design of template-based asynchronous circuits. Design/methodology/approach In this paper, the authors proposed a statistical dual-threshold voltage design of template-based asynchronous circuits considering process variations with spatial correlation. The utilized circuit model is an extended Timed Petri-Net which captures the dynamic behavior of the asynchronous circuit with statistical delay and power values. To have a more comprehensive framework, the authors model the spatial correlation information of the circuit. The authors applied a genetic optimization algorithm that uses a two-dimensional graph to calculate the power and performance of each threshold voltage assignment. Findings Experimental results show that using this statistically aware optimization, leakage power of asynchronous circuits can be reduced up to 3X. The authors also show that the spatial correlation may lead to large errors if not being considered in the design of dual-threshold-voltage asynchronous circuits. Originality/value The proposed framework is the scheme giving a low-power design of asynchronous circuits compared to other schemes. The comparison exhibits that the proposed method has better results in terms of performance and power. To consider the process variations with spatial correlation, the authors apply the principle component analysis method to transform the correlated variables into uncorrelated ones.

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43

Ni, Ping Hao y Wei Wang. "Research on an Online Monitoring and Diagnosis System of High-Voltage Circuit Breaker". Applied Mechanics and Materials 492 (enero de 2014): 212–17. http://dx.doi.org/10.4028/www.scientific.net/amm.492.212.

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The principle of an online monitoring and diagnosis system suitable for various kinds of High-voltage Circuit Breakers (HVCB) is presented in the paper. The system consists of distributed data acquisition devices, a communication system based on field bus, and a host based on B/S structure. The research presents the methods to select the main monitoring signals of high-voltage circuit breakers, to acquire data, and to calculate operational feature values, as well as realizes high-speed process to monitoring signals, valid online monitor to high-voltage circuit breakers, and fault diagnosis.

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44

Raikwal, P., V. Neema y A. Verma. "A New 8T SRAM Circuit with Low Leakage and High Data Stability Idle Mode at 70nm Technology". Oriental journal of computer science and technology 10, n.º 1 (22 de marzo de 2017): 86–93. http://dx.doi.org/10.13005/ojcst/10.01.12.

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Memory has been facing several problems in which the leakage current is the most severe. Many techniques have been proposed to withstand leakage control such as power gating and ground gating. In this paper a new 8T SRAM cell, which adopts a single bit line scheme has been proposed to limit the leakage current as well as to gain high hold static noise margin. The proposed cell with low threshold voltage, high threshold voltage and dual threshold voltage are used to effectively reduce leakage current, and delay. Additionally, the comparison has been performed between conventional 6T SRAM cell and the new 8T SRAM cell. The proposed circuit consumes 671.22 pA leakage current during idle state of the circuit which is very less as compare to conventional 6T SRAM cell with sleep and hold transistors and with different β ratio. The proposed new 8T SRAM cell shows highest noise immunity 0.329mv during hold state. Furthermore, the proposed new 8T SRAM circuit represents minimum read and write access delays 114.13ps and 38.56ps respectively as compare to conventional 6T SRAM cell with different threshold voltages and β ratio.

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45

McMillan, J. E. "A remote monitor circuit for measuring photomultiplier anode current at high voltage". Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment 562, n.º 1 (junio de 2006): 418–21. http://dx.doi.org/10.1016/j.nima.2006.02.171.

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46

Wang, Zhi Ping, Ai Dong Xu, Yan Song y Bing Jun Yan. "Design and Develop of Functional Safety Temperature Transmitter for Fault Status". Applied Mechanics and Materials 385-386 (agosto de 2013): 1272–77. http://dx.doi.org/10.4028/www.scientific.net/amm.385-386.1272.

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According to the requirements of the functional safety temperature transmitter high reliability, this paper selects the micro-power voltage reference, the reset monitor, the D-type flip-flop and the OR gate to design the functional safety temperature transmitter protection circuit for fault status. The protection circuit takes power from the data line of HART fieldbus by micro-power voltage references. According to the control signal of the functional safety transmitter, the protection circuit utilizes the state latch of D-type flip-flop, and realizes the functional safety temperature transmitter protection circuit for fault status.

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47

SWARTZ, ROBERT G. y YUSUKE OTA. "INTEGRATED ADAPTIVE THRESHOLD BURST MODE RECEIVERS FOR OPTICAL DATA LINKS—AN ANALYSIS". International Journal of High Speed Electronics and Systems 06, n.º 02 (junio de 1995): 375–94. http://dx.doi.org/10.1142/s0129156495000109.

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This paper provides a detailed analysis of the principles of the adaptive threshold, burst mode receiver circuit, covering architectures for both current and voltage input modes. In it we derive the circuit’s fundamental operating equations, and look at steady-state and dynamic stability issues. The paper also describes techniques for active threshold reset, and reviews factors affecting performance of the circuit over temperature.

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48

Yu, Zhi Qiang y Xing Wang. "Analysis of the Unexpected Opening of ABB Circuit-Breaker Opening under 30% Control Voltage". Advanced Materials Research 1003 (julio de 2014): 160–64. http://dx.doi.org/10.4028/www.scientific.net/amr.1003.160.

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The test data of circuit-breaker operating characteristics is important parameter to monitor the circuit-breaker. The unexpected opening of ABB HPL Series circuit-breaker under 30% control voltage in the recent operating characteristics in Shenzhen is analysed in this paper .The root cause of failure is identified. Two solutions are proposed: adjust the gap between coil and armature and replace the trip coil “open”, to eliminate such failures, ensure the safe and reliable operation of the circuit breaker.

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49

Li, Xue Qing, Anup Bhalla y Petre Alexandrov. "Short-Circuit Capability of SiC Cascode". Materials Science Forum 924 (junio de 2018): 871–74. http://dx.doi.org/10.4028/www.scientific.net/msf.924.871.

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This work investigates the short-circuit capability of SiC cascode by performing two-dimensional electro-thermal TCAD simulations. The effects of the threshold voltage of the SiC JFET on the cascode short-circuit withstand time are studied. A design trade-off between the JFET specific-on resistance and the cascode short-circuit withstand time is determined. The experimental results are also presented.

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50

Li, Bao Shu, Shang Chen, Xian Ping Zhao y Wei Hua Niu. "Monitoring the Travel Characteristics of High Voltage Circuit Breaker Based on TLD". Applied Mechanics and Materials 687-691 (noviembre de 2014): 938–41. http://dx.doi.org/10.4028/www.scientific.net/amm.687-691.938.

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For the circuit breaker, mechanical fault make up the largest share of the fault. In order to ensure reliable and secure power system can run,it is necessary to monitor the mechanical properties of the circuit breaker,which includes monitoring the breaker trip.By TLD video tracking technology ZN65-12 vacuum circuit breaker mechanical properties were measured,obtain a two-dimensional direction of travel, speed characteristic curves.The experimental results show that the error of the method used to obtain a circuit breaker stroke, speed and other parameters of not more than 1mm,compared with traditional methods of measurement can get richer information.

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