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Littérature scientifique sur le sujet « Current Steering DAC »

Auteur : Grafiati

Publié le 4 juin 2021

Mis à jour le 25 avril 2022

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Articles de revues sur le sujet "Current Steering DAC"

Dai, Lan, Guo Zhi Xu et Ke Qing Ning. « Dynamic-Performance-Improved Algorithm for 14 Bits 200MHz Current-Steering DAC ». Applied Mechanics and Materials 380-384 (août 2013) : 1721–24. http://dx.doi.org/10.4028/www.scientific.net/amm.380-384.1721.

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Performance of high-speed and high-resolution current-steering DAC is hardly suffered from non-ideal factors such as current-steering source mismatches. This paper presents a dynamic performance improved algorithm for current sources selection of current-steering DAC, the most attractive features of the algorithm are random direction and random origination address during current sources selection. The simulation results show this algorithm enhances randomness during current sources selection and exhibits better dynamic performance than many other methods.

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Patel, Jayeshkumar J., et Amisha P. Naik. « Design and implementation of 4 bit binary weighted current steering DAC ». International Journal of Electrical and Computer Engineering (IJECE) 10, n^o 6 (1 décembre 2020) : 5642. http://dx.doi.org/10.11591/ijece.v10i6.pp5642-5649.

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A compact current-mode Digital-to-Analog converter (DAC) suitable for biomedical application is repesented in this paper .The designed DAC is binary weighted in 180nm CMOS technology with 1.8V supply voltage. In this implementation, authors have focused on calculaton of Non linearity error say INL and DNL for 4 bit DAC having various type of switches: NMOS, PMOS and Transmission Gate. The implemented DAC uses lower area and power compared to unary architecture due to absence of digital decoders. The desired value of Integrated non linearity (INL) and Differential non linearity (DNL) for DAC for are within a range of +0.5LSB. Result obtained in this works for INL and DNL for the case DAC using Transmission Gate is +0.34LSB and +0.38 LSB respectively with 22mW power dissipation.

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Zurita, Marcos E. P. V., Loick Le Guevel, Gerard Billiot, Adrien Morel, Xavier Jehl, Aloysius G. M. Jansen et Gael Pillonnet. « Cryogenic Current Steering DAC With Mitigated Variability ». IEEE Solid-State Circuits Letters 3 (2020) : 254–57. http://dx.doi.org/10.1109/lssc.2020.3013443.

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XIA, FAN, YIQIANG ZHAO et GONGYUAN ZHAO. « A 12-bit 200-MHz CURRENT-STEERING DAC WITH CALIBRATION ». Journal of Circuits, Systems and Computers 23, n^o 04 (avril 2014) : 1450053. http://dx.doi.org/10.1142/s0218126614500534.

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In this paper, a 12-bit current-steering digital-to-analog converter (DAC) with high static and dynamic linearity is proposed. Compared to traditional intrinsic-accuracy DACs, the static linearity is obtained by a series of subsidiary DACs which can shorten the calibration cycle with smaller additional circuits. The presented DAC is based on the segmented architecture and layout has been carefully designed so that better synchronization among the current sources can be achieved. The DAC is implemented in a standard 0.18-μm CMOS technology and the current source block occupies less than 0.5 mm2. The measured differential nonlinearity (DNL) and integral nonlinearity (INL) performance is ± 0.3 LSB and ± 0.5 LSB, respectively, and the spurious free dynamic range (SFDR) is 75 dB at 1 MHz signal frequency and 200 MHz sampling frequency.

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Mathurkar, Piyush K. « CMOS 8-Bit Binary Type Current-Steering DAC ». International Journal of Embedded Systems and Applications 2, n^o 3 (30 septembre 2012) : 67–74. http://dx.doi.org/10.5121/ijesa.2012.2307.

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Shimizu, Akio, Takuro Noguchi, Yohei Ishikawa et Sumio Fukai. « Current-Steering DAC for Urinary Bladder Volume Measurement ». IEEJ Transactions on Electronics, Information and Systems 139, n^o 5 (1 mai 2019) : 632–33. http://dx.doi.org/10.1541/ieejeiss.139.632.

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Rekha, P., et N. Vijayanandam. « High Resolution Display Systems Using Current-Steering DAC ». i-manager's Journal on Electronics Engineering 4, n^o 2 (15 février 2014) : 28–33. http://dx.doi.org/10.26634/jele.4.2.2623.

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Tafir Mustaffa, Mohd, Yong Cheng Lim et Choon Yan Teh. « Current Steering Digital Analog Converter with Partial Binary Tree Network (PBTN) ». Indonesian Journal of Electrical Engineering and Computer Science 5, n^o 3 (1 mars 2017) : 643. http://dx.doi.org/10.11591/ijeecs.v5.i3.pp643-649.

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DACs are essential devices in many digital systems which require high performance data converters. Thus, shrinking of supply voltage, budget constraints of test times, and rising bandwidth requirement causing DAC architectures to highly relying on matched components to perform data conversions. However, matched components are nearly impossible to fabricate; there are always mismatch errors which causes the difference between the designed and actual component value. Dynamic Element Matching (DEM) is one of the techniques that are commonly used to reduce component mismatch error. This technique is a randomization technique to select one of the appropriate codes for each of the digital input value before entering DAC block. Thus, in this research, a new DEM algorithm is proposed on Current-Steering DAC with Partial Binary Tree Network (PBTN) algorithm that utilizes a lower complexity circuit to produce output signals with less glitches. Simulation results for 6-bit 1-MSB PBTN DAC produces 0.3184LSB of DNL, 0.0062LSB of INL, and a power consumption of 14.13 mW, while using only 126 transmission gates.

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Li, Weng Yuan, et Teng Xiao Jiang. « A 4-Bit 5 GS/s Current Steering DAC Integrated Circuit ». Applied Mechanics and Materials 513-517 (février 2014) : 4555–58. http://dx.doi.org/10.4028/www.scientific.net/amm.513-517.4555.

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In order to satisfy the higher and higher transmission rate and broadband requirement of modern communication, a 4-bit 5 GS/s digital-to-analog converter (DAC) integrated circuit is presented. The DAC circuit is based on current steering architecture and segmented with a 4 bit unary. The circuit is designed and analyzed in TSMC 0.18 μm CMOS technology. The chip size is 0.675 mm 0.525 mm. Simulation results show that the maximum integral nonlinearity (INL) is 0.15 LSB. The DAC can achieve a spurious-free dynamic range (SFDR) of 22.76 dB under a clock frequency of 5 GHz with an input signal frequency of 250 MHz, while the power consumption is 11.6 mW.

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Bramburger, Stefan, et Dirk Killat. « 10-bit tracking ADC with a multi-bit quantizer, variable step size and segmented current-steering DAC ». Advances in Radio Science 17 (19 septembre 2019) : 161–67. http://dx.doi.org/10.5194/ars-17-161-2019.

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Abstract. This paper presents a 10-bit tracking ADC using a multi-bit quantiser and a segmented current-steering DAC. The quantiser allows a dynamical adjustment of the step size dependent on the input signal waveform. This mitigates the limited slew rate of delta encoded ADCs. Energy consumption induced by 1 LSB ripple is removed by the quantiser. The segmented current-steering DAC allows simple control, good monotonicity and improved transient response when compared to previous design as well as potential power reduction.

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Thèses sur le sujet "Current Steering DAC"

Su, Chao. « Dynamic calibration of current-steering DAC ». [Ames, Iowa : Iowa State University], 2007.

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Moody, Tyler J. « Design of a 10-bit 1.2 GS/s Digital-to-Analog Converter in 90 nm CMOS ». Wright State University / OhioLINK, 2015. http://rave.ohiolink.edu/etdc/view?acc_num=wright1440063577.

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Majid, Abdul, et Abdul Waheed Malik. « Design and Implementation of a Direct Digital Frequency Synthesizer using Sum of Weighted Bit Products ». Thesis, Department of Electrical Engineering, 2009. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-19986.

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Direct Digital Frequency Synthesis (DDFS) is a method of producing an analog waveform by

generating a time-varying signal in digital form, succeeded by digital-to-analog reconstruction.

At behavioral level the bit products with specified weights are used to generate the sine wave. In representation of a sine wave both positive and negative weights are generated. Since negative weights are not desired in design, the negative weights are transformed to positive weights. To reduce the number of current sources and control signals, bit product signals of those current sources which cannot be switched on simultaneously and have equal weights are shared. After sharing weights, the control signals are reduced to from 59 to 43 and current sources from 207 to 145.

Different control words are used by the DDFS system in order to generate different frequencies. The control word is successively added to the previous value in a 20-bit accumulator. Nine most significant bits out of these twenty bits are used for the DAC.

Since the Current Steering DAC architecture is suitable for high speed and high resolution purposes, so a 9-bit nonlinear current steering DAC is used to convert the output of bit products to the analog sine wave. Seven bits are used to generate one quarter of the sine wave. Eighth and ninth bits are used to generate the full sine wave.

HCMOS 9 (130 nm) ST Microelectronics process is used by employing high speed NMOS and PMOS transistors. The bit products (control signals) are computed by using complementary static CMOS logic which then act as control signals for the current sources after passing through D-flip flops. Practical design issues of current sources and parts of digital logic were studied and implemented using the Cadence full-custom design environment.

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Warecki, Sylwester. « Behavioral simulation of digital to analog converters simulation of segmented current steering DAC with utilization of perfect sampling technique ». Diss., The University of Arizona, 2003. http://hdl.handle.net/10150/280331.

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Rapid progress in telecommunication and introduction of wireless phones has revolutionized the way, in which the analog signal is treated. High Radio Frequency (RF) pollution caused by increased number of subscribers imposes new requirements on the quality of transmitted RF signal. These requirements are met by introduction of Digital Direct Synthesis (DDS) of Intermediate Frequency (IF). The DDS eliminates the analog IF mixing stage, which is responsible interference with modulated signal. The high accuracy of DDS modulation is possible only with high quality digital-to-analog conversion. The design of Digital-to-Analog Converters (DAC) providing high-speed and high-resolution is extremely difficult. To overcome problems caused by manufacturing process variation numerous techniques such as thermometer coding or calibration are utilized in DAC design. However, in many cases implementation of these techniques becomes a source of new problems such as clock jitter or glitch. To solve them simulation of DAC, depicting numerous effects of physical phenomena, is an absolute necessity. Unfortunately such simulation with utilization of off-the-shelf mixed signal simulators is very demanding. Therefore simulation of all DAC circuit becomes impractical due to long simulation time or lack of good models of still studied phenomena such as glitch. A novel method allowing for simultaneous and accurate representation of numerous phenomena and significantly increasing simulation speed is proposed. The method is called a Perfect Sampling Technique (PST) and it allows for precise calculation of most important in telecommunication dynamic DAC performance metric---the Spurious Free Dynamic Range (SFDR). The technique was primarily built to overcome the deficiencies of popular Discrete Fourier Transform (DFT). This novel approach allows for concurrent simulation of the following phenomena: deterministic and random clock jitter, random and graded current source mismatch, and the glitch and output finite impedance. The implemented in Visual C++ simulator provides means of representation of various DAC structures: segmentation (thermometer and binary coding), 2D layout of current source matrix and analog switch dynamic characteristics. It utilizes behavioral models of DAC building blocks (analog switches) in custom-built extremely fast event driven simulation framework. It also provides means for parametric, statistical, transient and spectral analysis of DAC.

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Ebrahimi, Mehr Golnaz. « Design of a Rom-Less Direct Digital Frequency Synthesizer in 65nm CMOS Technology ». Thesis, Linköpings universitet, Elektroniska komponenter, 2013. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-91680.

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A 4 bit, Rom-Less Direct Digital Frequency Synthesizer (DDFS) is designed in 65nm CMOS technology. Interleaving with Return-to-Zero (RTZ) technique is used to increase the output bandwidth and synthesized frequencies. The performance of the designed synthesizer is evaluated using Cadence Virtuoso design tool. With 3.2 GHz sampling frequency, the DDFS achieves the spurious-free dynamic range (SFDR) of 60 dB to 58 dB for synthesized frequencies between 200 MHz to 1.6 GHz. With 6.4 GHz sampling frequency, the synthesizer achieves the SFDR of 46 dB to 40 dB for synthesized frequencies between 400 MHz to 3.2 GHz. The power consumption is 80 mW for the designed mixed-signal blocks.

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Bertondini, Giulio. « Progetto di un sistema di misura integrato per la calibrazione statica di un Current-Steering RF-DAC a 14 bit in tecnologia FinFET ». Master's thesis, Alma Mater Studiorum - Università di Bologna, 2020. http://amslaurea.unibo.it/19822/.

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Il presente lavoro di tesi, svolto nel corso di 6 mesi di tirocinio presso Xilinx Irlanda, è focalizzato sullo studio e calibrazione degli effetti introdotti dalle non-idealità di tipo statico presenti nei convertitori digitale-analogici (Digital to Analog Converter: DAC) a radio frequenza con architettura Current-Steering, basata su un insieme di generatori di corrente con segmentazione mista termometrica e binaria: 14 bit binari suddivisi in 8 LSB binari e 6 MSB binari convertiti in 63 bit termometrici. Le non-idealità statiche includono i mismatch dei generatori e un gradiente di processo che condiziona fortemente il valore delle correnti dei generatori. Questo porta ad avere problemi di distorsione armonica nel segnale analogico generato dal DAC. Sono stati implementati e simulati, in Verilog-A, algoritmi per la riduzione della distorsione utilizzando dapprima i valori di corrente dei generatori forniti da un modello Verilog-A del DAC. In realtà, su silicio, queste correnti devono essere misurate con precisione con un sistema di misura. È stato quindi progettato, utilizzando librerie FinFET TSMC (Taiwan Semiconductor Manufacturing Company) in Cadence Virtuoso, un sistema di misura integrato che consente di misurare le correnti di tutti i 63 generatori termometrici del valore nominale di 500uA, con una precisione di circa 50nA, impiegando un tempo di alcune decine di ms e consentendo in questo modo la calibrazione del DAC. Infine sono stati modificati gli algoritmi precedentemente introdotti nel modello del DAC, inserendo degli opportuni coefficienti legati alla precisione di misura del sistema progettato, ottenendo risultati molto positivi in cui si nota l'efficacia del sistema di misura e della calibrazione del DAC in situazioni realistiche.

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Marzocchi, Achille. « Time Interleaved DAC : Analisi delle non idealità dell'architettura e progetto di un sistema di misura del clock differenziale in tecnologia FinFET a 7nm ». Master's thesis, Alma Mater Studiorum - Università di Bologna, 2021. http://amslaurea.unibo.it/24108/.

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Lo sviluppo di nuove architetture di convertitori digitale-analogico in grado di operare a radio frequenza comporta nuove sfide e problematiche di cui è necessario che i progettisti tengano conto in fase di design. Il presente lavoro di ricerca, svolto nel corso di 9 mesi di tirocinio presso Xilinx, è focalizzato sullo studio delle non linearità e l’analisi delle prestazioni dell’architettura Two Folded Time Interleaved DAC implementata mediante l’utilizzo di due convertitori Current Steering DAC a 16bit operanti alla frequenza di 10GHz. A tale proposito è stato creato in ambiente Cadence Virtuoso un modello VerilogA dell’architettura che consente di simulare le non idealità statiche e dinamiche e di misurarne l’effetto sulle performance del circuito. Le analisi effettuate hanno dimostrato che uno scostamento del duty cycle del clock del convertitore di appena 100fs dal valore di riferimento comporti il peggioramento del SFDR del segnale di uscita a circa -54 dBc, risultato non accettabile per la maggior parte delle applicazioni in campo wireless. Metodi di calibrazione e correzione delle non idealità, tra cui il segnale di clock, sono quindi necessari per ottenere prestazioni accettabili per il mercato. Lo studio si è quindi posto l’obiettivo di progettare un sistema di misurazione delle non idealità temporali del clock al fine di fornire uno strumento di calibrazione del TIDAC. Nello specifico, è stato progettato un sistema di misura del clock in tecnologia FinFET TSMC a 7nm in grado di garantire che il duty cycle del clock differenziale del TIDAC sia del 50%. Si è poi verificato con opportune simulazioni che il sistema di misura è in grado di misurare lo skew e differenze di duty cycle tra le due fasi del clock con un errore di massimo 45fs e di misurare il duty cycle di ogni singola fase seguendo un approccio robusto a mismatch ed offset del sistema di misura.

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McDonnell, Samantha. « Compensation and Calibration Techniques for High Performance Current-Steering DACs ». The Ohio State University, 2016. http://rave.ohiolink.edu/etdc/view?acc_num=osu1468060900.

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Andersson, Ola. « Modeling and Implementation of Current-Steering Digital-to-Analog Converters ». Doctoral thesis, Linköpings universitet, Elektroniksystem, 2005. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-5062.

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Data converters, i.e., analog-to-digital converters (ADCs) and digital-to-analog converters (DACs), are interface circuits between the analog and digital domains. They are used in, e.g., digital audio applications, data communication applications, and other types of applications where conversion between analog and digital signal representation is required. This work covers different aspects related to modeling, error correction, and implementation of DACs for communication applications where the requirements on the circuits in terms of speed and linearity are hard. The DAC architecture considered in this work is the current-steering DAC, which is the most commonly used architecture for high-speed applications. Transistor-level simulation of complex circuits using accurate transistor models require long simulation times. A transistor-level model of a DAC used in a system simulation is likely to be a severe bottleneck limiting the overall system simulation speed. Moreover, investigations of stochastic parameter variations require multiple simulation runs with different parameter values making transistor-level models unsuitable. Therefore, there is a need for behavioral-level models with reasonably short simulation times. Behavioral-level models can also be used to find the requirements on different building blocks on high abstraction levels, enabling the use of efficient topdown design methodologies. Models of different nonideal properties in current-steering DACs are used and developed in this work. Static errors typically dominates the low-frequency behavior of the DAC. One of the limiting factors for the static linearity of a current-steering DAC is mismatch between current sources. A well-known model of this problem is used extensively in this work for evaluation of different ideas and techniques for linearity enhancement. The highfrequency behavior of the DAC is typically dominated by dynamic errors. Models oftwo types of dynamic errors are developed in this work. These are the dynamic errors caused by parasitic capacitance in wires and transistors and glitches caused by asymmetry in the settling behavior of a current source. The encoding used for the digital control word in a current steering DAC has a large influence on the circuit performance, e.g., in terms static linearity and glitches. In this work, two DAC architectures are developed. These are denoted the decomposed and partially decomposed architectures and utilize encoding strategies aiming at a high circuit performance by avoiding unnecessary switching of current sources. The developed architectures are compared with the well-known binary-weighted and segmented architectures using behavioral-level simulations. It can be hard to meet a DAC design specification using a straightforward implementation. Techniques for compensation of errors that can be applied to improve the DAC linearity are studied. The well-known dynamic element matching (DEM) techniques are used for transforming spurious tones caused by matching errors into white or shaped noise. An overview of these techniques are given in this work and a DEM technique for the decomposed DAC architecture is developed. In DS modulation, feedback of the quantization error is utilized to spectrally shape the quantization noise to reduce its power within the signal band. A technique based on this principle is developed for spectral shaping of DAC nonlinearity errors utilizing a DAC model in a feedback loop. Two examples of utilization of the technique are given. Four different current-steering DACs implemented in CMOS technology are developed to enable comparison between behavioral-level simulations and measurements on actual implementations and to provide platforms for evaluation of different techniques for linearity improvement. For example, a 14-bit DEM DAC is implemented and measurement results are compared with simulation results. A good agreement between measured and simulated results is obtained. Moreover, a configurable 12-bit DAC capable of operating with different degrees of segmentation and decomposition is implemented to evaluate the proposed decomposed architecture. Measurement results agree with results from behavioral-level simulations and indicate that the decomposed architecture is a viable alternative to the commonly used segmented architecture.

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Balasubramanian, Sidharth. « STUDIES ON HIGH-SPEED DIGITAL-TO-ANALOG CONVERSION ». The Ohio State University, 2013. http://rave.ohiolink.edu/etdc/view?acc_num=osu1376333781.

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Chapitres de livres sur le sujet "Current Steering DAC"

Kumar, Abhishek, Santosh Kumar Gupta et Vijaya Bhadauria. « A Low Power Approach for Designing 12-Bit Current Steering DAC ». Dans Lecture Notes in Electrical Engineering, 595–604. Singapore : Springer Singapore, 2020. http://dx.doi.org/10.1007/978-981-15-6840-4_49.

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Mathurkar, Piyush K., et Madan B. Mali. « CMOS 8-Bit Current-Steering Digital Random Return to Zero DAC ». Dans Advances in Computing and Information Technology, 615–22. Berlin, Heidelberg : Springer Berlin Heidelberg, 2013. http://dx.doi.org/10.1007/978-3-642-31600-5_60.

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Vital, J., A. Marques, P. Azevedo et J. Franca. « Design Considerations for a Retargetable 12b 200MHz CMOS Current-Steering DAC ». Dans Analog Circuit Design, 151–70. Boston, MA : Springer US, 2003. http://dx.doi.org/10.1007/0-306-47950-8_8.

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Das Mohapatra, Anshuman, et Manmath Narayan Sahoo. « Modelling of a Fibonacci Sequence 8-bit Current Steering DAC to Improve the Second Order Nonlinearities ». Dans Advances in Intelligent Systems and Computing, 533–43. Singapore : Springer Singapore, 2017. http://dx.doi.org/10.1007/978-981-10-6875-1_52.

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Darji, Pallavi, et Chetan Parikh. « A Calibration Technique for Current Steering DACs - Self Calibration with Capacitor Storage ». Dans Communications in Computer and Information Science, 103–14. Singapore : Springer Singapore, 2017. http://dx.doi.org/10.1007/978-981-10-7470-7_12.

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« Multispecies and Watershed Approaches to Freshwater Fish Conservation ». Dans Multispecies and Watershed Approaches to Freshwater Fish Conservation, sous la direction de Paul D. Thompson et Paul C. Burnett. American Fisheries Society, 2019. http://dx.doi.org/10.47886/9781934874578.ch24.

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Abstract—The Weber River is primarily known as a blue-ribbon Brown Trout Salmo trutta fishery; however, this river also supports populations of two jeopardized fishes, Bonneville Cutthroat Trout Oncorhynchus clarkii utah and Bluehead Sucker Catostomus discobolus. At least one population of Bonneville Cutthroat Trout in the Weber River provides an important and popular local fishery and expresses a fluvial life history where main-stem individuals grow large (300–500 mm total length) and migrate into small tributaries for spawning. Bluehead Suckers currently occur in the main stem of the Weber River, where they travel distances of 20 km between spawning and overwintering habitats. The habitat for both species has been fragmented by more than 300 barriers composed of irrigation diversions, road crossings, and utility stream crossings. Beginning in 2010, the Utah Division of Wildlife Resources and Trout Unlimited began undertaking barrier removal for native fish as a priority conservation action. Initially, the effort to reconnect habitat was slow and the lack of relationships with stakeholders such as water users, government agencies, private landowners, and utility companies was hampering progress with habitat reconnection. New barriers were being built at a faster rate than barriers were being removed. To build these relationships, a steering committee was formed to secure a small grant, hire a consulting firm, organize stakeholder meetings to identify broad stakeholder priorities, and write a watershed plan that ultimately identified Bonneville Cutthroat Trout and Bluehead Sucker as priority conservation targets. The watershed plan and subsequent stakeholder meetings developed a framework for the Weber River Partnership. The partnership holds an annual symposium where larger watershed issues are discussed. The symposium also provides a platform where all stakeholders can understand the activities occurring throughout the watershed and where there are opportunities to collaborate. The Weber River Partnership has provided a forum where fisheries managers have told the story of Bonneville Cutthroat Trout and Bluehead Sucker and the importance of habitat connectivity. Through collaborative relationships with nontraditional partners, the relevance of fisheries in the Weber River has been realized. Further relevance in the watershed is evidenced by the development of a wide range of on-the-ground actions. Fish passage has been re-established at three main-stem and four tributary barriers. Additional projects are in various stages of development, including a large fish ladder that will be built as part of a Federal Energy Regulatory Commission relicensing project at a small hydroelectric dam, and we continue to be contacted by water users with interest in developing irrigation diversion reconstruction projects that incorporate fish passage.

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Actes de conférences sur le sujet "Current Steering DAC"

Hu, Rongbin, et Xiaoying Zhang. « A switch-decoded current-steering DAC ». Dans 2015 International Conference on Optoelectronics and Microelectronics (ICOM). IEEE, 2015. http://dx.doi.org/10.1109/icoom.2015.7398812.

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Leger, Gildas. « Doubly-segmented current-steering DAC calibration ». Dans 2014 9th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS). IEEE, 2014. http://dx.doi.org/10.1109/dtis.2014.6850672.

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Zhang, Wei, Ruoyuan Qu et Ming Zhu. « Non-ideality Analysis of Current steering DAC ». Dans 2020 IEEE International Conference on Artificial Intelligence and Information Systems (ICAIIS). IEEE, 2020. http://dx.doi.org/10.1109/icaiis49377.2020.9194898.

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Muller, Stefan, Oner Hanay et Renato Negra. « Current-steering DAC linearisation by impedance transformation ». Dans 2016 IEEE Nordic Circuits and Systems Conference (NORCAS) : NORCHIP and International Symposium of System-on-Chip (SoC). IEEE, 2016. http://dx.doi.org/10.1109/norchip.2016.7792900.

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Pu Luo, Weidong Yang et Dongbing Fu. « A current switch of current-steering DAC output stage ». Dans 2011 International Conference on Anti-Counterfeiting, Security and Identification (2011 ASID). IEEE, 2011. http://dx.doi.org/10.1109/asid.2011.5967439.

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Cheng, Long, Chi-Xiao Chen, Fan Ye, Ning Li et Jun-Yan Ren. « A digitally calibrated current-steering DAC with current-splitting array ». Dans 2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS). IEEE, 2012. http://dx.doi.org/10.1109/mwscas.2012.6292011.

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Kunnath, Abishek T., et Bibhudatta Sahoo. « A Digitally Assisted Radiation Hardened Current Steering DAC ». Dans 2016 29th International Conference on VLSI Design and 2016 15th International Conference on Embedded Systems (VLSID). IEEE, 2016. http://dx.doi.org/10.1109/vlsid.2016.76.

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Luo, Min, Mingyan Yu et Gen Li. « An 11-bit high-speed current steering DAC ». Dans 2012 2nd International Conference on Consumer Electronics, Communications and Networks (CECNet). IEEE, 2012. http://dx.doi.org/10.1109/cecnet.2012.6202005.

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Lei Luo et Jun Yan Ren. « An 8-bit 700Ms/s current-steering DAC ». Dans 2008 9th International Conference on Solid-State and Integrated-Circuit Technology (ICSICT). IEEE, 2008. http://dx.doi.org/10.1109/icsict.2008.4734969.

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Yenuchenko, Mikhail S. « Alternative structures of a segmented current-steering DAC ». Dans 2018 International Symposium on Consumer Technologies (ISCT). IEEE, 2018. http://dx.doi.org/10.1109/isce.2018.8408905.

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Rapports d'organisations sur le sujet "Current Steering DAC"

Gregow, Hilppa, Antti Mäkelä, Heikki Tuomenvirta, Sirkku Juhola, Janina Käyhkö, Adriaan Perrels, Eeva Kuntsi-Reunanen et al. Ilmastonmuutokseen sopeutumisen ohjauskeinot, kustannukset ja alueelliset ulottuvuudet. Suomen ilmastopaneeli, 2021. http://dx.doi.org/10.31885/9789527457047.

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The new EU strategy on adaptation to climate change highlights the urgency of adaptation measures while bringing forth adaptation as vitally important as a response to climate change as mitigation. In order to provide information on how adaptation to climate change has been promoted in Finland and what calls for attention next, we have compiled a comprehensive information package focusing on the following themes: adaptation policy, impacts of climate change including economic impacts, regional adaptation strategies, climate and flood risks in regions and sea areas, and the availability of scientific data. This report consists of two parts. Part 1 of the report examines the work carried out on adaptation in Finland and internationally since 2005, emphasising the directions and priorities of recent research results. The possibilities of adaptation governance are examined through examples, such as how adaptations steering is organised in of the United Kingdom. We also examine other examples and describe the Canadian Climate Change Adaptation Platform (CCAP) model. We apply current information to describe the economic impacts of climate change and highlight the related needs for further information. With regard to regional climate strategy work, we examine the status of adaptation plans by region and the status of the Sámi in national adaptation work. In part 2 of the report, we have collected information on the temporal and local impacts of climate change and compiled extensive tables on changes in weather, climate and marine factors for each of Finland's current regions, the autonomous Åland Islands and five sea areas, the eastern Gulf of Finland, the western Gulf of Finland, the Archipelago Sea, the Bothnian Sea and the Bay of Bothnia. As regards changes in weather and climate factors, the changes already observed in 1991-2020 are examined compared to 1981-2010 and future changes until 2050 are described. For weather and climate factors, we examine average temperature, precipitation, thermal season duration, highest and lowest temperatures per day, the number of frost days, the depth and prevalence of snow, the intensity of heavy rainfall, relative humidity, wind speed, and the amount of frost per season (winter, spring, summer, autumn). Flood risks, i.e. water system floods, run-off water floods and sea water floods, are discussed from the perspective of catchment areas by region. The impacts of floods on the sea in terms of pollution are also assessed by sea area, especially for coastal areas. With regard to marine change factors, we examine surface temperature, salinity, medium water level, sea flood risk, waves, and sea ice. We also describe combined risks towards sea areas. With this report, we demonstrate what is known about climate change adaptation, what is not, and what calls for particular attention. The results can be utilised to strengthen Finland's climate policy so that the implementation of climate change adaptation is strengthened alongside climate change mitigation efforts. In practice, the report serves the reform of the National Climate Change Adaptation Plan and the development of steering measures for adaptation to climate change both nationally and regionally. Due to its scale, the report also serves e.g. the United Nations’ aim of protecting marine life in the Baltic Sea and the national implementation of the EU strategy for adaptation to climate change. As a whole, the implementation of adaptation policy in Finland must be speeded up swiftly in order to achieve the objectives set and ensure sufficient progress in adaptation in different sectors. The development of binding regulation and the systematic evaluation, monitoring and support of voluntary measures play a key role.

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