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1
Su, Chao. « Dynamic calibration of current-steering DAC ». [Ames, Iowa : Iowa State University], 2007.
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2
Moody, Tyler J. « Design of a 10-bit 1.2 GS/s Digital-to-Analog Converter in 90 nm CMOS ». Wright State University / OhioLINK, 2015. http://rave.ohiolink.edu/etdc/view?acc_num=wright1440063577.
Texte intégral
3
Majid, Abdul, et Abdul Waheed Malik. « Design and Implementation of a Direct Digital Frequency Synthesizer using Sum of Weighted Bit Products ». Thesis, Department of Electrical Engineering, 2009. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-19986.
Texte intégralRésumé :
Direct Digital Frequency Synthesis (DDFS) is a method of producing an analog waveform by
generating a time-varying signal in digital form, succeeded by digital-to-analog reconstruction.
At behavioral level the bit products with specified weights are used to generate the sine wave. In representation of a sine wave both positive and negative weights are generated. Since negative weights are not desired in design, the negative weights are transformed to positive weights. To reduce the number of current sources and control signals, bit product signals of those current sources which cannot be switched on simultaneously and have equal weights are shared. After sharing weights, the control signals are reduced to from 59 to 43 and current sources from 207 to 145.
Different control words are used by the DDFS system in order to generate different frequencies. The control word is successively added to the previous value in a 20-bit accumulator. Nine most significant bits out of these twenty bits are used for the DAC.
Since the Current Steering DAC architecture is suitable for high speed and high resolution purposes, so a 9-bit nonlinear current steering DAC is used to convert the output of bit products to the analog sine wave. Seven bits are used to generate one quarter of the sine wave. Eighth and ninth bits are used to generate the full sine wave.
HCMOS 9 (130 nm) ST Microelectronics process is used by employing high speed NMOS and PMOS transistors. The bit products (control signals) are computed by using complementary static CMOS logic which then act as control signals for the current sources after passing through D-flip flops. Practical design issues of current sources and parts of digital logic were studied and implemented using the Cadence full-custom design environment.
4
Warecki, Sylwester. « Behavioral simulation of digital to analog converters simulation of segmented current steering DAC with utilization of perfect sampling technique ». Diss., The University of Arizona, 2003. http://hdl.handle.net/10150/280331.
Texte intégralRésumé :
Rapid progress in telecommunication and introduction of wireless phones has revolutionized the way, in which the analog signal is treated. High Radio Frequency (RF) pollution caused by increased number of subscribers imposes new requirements on the quality of transmitted RF signal. These requirements are met by introduction of Digital Direct Synthesis (DDS) of Intermediate Frequency (IF). The DDS eliminates the analog IF mixing stage, which is responsible interference with modulated signal. The high accuracy of DDS modulation is possible only with high quality digital-to-analog conversion. The design of Digital-to-Analog Converters (DAC) providing high-speed and high-resolution is extremely difficult. To overcome problems caused by manufacturing process variation numerous techniques such as thermometer coding or calibration are utilized in DAC design. However, in many cases implementation of these techniques becomes a source of new problems such as clock jitter or glitch. To solve them simulation of DAC, depicting numerous effects of physical phenomena, is an absolute necessity. Unfortunately such simulation with utilization of off-the-shelf mixed signal simulators is very demanding. Therefore simulation of all DAC circuit becomes impractical due to long simulation time or lack of good models of still studied phenomena such as glitch. A novel method allowing for simultaneous and accurate representation of numerous phenomena and significantly increasing simulation speed is proposed. The method is called a Perfect Sampling Technique (PST) and it allows for precise calculation of most important in telecommunication dynamic DAC performance metric---the Spurious Free Dynamic Range (SFDR). The technique was primarily built to overcome the deficiencies of popular Discrete Fourier Transform (DFT). This novel approach allows for concurrent simulation of the following phenomena: deterministic and random clock jitter, random and graded current source mismatch, and the glitch and output finite impedance. The implemented in Visual C++ simulator provides means of representation of various DAC structures: segmentation (thermometer and binary coding), 2D layout of current source matrix and analog switch dynamic characteristics. It utilizes behavioral models of DAC building blocks (analog switches) in custom-built extremely fast event driven simulation framework. It also provides means for parametric, statistical, transient and spectral analysis of DAC.
5
Ebrahimi, Mehr Golnaz. « Design of a Rom-Less Direct Digital Frequency Synthesizer in 65nm CMOS Technology ». Thesis, Linköpings universitet, Elektroniska komponenter, 2013. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-91680.
Texte intégralRésumé :
A 4 bit, Rom-Less Direct Digital Frequency Synthesizer (DDFS) is designed in 65nm CMOS technology. Interleaving with Return-to-Zero (RTZ) technique is used to increase the output bandwidth and synthesized frequencies. The performance of the designed synthesizer is evaluated using Cadence Virtuoso design tool. With 3.2 GHz sampling frequency, the DDFS achieves the spurious-free dynamic range (SFDR) of 60 dB to 58 dB for synthesized frequencies between 200 MHz to 1.6 GHz. With 6.4 GHz sampling frequency, the synthesizer achieves the SFDR of 46 dB to 40 dB for synthesized frequencies between 400 MHz to 3.2 GHz. The power consumption is 80 mW for the designed mixed-signal blocks.
6
Bertondini, Giulio. « Progetto di un sistema di misura integrato per la calibrazione statica di un Current-Steering RF-DAC a 14 bit in tecnologia FinFET ». Master's thesis, Alma Mater Studiorum - Università di Bologna, 2020. http://amslaurea.unibo.it/19822/.
Texte intégralRésumé :
Il presente lavoro di tesi, svolto nel corso di 6 mesi di tirocinio presso Xilinx Irlanda, è focalizzato sullo studio e calibrazione degli effetti introdotti dalle non-idealità di tipo statico presenti nei convertitori digitale-analogici (Digital to Analog Converter: DAC) a radio frequenza con architettura Current-Steering, basata su un insieme di generatori di corrente con segmentazione mista termometrica e binaria: 14 bit binari suddivisi in 8 LSB binari e 6 MSB binari convertiti in 63 bit termometrici.
Le non-idealità statiche includono i mismatch dei generatori e un gradiente di processo che condiziona fortemente il valore delle correnti dei generatori. Questo porta ad avere problemi di distorsione armonica nel segnale analogico generato dal DAC.
Sono stati implementati e simulati, in Verilog-A, algoritmi per la riduzione della distorsione utilizzando dapprima i valori di corrente dei generatori forniti da un modello Verilog-A del DAC. In realtà, su silicio, queste correnti devono essere misurate con precisione con un sistema di misura. È stato quindi progettato, utilizzando librerie FinFET TSMC (Taiwan Semiconductor Manufacturing Company) in Cadence Virtuoso, un sistema di misura integrato che consente di misurare le correnti di tutti i 63 generatori termometrici del valore nominale di 500uA, con una precisione di circa 50nA, impiegando un tempo di alcune decine di ms e consentendo in questo modo la calibrazione del DAC.
Infine sono stati modificati gli algoritmi precedentemente introdotti nel modello del DAC, inserendo degli opportuni coefficienti legati alla precisione di misura del sistema progettato, ottenendo risultati molto positivi in cui si nota l'efficacia del sistema di misura e della calibrazione del DAC in situazioni realistiche.
7
Marzocchi, Achille. « Time Interleaved DAC : Analisi delle non idealità dell'architettura e progetto di un sistema di misura del clock differenziale in tecnologia FinFET a 7nm ». Master's thesis, Alma Mater Studiorum - Università di Bologna, 2021. http://amslaurea.unibo.it/24108/.
Texte intégralRésumé :
Lo sviluppo di nuove architetture di convertitori digitale-analogico in grado di operare a
radio frequenza comporta nuove sfide e problematiche di cui è necessario che i progettisti
tengano conto in fase di design. Il presente lavoro di ricerca, svolto nel corso di 9 mesi di
tirocinio presso Xilinx, è focalizzato sullo studio delle non linearità e l’analisi delle
prestazioni dell’architettura Two Folded Time Interleaved DAC implementata mediante
l’utilizzo di due convertitori Current Steering DAC a 16bit operanti alla frequenza di
10GHz. A tale proposito è stato creato in ambiente Cadence Virtuoso un modello
VerilogA dell’architettura che consente di simulare le non idealità statiche e dinamiche e
di misurarne l’effetto sulle performance del circuito. Le analisi effettuate hanno
dimostrato che uno scostamento del duty cycle del clock del convertitore di appena 100fs
dal valore di riferimento comporti il peggioramento del SFDR del segnale di uscita a circa
-54 dBc, risultato non accettabile per la maggior parte delle applicazioni in campo
wireless. Metodi di calibrazione e correzione delle non idealità, tra cui il segnale di clock,
sono quindi necessari per ottenere prestazioni accettabili per il mercato. Lo studio si è
quindi posto l’obiettivo di progettare un sistema di misurazione delle non idealità
temporali del clock al fine di fornire uno strumento di calibrazione del TIDAC. Nello
specifico, è stato progettato un sistema di misura del clock in tecnologia FinFET TSMC
a 7nm in grado di garantire che il duty cycle del clock differenziale del TIDAC sia del
50%. Si è poi verificato con opportune simulazioni che il sistema di misura è in grado di
misurare lo skew e differenze di duty cycle tra le due fasi del clock con un errore di
massimo 45fs e di misurare il duty cycle di ogni singola fase seguendo un approccio
robusto a mismatch ed offset del sistema di misura.
8
McDonnell, Samantha. « Compensation and Calibration Techniques for High Performance Current-Steering DACs ». The Ohio State University, 2016. http://rave.ohiolink.edu/etdc/view?acc_num=osu1468060900.
Texte intégral
9
Andersson, Ola. « Modeling and Implementation of Current-Steering Digital-to-Analog Converters ». Doctoral thesis, Linköpings universitet, Elektroniksystem, 2005. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-5062.
Texte intégralRésumé :
Data converters, i.e., analog-to-digital converters (ADCs) and digital-to-analog converters (DACs), are interface circuits between the analog and digital domains. They are used in, e.g., digital audio applications, data communication applications, and other types of applications where conversion between analog and digital signal representation is required. This work covers different aspects related to modeling, error correction, and implementation of DACs for communication applications where the requirements on the circuits in terms of speed and linearity are hard. The DAC architecture considered in this work is the current-steering DAC, which is the most commonly used architecture for high-speed applications. Transistor-level simulation of complex circuits using accurate transistor models require long simulation times. A transistor-level model of a DAC used in a system simulation is likely to be a severe bottleneck limiting the overall system simulation speed. Moreover, investigations of stochastic parameter variations require multiple simulation runs with different parameter values making transistor-level models unsuitable. Therefore, there is a need for behavioral-level models with reasonably short simulation times. Behavioral-level models can also be used to find the requirements on different building blocks on high abstraction levels, enabling the use of efficient topdown design methodologies. Models of different nonideal properties in current-steering DACs are used and developed in this work. Static errors typically dominates the low-frequency behavior of the DAC. One of the limiting factors for the static linearity of a current-steering DAC is mismatch between current sources. A well-known model of this problem is used extensively in this work for evaluation of different ideas and techniques for linearity enhancement. The highfrequency behavior of the DAC is typically dominated by dynamic errors. Models oftwo types of dynamic errors are developed in this work. These are the dynamic errors caused by parasitic capacitance in wires and transistors and glitches caused by asymmetry in the settling behavior of a current source. The encoding used for the digital control word in a current steering DAC has a large influence on the circuit performance, e.g., in terms static linearity and glitches. In this work, two DAC architectures are developed. These are denoted the decomposed and partially decomposed architectures and utilize encoding strategies aiming at a high circuit performance by avoiding unnecessary switching of current sources. The developed architectures are compared with the well-known binary-weighted and segmented architectures using behavioral-level simulations. It can be hard to meet a DAC design specification using a straightforward implementation. Techniques for compensation of errors that can be applied to improve the DAC linearity are studied. The well-known dynamic element matching (DEM) techniques are used for transforming spurious tones caused by matching errors into white or shaped noise. An overview of these techniques are given in this work and a DEM technique for the decomposed DAC architecture is developed. In DS modulation, feedback of the quantization error is utilized to spectrally shape the quantization noise to reduce its power within the signal band. A technique based on this principle is developed for spectral shaping of DAC nonlinearity errors utilizing a DAC model in a feedback loop. Two examples of utilization of the technique are given. Four different current-steering DACs implemented in CMOS technology are developed to enable comparison between behavioral-level simulations and measurements on actual implementations and to provide platforms for evaluation of different techniques for linearity improvement. For example, a 14-bit DEM DAC is implemented and measurement results are compared with simulation results. A good agreement between measured and simulated results is obtained. Moreover, a configurable 12-bit DAC capable of operating with different degrees of segmentation and decomposition is implemented to evaluate the proposed decomposed architecture. Measurement results agree with results from behavioral-level simulations and indicate that the decomposed architecture is a viable alternative to the commonly used segmented architecture.
10
Balasubramanian, Sidharth. « STUDIES ON HIGH-SPEED DIGITAL-TO-ANALOG CONVERSION ». The Ohio State University, 2013. http://rave.ohiolink.edu/etdc/view?acc_num=osu1376333781.
Texte intégral
11
Lu, Hsing-Ming, et 盧星銘. « A 6-bit 1GS/s Current-Steering DAC ». Thesis, 2012. http://ndltd.ncl.edu.tw/handle/54230076085442256329.
Texte intégralRésumé :
碩士中原大學
電子工程研究所
100
In this paper, a current-steering digital-to-analog converter with a 6-bit 1GS/s is designed. It is facilitated with TSMC 0.18 1P6M CMOS process with digital and analog supply voltage at 1.8V. With sampling frequency at 490MHz, the SFDR is obtained as 51dB, which corresponds to effective digit at 5.95. Total power consumption is 24mW with analog part as 22.68mW and digital part as 1.32mW.
12
Sun, Yu-long, et 孫玉龍. « A 14-bit High Accuracy Current-Steering DAC ». Thesis, 2014. http://ndltd.ncl.edu.tw/handle/95263781938376185817.
Texte intégralRésumé :
碩士國立臺灣科技大學
電子工程系
102
A general methodology to construct highly matched layout pattern for multiple-device is proposed in this thesis. With these general methodologies, engineers will have more degrees of freedom for choosing layout pattern according to their innovations and the degree of circuit precision. This thesis Design a 14-bit high accuracy current-steering DAC to implement proposed layout pattern. The DAC presented is segmented architecture. The eight most significant bits are decoded from binary to thermometer code in the thermometer decoder, which steers the unary weighted current source array. The Systematic mismatch of this current source array is canceled by highly matched layout pattern. The size of transistor is decided though Monte Carlo simulation , and the layout of current source array made by Layout automation. The six bit least significant bits are implemented by a current divided circuit proposed by this thesis to enhance accuracy and update rate. The DAC would be integrated in TSMC 0.18um Mixed-Signal 1P6M process, running from 2.7V power supply. The integral nonlinearity of post-simulation is 0.034LSB, update rate is 200 MHz and the chip core area is 6.62mm2.
13
Wei-ChengHung et 洪偉程. « A 12-bit 2GS/s Current-Steering DAC in 0.07mm2 ». Thesis, 2013. http://ndltd.ncl.edu.tw/handle/19395243757378184961.
Texte intégralRésumé :
碩士國立成功大學
電機工程學系碩博士班
101
In this thesis, a 12-bit 2GS/s current-steering DAC design is presented to overcome the three main nonlinearity sources, which are current source mismatch, output transition nonlinearity, and finite output impedance, and achieve high-speed high-resolution characteristic. Firstly, for the current source mismatch, two different dynamic element matching (DEM) algorithms, random rotation-based binary-weighted selection (RRBS) and data weighted averaging (DWA), are adopted to process the harmonic distortion tones caused by mismatch error for different applications. Secondly, reduced-switch and non-cascoded modifications of the current cells increase the output transition speed and decrease the influence of transition nonlinearity. In addition, a digital resetting return-to-zero (RTZ) is adopted to further enhance the output transition linearity. Finally, for the finite output impedance, an output impedance compensation circuit is proposed to compensate the nonlinear impedance curve of current cells. By dealing with these nonlinearity sources, this DAC performs excellent at high sampling rate. The current-steering DAC is fabricated in TSMC 90nm 1P9M CMOS technology with only 0.07mm2 of active area. The measurement results show that the DAC achieves 〉70dB SFDR from dc to 400MHz sampling at 1GHz and performs best in figure of merit (FOM) comparing to state-of-the-art works.
14
Cheng, Wei-Sheng, et 程韋盛. « A High Speed Current-Steering DAC for Powerline Communication System ». Thesis, 2012. http://ndltd.ncl.edu.tw/handle/84476907365301286957.
Texte intégralRésumé :
碩士國立臺灣大學
電子工程學研究所
101
A 10-bit current-steering digital-to-analog converter (DAC) has been proposed for high speed communication systems. This study is used for the transmitter (Tx) of the powerline communication (PLC) analog-front-end (AFE), and it reaches the standard of the HomePlug AV2. And the DAC has also been combined with the line driver as the transmitter of the whole system. In order to improve static performance, we use 6-4 segmented decoding architecture to get good matching and reduce the glitch. Furthermore, we implemented our current source array as common centroid type and adding dummy current sources around the array to reduce the mismatch between edge and center. For dynamic performance consideration, the proposed DAC uses a technique as digital random-return-to-zero (DRRZ) [10][11] to achieve good performance for high speed sampling frequency. The test chip was fabricated in TSMC 90 nm CMOS technology and occupied 0.42 mm2 for active area. The supplies for the analog and digital circuits are 2.5V and 1.2V. The maximum INL and DNL are 0.8 LSB and 0.3 LSB respectively. The SFDR is up to 40.09 dB for 1.25GS/s of Nyquist-rate sampling. The power consumption is 58mW.
15
Lai, Ming-Jun, et 賴明君. « A 1.8V 10-bit 500MS/s Low Glitch Current-Steering DAC ». Thesis, 2009. http://ndltd.ncl.edu.tw/handle/19654004222443783767.
Texte intégralRésumé :
碩士國立交通大學
電信工程系所
97
In the recently years, wireless communication systems require high speed and high resolution digital-to-analog converters. Current-steering DAC is a particularly appropriate architecture for these applications. These DAC’s specification in dynamic performance, are more important than static performances including INL and DNL in wireless communication systems. DAC’s dynamic performances are limited by output impedance and low output swing in the low voltage design, besides, glitch energy also manly degrades the SFDR. In this thesis, a 1.8V 10-bit 500MHz, low glitch energy current-steering digital-to-analog converter (DAC) is presented. This DAC is segmented into 4 LSBs binary-weighted and 6 MSBs unary cells. A “multi-finger” technique is used to reduce the worst case of glitch energy. The post-layout simulation in the 500MS/s results the glitch energy is only 0.4 pVs. The SFDR achieve 74 dB with a full-scale 49 MHz input frequency. The integral nonlinearity (INL) and differential nonlinearity (DNL) are less than 0.07 LSB and 0.06 LSB. The power consumption is just only 14mW at maximum sampling rate.
16
Hutahaean, Antony, et Antony Hutahaean. « A 14-bit 500MS/s High Accuracy Current-Steering CMOS DAC ». Thesis, 2015. http://ndltd.ncl.edu.tw/handle/96627273568148415927.
Texte intégralRésumé :
碩士國立臺灣科技大學
電子工程系
103
A 14-bit 500MS/s high accuracy current-steering digital-to-analog converter (DAC) was designed in UMC 0.18um Mixed-Mode RF CMOS 1P6M process. To achieve a high accuracy, a general methodology to construct highly matched layout pattern for multiple-device was proposed in this thesis. With this general methodology, the engineers will be free to choose a layout pattern according to their innovation and the level of circuit precision. DAC was implemented in segmented architecture to implement the proposed layout pattern. The eight most significant bits are decoded from binary to thermometer code in the thermometer decoder, which steers the unary weighted current source array. The systematic mismatch of this current source array is canceled by highly matched layout pattern. To achieve higher output impedance, a 3.3 Volt CMOS model was used in cascade current source. The size of current sources was decided through Monte Carlo simulation, and the layout of current source array made by layout automation. The six bit least significant bits are implemented by binary weighted current divider circuit to enhance accuracy and update rate. And proposed switch and deglitcher were implemented to reduce the current glitch. The simulation on integral and differential nonlinearity performance are 0.1 and 0.09 LSB, respectively; the spurious-free dynamic range is 80.8 dB at 240 MHz and total area allocation is 1.32*1.52mm2.
17
Fu, Jian-Ming, et 傅健銘. « Design of 10-Bit 500MSample/s Current-Steering Binary-Weighted DAC ». Thesis, 2006. http://ndltd.ncl.edu.tw/handle/91026253264281549299.
Texte intégralRésumé :
碩士國立暨南國際大學
電機工程學系
94
Digital to analog converter (DAC) is widely used in many modern audio and communication system. Such as: digital TV, and radio transmitter etc.. For the applications, a high speed DAC with suitable resolution is required. In the thesis, a 10-Bit 500MSample/s Current-Steering Binary-Weighted DAC is presented. In order to achieve high linearity and spurious free dynamic range (SFDR) , four technique is adopted, including of using binary-weight coding to reduce the circuit area, current source arranging in current source array (CSA) to decrease process variation, using randomization to average non-linearity error, and employing a deglitch latch to improve dynamic performance. For a 500MHz sampling rate, the SPDR of 69dB at 100MHz signal frequency is achieved. The converter consumes total 90 mW. The chip is implemented in a standard TSMC 0.18-mm 1P6M CMOS technology. The converter active area is 0.6 mm2.
18
« Design and Calibration of a 12-Bit Current-Steering DAC Using Data-Interleaving ». Master's thesis, 2014. http://hdl.handle.net/2286/R.I.26805.
Texte intégralRésumé :
abstract: High speed current-steering DACs with high linearity are needed in today's applications such as wired and wireless communications, instrumentation, radar, and other direct digital synthesis (DDS) applications. However, a trade-off exists between the speed and resolution of Nyquist rate current-steering DACs. As the resolution increases, more transistor area is required to meet matching requirements for optimal linearity and thus, the overall speed of the DAC is limited.
In this thesis work, a 12-bit current-steering DAC was designed with current sources scaled below the required matching size to decrease the area and increase the overall speed of the DAC. By scaling the current sources, however, errors due to random mismatch between current sources will arise and additional calibration hardware is necessary to ensure 12-bit linearity. This work presents how to implement a self-calibration DAC that works to fix amplitude errors while maintaining a lower overall area. Additionally, the DAC designed in this thesis investigates the implementation feasibility of a data-interleaved architecture. Data interleaving can increase the total bandwidth of the DACs by 2 with an increase in SQNR by an additional 3 dB.
The final results show that the calibration method can effectively improve the linearity of the DAC. The DAC is able to run up to 400 MSPS frequencies with a 75 dB SFDR performance and above 87 dB SFDR performance at update rates of 200 MSPS.Dissertation/Thesis
Masters Thesis Electrical Engineering 2014
19
Lu, Nan-Ku, et 呂南谷. « Nonlinearity Analysis and Implementation of Folded R-2R Ladder-Based Current-Steering DAC ». Thesis, 2012. http://ndltd.ncl.edu.tw/handle/94729863484871062796.
Texte intégralRésumé :
博士中原大學
電子工程研究所
100
This thesis presents two new architectures which are called folded R-2R ladder-based current-steering digital to analog converter and pseudo binary folded R-2R ladder-based current-steering digital to analog converter, respectively. A theoretical nonlinearity analysis of R-2R ladder-based current-steering digital to analog converter and proposed circuits is presented. In addition, the nonlinearities caused by the current mismatches and the resistor mismatches are also analyzed. This thesis also presents a design flow of pseudo binary folded R-2R ladder-based current-steering digital to analog converter. The derived equations enable circuit designers to quickly select the most suitable design for their applications by calculating the required resistor mismatch and required current mismatch. In the case of 6-bit resolution, the proposed circuit can reduce the total number of required unit resistors by up to 56.25% and 56.25% power consumption compared with conventional R-2R ladder-based current-steering DAC. The measured DNL and INL are 0.34LSB and 0.25LSB, respectively. The converter consumes 8mW with 1.8V power supply. The active area of chip is less than 0.042mm2 in TSMC 0.18um 1P6M process.
20
Wei, Li-Fan, et 魏立帆. « A 10-Bit 1-GS/s Current-Steering DAC with Foreground Calibration Method ». Thesis, 2017. http://ndltd.ncl.edu.tw/handle/543dv6.
Texte intégralRésumé :
碩士國立清華大學
電機工程學系所
105
Abstract As the communication system advances, the data of the digital transmission is growing rapidly.Therefore, the data converter plays the important role in the recent years. Also, high speed, high bandwidth and dynamic range are the future trend. The topic of the thesis is implementing the digital to analog converter in the high speed and high bandwidth requirements. For high speed operation, the work employ the current steering data converter which the limit of the speed depends on the time constant, and is convenient in high speed application. However the mismatch between the current sources rigidly influence the static and dynamic performance for the data converter. Except for using bigger size of the device, we use the calibration for the current source instead. Before the operation for DAC, we can adjust the current for the current source one to one in the foreground calibration method which can save the area and also achieve the high accuracy. In the implementation of the chip, my work employ the 10bit D/A converter in 65nm. The power supply is 2.5V and the differential output’s Vpp is 0.8V. The chip can split in two parts: the D/A converter, the delta sigma ADC. The D/A converter is built by the current steering DAC, and the delta sigma ADC which is used to sample the difference between current source implements in the first order discrete time delta sigma modulator. After the calibration, SFDR can be improved from 58dB to 79dB in Fin=50M, Fs=1GS/s.
21
Wen, Yu-De, et 溫于德. « The Design of Current-Steering DAC for Dual Mode Array Sensor Readout Circuit ». Thesis, 2014. http://ndltd.ncl.edu.tw/handle/23696896745825315531.
Texte intégralRésumé :
碩士國立暨南國際大學
電機工程學系
102
This paper proposes dual-mode buffer direct injection (BDI) and direct injection (DI) with current steering DAC readout circuit design. Combining advantages of DI with BDI is used many types of sensors applications. According to the sensor types, added switch to control readout circuit structure become BDI & DI. It has completed dual switch mode which has detected different sensor at array integrated readout circuit. We debated from the power, efficiency, injection efficiency, layout area and circuit noise. Current steering DAC is used to control the biosensor bias voltage and control Gain stage offset voltage. Gain, bandwidth and noise are the readout circuit design of chief considerations. Simulation result of amplifier gain is 40dB. The Circuit is simulated by using TSMC 0.35um Mixed Signal 2P4M CMOS 5V process. The input current setting 1nA to 10nA, the simulation output voltage swing is 2V and the total power consumption is less than 9.76mW. The DAC has the following characteristics: 7bit, INL≦ ± 0.9 LSB,DNL≦ ±0.4LSB and cosumes power 0.299mW. The measurement current setting 10p to 10 nA. The integration time would adjust. The circuit output swing is 2V, signal to noise ratio is 52dB, and the full chip circuit power consumption is 10.31mW.
22
Chuang, He-Hsiang, et 莊賀翔. « A 10-bit Current-Steering DAC with Dynamic Element Matching for Powerline Communication System ». Thesis, 2013. http://ndltd.ncl.edu.tw/handle/17930901638333208041.
Texte intégralRésumé :
碩士國立臺灣大學
電子工程學研究所
101
A 10-bit current-steering digital-to-analog converter (DAC) has been proposed for high accuracy communication systems. This chip is used for the transmitter (Tx) of the powerline communication (PLC) analog-front-end (AFE), and it reaches the standard of the HomePlug AV2 (2MHz~86MHz). In order to improve static performance, we use 6(thermometer-coded)-4 (weighted) segmented decoding architecture to get good matching and reduce the glitch. Furthermore, we implement the current source array as common centroid and adding dummy current sources around the array to reduce the mismatch between edge and center. For dynamic performance consideration, the proposed DAC uses the Dynamic Element Matching (DEM) technique [7][11][12] to achieve good linearity. The chip was fabricated in TSMC 90 nm CMOS technology and occupied 0.35 mm2 for active area. The supplies for the analog and digital circuits both are 1.2V. The maximum INL and DNL are -0.57 LSB and -0.44 LSB respectively. The SFDR is up to 45 dB for 400MS/s of Nyquist-rate sampling. The power consumption is 25.42mW.
23
Ma, Yu-Qian, et 馬有謙. « A 10-Bit 1-GS/s Current-Steering DAC with Improved Dynamic-Performance Techniques ». Thesis, 2018. http://ndltd.ncl.edu.tw/handle/5a396j.
Texte intégralRésumé :
碩士國立清華大學
電機工程學系所
106
With the rapid development of communication systems and the need for integration of SoCs, the digital-to-analog converters (DACs) with accurate and massive data transmission have been widely used. Recently, high-speed and high-linearity current-steering digital-to-analog converters are widely used architecture. So the trend of the circuit is also going to use a smaller area to achieve a converter with higher speed, high dynamic specification. In order to achieve high specification of SFDR (SpuriousSpurious -Free ree ree ree Dynamic ynamic ynamic ynamic ynamic ynamic Rangeange ange), many non-linear problems need to be solved, such as the mismatch errors among current sources, finite impedance of current sources, high-speed switching transients, etc… The mismatch errors caused by the current source will affect the performance of both static and dynamic. Therefore, this thesis proposes a mechanism of RRHS (Random Rotation-Based Hybrid-Weighted Selector) DEM so that the errors caused by harmonic distortions can be converted more effectively to random white noise which is independent of the input digital code. It can also achieve high-accuracy and high-speed digital-to-analog converters in a smaller area. The use of the Always-on Cascode Stage to reduce the influence of the switching impedance in the finite impedance of the current sources. For high-speed switching transients, the skill of Moderate-Swing which effectively reduces the fluctuation of the current path due to parasitic capacitances is used to switch the switches. In this thesis, a 10-bit current-steering digital-to-analog converter with improved dynamic-performance is implemented. The device is fabricated with TSMC 65 nm and 1P9M complementary MOSFETs. Through the RRHS DEM, Always-on Cascode Stage, Moderate-Swing and other techniques, SFDR can be improved from less than 60dB to at least more than 70dB, also completing a high dynamic specifications of the current-steering digital analog-to-digital converter.
24
Chang, Chun-Chi, et 張峻旗. « A 14bit 100MS/s Current-Steering DAC with a Low Cost Self-Calibration Structure ». Thesis, 2007. http://ndltd.ncl.edu.tw/handle/29641677236088833548.
Texte intégralRésumé :
碩士國立成功大學
電機工程學系碩博士班
95
In many signal processing and telecommunication applications, Data converter is an important I/O interface. Data converter includes analog-to-digital converter (ADC) and digital-to-analog converter (DAC). In this thesis, we mainly focus in DAC design. For high speed application, the current-steering DAC is one of most suitable architecture. However, mismatch between current sources limits the performance of DAC. Large-area current source arrays can maintain a required level of matching accuracy between current sources, but the parasitic effect of large device results in degradation of dynamic range for high-frequency signal. So we present a new foreground self-calibration structure to overcome the problem. The calibration technique doesn't need addition high resolution analog-to-digital converter (ADC), it would reduce the complexity for circuit design. Beside, we use a deglitch technique to reduce glitch effect at switching time. In this thesis, a 14-bit 100MS/s current-steering DAC with a low cost self-calibration structure has been implemented. It uses the above foreground self-calibration technique to overcome the mismatch between current sources, and reduce device size to decrease in degradation of dynamic range for high-frequency signal. This not only makes cost down (smaller die area) but also improves the performance of the circuit. The DAC occupies 0.99 mm2 0f active area in TSMC 0.18-um 1P6M mixed signal CMOS process. It operates in 1.8 V power supply, and the power consumption is 32mW.
25
Liang, Ming-Chieh, et 梁明傑. « A 12-Bit 200MS/S Current-Steering DAC with TSMC 0.18um PDK Monte-Carlo-Analysis ». Thesis, 2010. http://ndltd.ncl.edu.tw/handle/04521674800079642167.
Texte intégralRésumé :
碩士國立清華大學
產業研發碩士積體電路設計專班
98
We propose a 12-Bit 200MS/S Current-Steering DAC based on a Segmented (5+7) current-steering architecture. In order to decrease the differential nonlinearity error (DNL) and reduce area, we employ Unary-Current cell with thermometer code decoder for the 5MSBs and Binary-Weighted Current Cell for the 7LSBs. In order to synchronize inputs and improve glitch energy, we use a digital latch approach. Differential switch order is very critical for DNL, so we use the Two Dimensional Centroid method. In order to enhance DAC output impedance and SFDR, both the MSB and LSB are implemented with Cascode Current Cell. To meet the 200MS/S and 1mm2 area spec, we perform Monte-Carlo Analysis with TSMC 0.18um Process Design Kit (PDK) and Mismatch Model. Because the Mismatch Model includes Process-Variation information, it can achieve more simulation accuracy than the corner model. Monte-Carlo simulation result, shows that when the input signal is 100MHz and sample rate is 200MHz, we have DNL=0.6LSB , and INL =0.8LSB. The chip area is 0.2mm2 in a TSMC 0.18um 1P6M CMOS Process.
26
Lai, Yan-Fong, et 賴晏鋒. « A 14-bit 200MS/s Current-Steering DAC with Digitally Assisted Calibration and Dynamic Matching Techniques ». Thesis, 2011. http://ndltd.ncl.edu.tw/handle/16227096937734524848.
Texte intégral
27
Hsu, Chih-Yuan, et 許智淵. « A 14-bit 100MSPS Current-Steering DAC with RMDWA Algorithm and New Return-to-Zero Scheme ». Thesis, 2006. http://ndltd.ncl.edu.tw/handle/05641775000847278597.
Texte intégralRésumé :
碩士國立成功大學
電機工程學系碩博士班
94
Current-steering digital-to-analog converters (DACs) can drive the external loading directly in high-speed applications. However, the performance of these current-steering DACs is determined by both the static and dynamic linearity. In this thesis, a DEM-like algorithm called “Random Multiple Data-Weighted Averaging, RMDWA” is accomplished to diminish the harmonic distortions resulted from process mismatches with its simple circuit design. BM rotated walk layout technique is proposed to increase the effect. Besides, the DACs also suffer from the glitches when they are operated at high speed. The return-to-zero (RTZ) switching scheme becomes a best candidate to eliminate the glitches from transients. Nevertheless, conventional RTZ schemes are the ways which are shorted the output to the ground. Abrupt voltage change results in current variations and more distortions. A proposed return-to-zero scheme with constant switching load can keep the same environments when transients and can maintain the high spurious free dynamic range (SFDR) in high-speed operations. Using the antecedent of new techniques, a low-power and small-area 14-bit 100-MHz current-steering DAC is implemented in this thesis. The DAC includes a 5-bit MSBs and ULSBs with thermometer decoders and RMDWA algorithm and 4-bit binary-coded LLSBs. A new return-to-zero switching scheme is placed in output of DAC to maintain the high-performance at high-speed output frequency. It just occupies 0.26mm2 in a TSMC 0.18um 1P6M CMOS process. In the simulation, the SFDR achieves 89dB at the lower output frequency, and 69dB at the Nyquist-rate output frequency with operated frequency of 100MS/s. The power consumptions are 21mW for analog circuits and 2mW for digital circuits from a 1.8V supply.
28
Ho, Zong-Yue, et 何宗岳. « Implementation of a 14-bit 200-MS/s Current-Steering DAC with Digital Foreground Calibration in 90-nm CMOS ». Thesis, 2014. http://ndltd.ncl.edu.tw/handle/a7343p.
Texte intégralRésumé :
碩士國立交通大學
電機工程學系
103
In recent years, high-speed; high-resolution digital-to-analog converters(DACs) become an essential element for direct frequency synthesizers, arbitrary wave generators, multimedia displays and communications transmitters. For high-speed applications, we adopt the current-steering structure; since its operation speed is mainly limited by output loadings and thus high sampling speed can be achieved. As to the design of high-accuracy current-steering DACs, current sources with high matching property are required and occupy a large area. Such a large area results in more intrinsic and parasitic capacitor loadings, and also degrades the signal bandwidth. In order to reduce loading, the most common way is using compact current cells. Therefore, foreground calibration performed in the digital domain is presented in this thesis to correct the current mismatches caused by small dimension of the current source. To verify the presented foreground calibration algorithm, a 14-bit 200Ms/s DAC has been fabricated in 90-nm CMOS technology. The area of under-calibrated current sources is 1/116 of the required area which is designed for 14-bit resolution. The active area is 1110 by 830 um^{2} . Simulation results show that the calibrated current-steering DAC achieves improvements in the SNDR and the SFDR by 30dB and 40dB respectively when 3.65% random errors are added to the current sources of most significant bit(MSB).
29
Hsu, Chia-Hsin, et 徐嘉欣. « High Efficiency Buck Converter with Wide Load Current Range Using Dual-mode of PWM and PSM and A 12-bit 100 MS/s Current Steering DAC Using Dynamic Element Matching and Return to Zero Techniques ». Thesis, 2019. http://ndltd.ncl.edu.tw/handle/d652de.
Texte intégralRésumé :
碩士國立中山大學
電機工程學系研究所
107
The Implementation of Signal Processing Chips”. Particularly, these topics applied the photonic gyro system are high-efficiency buck converter with wide load current range using dual-mode of PWM and PSM and 12-bit 100 MS/s current steering DAC using dynamic element matching and return to zero techniques. They are implemented using TSMC 0.35 um Mixed-Signal 2P4M Polycide 3.3/5 V and TSMC 45 nm CMOS LOGIC General Purpose Superb (40G) ELK Cu 1P10M 0.9/2.5 V processes, respectively. The proposed high efficiency buck converter is featured with integration of PWM and PSM modes to increase the efficiency given a wide load current range. The peak efficiency is 96.76 % when the load current is 1000 mA, while the efficiency in the load current range from 10 mA to 1000 mA is over 94.80 %. In addition, the proposed design accurately switches between heavy load current and light load current by a well-designed logic decoder circuit. A dynamic element matching and return to zero techniques are used to realize a 12- bit 100 MS/s current steering DAC with a precision of 1 to 10◦/h for the Heterogeneous Silicon Photonics Gyroscope. A pseudo-random number generator carries out the random selection of current sources to reduce the mismatch among these current sources caused by layout issues and also reduce the delay by using compact return to zero technique. Not only is the circuit area greatly reduced, the SFDR is also enhanced to 61 dB at 100 MS/s.
30
Wei-TeLin et 林韋德. « Dynamic-Performance-Improved Techniques for Nyquist-Rate Current-Steering DACs ». Thesis, 2013. http://ndltd.ncl.edu.tw/handle/80458940989109035842.
Texte intégralRésumé :
博士國立成功大學
電機工程學系碩博士班
101
Current-Steering Digital-to-Analog Converters (DACs) are widely used in high–speed applications. In this dissertation, several dynamic-performance-improved techniques for Nyquist-rate current-steering DACs are presented. For low-cost DAC designs, a DEM method, random rotation-based binary-weighted selection (RRBS), is proposed which offers the circuit simplicity that using binary- weighted coding and greatly reduces the mismatch effect. Compared with the conventional binary-weighted architecture, the switching activity of RRBS is improved and the glitch energy issues are inherently reduced by randomization. Although its switching activity is not near-minimum, the binary-to-thermometer decoder is not required, thereby further saving chip area. A 10-bit RRBS DAC is implemented with only 0.034 mm2 in a 0.18μm CMOS process. Measured performance achieves 〉61 dB spurious-free dynamic range (SFDR) in the Nyquist bandwidth with 500 MS/s, while its active area is less than one-tenth of that required by state-of-the-art 10-bit current steering DACs. Its SFDR is also comparable to that of 12-bit published designs. Three popular figures-of-merit (FoMs) are used to compare this design with other state-of-the-art 10~12-bit DACs, with the proposed design performing best with 2 FoMs. For high-resolution DACs, A novel layout pattern, i.e., one-line-routing (OLR), incorporating with DEM method for low-cost current-steering DACs is proposed. The proposed OLR method exhibits good gradient error compensation with low complexity and small metal routing overhead compared with most published methods, and induces less parasitic capacitance. With the proposed OLR incorporating with DEM, a 14-bit current-steering DAC is implemented in a 0.18μm CMOS process. The measured SFDR exceeds 80 dB at low output frequency and maintains 70 dB at near Nyquist output frequency clocked at 300 MS/s. The DAC has an active area of less than 0.18 mm2, which achieves a smaller active area than most of the state-of-the-art 14-bit DACs. For high-speed, high-resolution DACs, a technique utilizing dynamic-element- matching and digital return-to-zero, called DEMDRZ, is proposed to simultaneously suppress the mismatch- and transient-induced nonlinearity. In doing so, the usage of small-sized current sources and switches is possible, and the spurious-free dynamic range (SFDR) and third-order intermodulation distortion (IM3) for high signal frequencies can be improved. A 12-bit compact, low-power, high-speed, DAC is implemented in TSMC 40nm CMOS process. The implemented DAC achieves 〉70 dB SFDR for signals over the 800 MHz Nyquist bandwidth at 1.6 GS/s and 〈 -61 dB IM3 for signals over the 1.4 GHz Nyquist bandwidth at 2.8 GS/s. Further, it dissipates 40 mW with a single 1.2 V supply. The active area of the DAC is 0.016 mm2, which is less than 6% of other state-of-the-art 12-bit current steering DACs. Furthermore, the implemented DAC performs best with three common figure-of-merits (FoMs).
31
Shen, Meng-Hung, et 沈孟弘. « Linearity Enhancement and Area Reduction Techniques for CMOS Current-steering DACs ». Thesis, 2011. http://ndltd.ncl.edu.tw/handle/02653374607566394870.
Texte intégralRésumé :
博士國立清華大學
電機工程學系
99
This thesis investigates the techniques to reduce the silicon area of CMOS current-steering digital-to-analog converters (DACs) without compromising the circuit linearity. Conventional high-resolution DACs have to pay a penalty of large-size transistors to get better matching characteristics, thereby increasing the fabrication cost. In this thesis, two methods are proposed to achieve low-cost and high-resolution current-steering DACs. A self-correction method is developed in the first work. To minimize the area, the transistor size of current source array is reduced deliberately. This shrink will corrupt the DAC linearity performance. With the assistance of a current comparator, a calibration DAC (CalDAC) and calibration logics, two calibration loops are employed to estimate the current mismatches. Since all calibration processes work in the digital domain, the overhead for analog circuit is minimized. In the meanwhile, the proposed methodology can be easily ported to other high-resolution current-steering DACs, especially for deep-submicron processes. We designed a 12-bit video DAC prototype to demonstrate the proposed scheme. Experiment results show the proposed method reduces the DNL and INL to 0.26 and 0.42 LSB, which guarantees 12-bit linearity. At 400-MS/s update rate, the spurious-free dynamic range is above 59 dB within a 30-MHz bandwidth, which corresponds to the signal bandwidth for HDTV applications. This prototype occupies only 0.18mm^2 die area including all calibration functions in a standard 90- nm CMOS technology. Besides the calibration, dynamic element matching (DEM) is another effective method to increase the spurious free dynamic range of DACs. The second work describes a new DEM method called Random Swapping Thermometer Coding (RSTC). The direction selected for a sequence of unit current sources will be randomly changed. Combining this method with the restricted jumping technique the low-frequency idle tones can be mitigated. This approach minimizes the number of switched elements and transient glitches as code changes, while achieving good spectrum purity as other DEM implementations. This method is applied to a 14-bit current-steering DAC with a 4+4+6 double-segmented structure. The first four bits (MSB) and the middle four bits (ULSB) are converted into thermometer codes and employ the proposed RSTC algorithm, which can relax the matching requirement on current cells. The test chip draws 70mW from the supplies with 20mA full-scale current, and occupies only 0.28 mm^2 active area in a standard 55-nm CMOS process. From measurement results of the test chip, it has been shown to display only 10-bit static linearity with INL around 16LSB. The dynamic performance obtained after applying RSTC algorithm is enhanced from 62dB to 79dB at low frequencies for a 100MHz sampling clock.