Bibliographies thématiques / Electronic chips

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Littérature scientifique sur le sujet « Electronic chips »

Auteur : Grafiati
Publié le 4 juin 2021
Mis à jour le 6 septembre 2023

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Articles de revues sur le sujet "Electronic chips"

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Jackel, L. D., H. P. Graf et R. E. Howard. « Electronic neural network chips ». Applied Optics 26, no 23 (1 décembre 1987) : 5077. http://dx.doi.org/10.1364/ao.26.005077.

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Vallishayee, Rakesh R., Steven A. Orszag, Eric Jackson et Eytan Barouch. « Manufacturability of Electronic Chips ». Theoretical and Computational Fluid Dynamics 10, no 1-4 (1 janvier 1998) : 407–23. http://dx.doi.org/10.1007/s001620050073.

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Miller, David A. B. « Optical interconnects to electronic chips ». Applied Optics 49, no 25 (14 juillet 2010) : F59. http://dx.doi.org/10.1364/ao.49.000f59.

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Hayes, J. « Deep As Chips [AI chips] ». Engineering & ; Technology 15, no 11 (1 décembre 2020) : 72–75. http://dx.doi.org/10.1049/et.2020.1113.

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Harris, A. « Frozen chips [RFID chips] ». Computing and Control Engineering 17, no 3 (1 juin 2006) : 16–21. http://dx.doi.org/10.1049/cce:20060302.

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Grönroos, Päivi, Nur-E-Habiba, Kalle Salminen, Marja Nissinen, Tomi Tuomaala, Kim Miikki, Qiang Zhang et al. « Immunoassays Based on Hot Electron-Induced Electrochemiluminescence at Disposable Cell Chips with Printed Electrodes ». Sensors 19, no 12 (19 juin 2019) : 2751. http://dx.doi.org/10.3390/s19122751.

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Novel hot electron-emitting working electrodes and conventional counter electrodes were created by screen printing. Thus, low-cost disposable electrode chips for bioaffinity assays were produced to replace our older expensive electrode chips manufactured by manufacturing techniques of electronics from silicon or on glass chips. The present chips were created by printing as follows: (i) silver lines provided the electronic contacts, counter electrode and the bottom of the working electrode and counter electrode, (ii) the composite layer was printed on appropriate parts of the silver layer, and (iii) finally a hydrophobic ring was added to produce the electrochemical cell boundaries. The applicability of these electrode chips in bioaffinity assays was demonstrated by an immunoassay of human C-reactive protein (i) using Tb(III) chelate label displaying long-lived hot electron-induced electrochemiluminescence (HECL) and (ii) now for the first time fluorescein isothiocyanate (FITC) was utilized as an a low-cost organic label displaying a short-lived HECL in a real-world bioaffinity assay.
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Szu, Harold, Jung Kim et Insook Kim. « Live neural network formations on electronic chips ». Neurocomputing 6, no 5-6 (octobre 1994) : 551–64. http://dx.doi.org/10.1016/0925-2312(94)90006-x.

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Ivanov, Yuri D., Kristina A. Malsagova, Vladimir P. Popov, Tatyana O. Pleshakova, Andrey F. Kozlov, Rafael A. Galiullin, Ivan D. Shumov et al. « Nanoribbon-Based Electronic Detection of a Glioma-Associated Circular miRNA ». Biosensors 11, no 7 (13 juillet 2021) : 237. http://dx.doi.org/10.3390/bios11070237.

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Nanoribbon chips, based on “silicon-on-insulator” structures (SOI-NR chips), have been fabricated. These SOI-NR chips, whose surface was sensitized with covalently immobilized oligonucleotide molecular probes (oDNA probes), have been employed for the nanoribbon biosensor-based detection of a circular ribonucleic acid (circRNA) molecular marker of glioma in humans. The nucleotide sequence of the oDNA probes was complimentary to the sequence of the target oDNA. The latter represents a synthetic analogue of a glioma marker—NFIX circular RNA. In this way, the detection of target oDNA molecules in a pure buffer has been performed. The lowest concentration of the target biomolecules, detectable in our experiments, was of the order of ~10−17 M. The SOI-NR sensor chips proposed herein have allowed us to reveal an elevated level of the NFIX circular RNA in the blood of a glioma patient.
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Takei, Yusuke, Ken-ichi Nomura, Yoshinori Horii, Daniel Zymelka, Hirobumi Ushijima et Takeshi Kobayashi. « Fabrication of Simultaneously Implementing “Wired Face-Up and Face-Down Ultrathin Piezoresistive Si Chips” on a Film Substrate by Screen-Offset Printing ». Micromachines 10, no 9 (26 août 2019) : 563. http://dx.doi.org/10.3390/mi10090563.

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We realized the implementation of an ultrathin piezoresistive Si chip and stretchable printed wires on a flexible film substrate using simple screen-offset printing technology. This process does not require a special MEMS fabrication equipment and is applicable to face-up chips where electrodes are formed on the top surface of the chip, as well as to face-down chips where electrodes are formed on the bottom surface of the chip. This fabrication process is quite useful in the field of flexible hybrid electronics (FHE) as a method for mounting and wiring electronic components on a flexible substrate. In this study, we confirmed that face-up and face-down chips could be mounted on polyimide film tape. Furthermore, it was confirmed that the two types of chips could be simultaneously mounted even if they exist on the same substrate. Five-μm-thick piezoresistive Si chips were transferred and wired on a polyimide film tape using screen-offset printing, and a band-plaster type blood pulse sensor was fabricated. Moreover, we successfully demonstrated that the blood pulse could be measured with neck, inner elbow, wrist, and ankle.
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Jassim, Daniya Amer, et Taha A. Elwi. « Optical nano monopoles for interconnection electronic chips applications ». Optik 249 (janvier 2022) : 168142. http://dx.doi.org/10.1016/j.ijleo.2021.168142.

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Thèses sur le sujet "Electronic chips"

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Lee, Chieh-feng. « Packaging solution for VLSI electronic photonic chips ». Thesis, Massachusetts Institute of Technology, 2007. http://hdl.handle.net/1721.1/42155.

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Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Materials Science and Engineering, 2007.
Includes bibliographical references.
As the demand of information capacity grows, the adoption of optical technology will increase. The issue of resistance and capacitance is limiting the electronic transmission bandwidth while fiber optic delivers data at the speed of light and is only limited by scattering as well as absorption. Electronic-photonic convergence is needed for communication systems to meet the performance requirement. Hence, an increasing number of Very-Large-Scale Integration (VLSI) electronic photonic chips are going to be designed and utilized. However, packaging for the chip is one of the major challenges for optoelectronic industry to overcome due to its high cost and lack of standards. This thesis examines the trend in semiconductor technology and also in the package performance requirement. A transceiver platform to meet the future information capacity demand is proposed by reviewing several materials and devices of current state. Lastly, the package design is demonstrated with the analysis of cost, performance, and materials.
by Chieh-feng Lee.
M.Eng.
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Ributzka, Juergen. « Toward a software pipelining framework for many-core chips ». Access to citation, abstract and download form provided by ProQuest Information and Learning Company ; downloadable PDF file, 98 p, 2009. http://proquest.umi.com/pqdweb?did=1889024501&sid=1&Fmt=2&clientId=8331&RQT=309&VName=PQD.

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Sarkar, Souradip. « Multiple clock domain synchronization for network on chips ». Online access for everyone, 2007. http://www.dissertations.wsu.edu/Thesis/Fall2007/S_Sarkar_112907.pdf.

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Qi, Ji. « System-level design automation and optimisation of network-on-chips in terms of timing and energy ». Thesis, University of Southampton, 2015. https://eprints.soton.ac.uk/386210/.

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As system complexity constantly increases, traditional bus-based architectures are less adaptable to the increasing design demands. Specifically in on-chip digital system designs, Network-on-Chip (NoC) architectures are promising platforms that have distributed multi-core co-operation and inter-communication. Since the design cost and time cycles of NoC systems are growing rapidly with higher integration, systemlevel Design Automation (DA) techniques are used to abstract models at early design stages for functional validation and performance prediction. Yet precise abstractions and efficient simulations are critical challenges for modern DA techniques to improve the design efficiency. This thesis makes several contributions to address these challenges. We have firstly extended a backbone simulator, NIRGAM, to offer accurate system level models and performance estimates. A case study of developing a one-to-one transmission system using asynchronous FIFOs as buffers in both the NIRGAM simulator and a synthesised gate-level design is given to validate the model accuracy by comparing their power and timing performance. Then we have made a second contribution to improve DA techniques by proposing a novel method to efficiently emulate non-rectangular NoC topologies in NIRGAM and generating accurate energy and timing performance. Our proposed method uses time regulated models to emulate virtual non-rectangular topologies based on a regular Mesh. The performance accuracy of virtual topologies is validated by comparing with corresponding real NoC topologies. The third contribution of our research is a novel task-mapping scheme that generates optimal mappings to tile-based NoC networks with accurate performance prediction and increased execution speed. A novel Non-Linear Programming (NLP) based mapping problem has been formulated and solved by a modified Branch and Bound (BB) algorithm. The proposed method predicts the performance of optimised mappings and compares it with NIRGAM simulations for accuracy validation.
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Choi, Jinseong. « Modeling of power supply noise in large chips using the finite difference time domain method ». Diss., Georgia Institute of Technology, 2002. http://hdl.handle.net/1853/14977.

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Thacker, Hiren Dilipkumar. « Probe Modules for Wafer-Level Testing of Gigascale Chips with Electrical and Optical I/O Interconnects ». Diss., Georgia Institute of Technology, 2006. http://hdl.handle.net/1853/11597.

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The use of optical input/output (I/O) interconnects, in addition to electrical I/Os, is a promising approach for achieving high-bandwidth, chip-to-board communications required for future high-performance gigascale chip-based systems. While numerous efforts are underway to investigate the integration of optoelectronics and silicon microelectronics, virtually no work has been reported relating to testing of such chips. The objective of this research is to explore methods that enable wafer-level testing of gigascale chips having electrical and optical I/O interconnects. A major challenge in achieving this is to develop probe modules which would allow high-precision, temporary interconnection of a multitude of electrical and optical I/Os, in a chip-size area, to automated test equipment. A probe module would need to do this in a rapid, step-and-repeat manner across all the chips on the wafer. In this work, two candidate probe modules were devised, batch-fabricated on Si using microfabrication techniques, and successfully demonstrated. The first probe module consists of compliant electrical probes (10^3 probes/cm^2) fabricated alongside grating-in-waveguide optical probes. The second module consists of micro-opto-electro-mechanical-systems (MOEMS)-based microsocket probes (10^4 probes/cm^2) to interface a chip with polymer pillar-based electrical and optical I/Os. High-density through-wafer interconnects are an essential attribute in both probe substrates for transferring electrical and optical signals to the substrate back-side. Fabrication and characterization of metal-clad, metal-filled, and polymer-filled through-wafer interconnects as well as process integration with probe substrate fabrication are described and numerous possible redistribution schemes are explicated. Chips with optical and electrical I/Os are an emerging technology, and one that test engineers are likely to encounter in the near future. The contributions of this thesis are to help understand and address the issues relating to joint electrical and optical testing during manufacturing.
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Gdhaidh, Farouq A. S. « Heat Transfer Characteristics of Natural Convection within an Enclosure Using Liquid Cooling System ». Thesis, University of Bradford, 2015. http://hdl.handle.net/10454/7824.

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In this investigation, a single phase fluid is used to study the coupling between natural convection heat transfer within an enclosure and forced convection through computer covering case to cool the electronic chip. Two working fluids are used (water and air) within a rectangular enclosure and the air flow through the computer case is created by an exhaust fan installed at the back of the computer case. The optimum enclosure size configuration that keeps a maximum temperature of the heat source at a safe temperature level (85℃) is determined. The cooling system is tested for varying values of applied power in the range of 15−40𝑊. The study is based on both numerical models and experimental observations. The numerical work was developed using the commercial software (ANSYS-Icepak) to simulate the flow and temperature fields for the desktop computer and the cooling system. The numerical simulation has the same physical geometry as those used in the experimental investigations. The experimental work was aimed to gather the details for temperature field and use them in the validation of the numerical prediction. The results showed that, the cavity size variations influence both the heat transfer process and the maximum temperature. Furthermore, the experimental results ii compared favourably with those obtained numerically, where the maximum deviation in terms of the maximum system temperature, is within 3.5%. Moreover, it is seen that using water as the working fluid within the enclosure is capable of keeping the maximum temperature under 77℃ for a heat source of 40𝑊, which is below the recommended electronic chips temperature of not exceeding 85℃. As a result, the noise and vibration level is reduced. In addition, the proposed cooling system saved about 65% of the CPU fan power.
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Gdhaidh, Farouq Ali S. « Heat transfer characteristics of natural convection within an enclosure using liquid cooling system ». Thesis, University of Bradford, 2015. http://hdl.handle.net/10454/7824.

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In this investigation, a single phase fluid is used to study the coupling between natural convection heat transfer within an enclosure and forced convection through computer covering case to cool the electronic chip. Two working fluids are used (water and air) within a rectangular enclosure and the air flow through the computer case is created by an exhaust fan installed at the back of the computer case. The optimum enclosure size configuration that keeps a maximum temperature of the heat source at a safe temperature level (85°C) is determined. The cooling system is tested for varying values of applied power in the range of 15-40W. The study is based on both numerical models and experimental observations. The numerical work was developed using the commercial software (ANSYS-Icepak) to simulate the flow and temperature fields for the desktop computer and the cooling system. The numerical simulation has the same physical geometry as those used in the experimental investigations. The experimental work was aimed to gather the details for temperature field and use them in the validation of the numerical prediction. The results showed that, the cavity size variations influence both the heat transfer process and the maximum temperature. Furthermore, the experimental results ii compared favourably with those obtained numerically, where the maximum deviation in terms of the maximum system temperature, is within 3.5%. Moreover, it is seen that using water as the working fluid within the enclosure is capable of keeping the maximum temperature under 77°C for a heat source of 40W, which is below the recommended electronic chips temperature of not exceeding 85°C. As a result, the noise and vibration level is reduced. In addition, the proposed cooling system saved about 65% of the CPU fan power.
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Marusiak, David. « MOS CURRENT MODE LOGIC (MCML) ANALYSIS FOR QUIET DIGITAL CIRCUITRY AND CREATION OF A STANDARD CELL LIBRARY FOR REDUCING THE DEVELOPMENT TIME OF MIXED-SIGNAL CHIPS ». DigitalCommons@CalPoly, 2014. https://digitalcommons.calpoly.edu/theses/1363.

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Many modern digital systems use forms of CMOS logical implementation due to the straight forward design nature of CMOS logic and minimal device area since CMOS uses fewer transistors than other logic families. To achieve high-performance requirements in mixed-signal chip development and quiet, noiseless circuitry, this thesis provides an alternative toCMOSin the form of MOS Current Mode Logic (MCML). MCML dissipates constant current and does not produce noise during value changing in a circuit CMOS circuits do. CMOS logical networks switch during clock ticks and with every device switching, noise is created on the supply and ground to deal with the transitions. Creating a noiseless standard cell library with MCML allows use of circuitry that uses low voltage switching with 1.5V between logic levels in a quiet or mixed-signal environment as opposed to the full rail to rail swinging of CMOS logic. This allows cohesive implementation with analog circuitry on the same chip due to constant current and lower switching ranges not creating rail noise during digital switching. Standard cells allow for the Cadence tools to automatically generate circuits and Cadence serves as the development platform for the MCML standard cells. The theory surrounding MCML is examined along with current and future applications well-suited for MCML are researched and explored with the goal of highlighting valid candidate circuits for MCML. Inverters and NAND gates with varying current drives are developed to meet these specialized goals and are simulated to prove viability for quiet, mixed-signal applications. Analysis and results show that MCML is a superior implementation choice compared toCMOSfor high speed and mixed signal applications due to frequency independent power dissipation and lack of generated noise during operation. Noise results show rail current deviations of 50nA to 300nA during switching over an average operating current of 20µA to 80µA respectively. The multiple order of magnitude difference between noise and signal allow the MCML cells to dissipate constant power and thus perform with no noise added to a system. Additional simulated results of a 31-stage ring oscillator result in a frequency for MCML of 1.57GHz simulated versus the 150.35MHz that MOSIS tested on a fabricated 31-stage CMOS oscillator. The layouts designed for the standard cell library conform to existing On Semiconductor ami06 technology dimensions and allow for design of any logical function to be fabricated. The I/O signals of each cell operate at the same input and output voltage swings which allow seamless integration with each other for implementation in any logical configuration.
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Hansson, Martin. « Low-Power Multi-GHz Circuit Techniques for On-chip Clocking ». Licentiate thesis, Linköping : Linköping University, 2006. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-7545.

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Livres sur le sujet "Electronic chips"

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Mermet, Jean. Electronic Chips & Systems Design Languages. Boston, MA : Springer US, 2001.

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Jean-Michel, Mermet, dir. Electronic chips & systems design languages. Boston : Kluwer Academic Publishers, 2001.

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Mermet, Jean, dir. Electronic Chips & ; Systems Design Languages. Boston, MA : Springer US, 2001. http://dx.doi.org/10.1007/978-1-4757-3326-6.

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Vajda, András. Programming many-core chips. New York, NY : Springer, 2011.

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A, Harper Charles, dir. Electronic assembly fabrication : Chips, circuit boards, packages, and components. New York : McGraw-Hill, 2002.

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Vajda, András. Programming many-core chips. New York, NY : Springer, 2011.

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Salinas, David. Stresses in solder joints of electronic packages. Monterey, Calif : Naval Postgraduate School, 1991.

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service), SpringerLink (Online, dir. Focal-Plane Sensor-Processor Chips. New York, NY : Springer Science+Business Media, LLC, 2011.

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In the matter of certain GPS chips, associated software and systems, and products containing same : Investigation no. 337-TA-596. Washington, DC : U.S. International Trade Commission, 2010.

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Tong, Ho-Ming. Advanced Flip Chip Packaging. Boston, MA : Springer US, 2013.

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Chapitres de livres sur le sujet "Electronic chips"

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Rosin, David P. « Autonomous Boolean Networks on Electronic Chips ». Dans Dynamics of Complex Autonomous Boolean Networks, 25–33. Cham : Springer International Publishing, 2015. http://dx.doi.org/10.1007/978-3-319-13578-6_3.

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K., Mathew V., et Tapano Kumar Hotta. « Introduction to Electronic Cooling ». Dans Hybrid Genetic Optimization for IC Chips Thermal Control, 1–7. Boca Raton : Chapman and Hall/CRC, 2022. http://dx.doi.org/10.1201/9781003188506-1.

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Christen, Ernst, et Kenneth Bakalar. « Library Development Using the VHDL-AMS Language ». Dans Electronic Chips & ; Systems Design Languages, 5–16. Boston, MA : Springer US, 2001. http://dx.doi.org/10.1007/978-1-4757-3326-6_1.

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Kumar, Rajesh. « Using SDL to Model Reactive Embedded System in a Co-Design Environment ». Dans Electronic Chips & ; Systems Design Languages, 121–30. Boston, MA : Springer US, 2001. http://dx.doi.org/10.1007/978-1-4757-3326-6_10.

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Plöger, P. G., Reinhard Budde et Karl H. Sylla. « A Synchronous Object-Oriented Design Flow for Embedded Applications ». Dans Electronic Chips & ; Systems Design Languages, 131–42. Boston, MA : Springer US, 2001. http://dx.doi.org/10.1007/978-1-4757-3326-6_11.

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Bjuréus, Per, et Axel Jantsch. « Heterogeneous System-Level Cosimulation with SDL and Matlab ». Dans Electronic Chips & ; Systems Design Languages, 145–57. Boston, MA : Springer US, 2001. http://dx.doi.org/10.1007/978-1-4757-3326-6_12.

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Moser, Vincent, Alexis Boegli, Hans Peter Amann et Fausto Pellandini. « VHDL-based HW/SW Cosimulation of Microsystems ». Dans Electronic Chips & ; Systems Design Languages, 159–68. Boston, MA : Springer US, 2001. http://dx.doi.org/10.1007/978-1-4757-3326-6_13.

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Bauer, Matthias, Wolfgang Ecker et Andreas Zinn. « Modeling Interrupts for HW/SW Co-Simulation based on a VHDL/C Coupling ». Dans Electronic Chips & ; Systems Design Languages, 169–78. Boston, MA : Springer US, 2001. http://dx.doi.org/10.1007/978-1-4757-3326-6_14.

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Jantsch, Axel, Shashi Kumar, Ingo Sander, Bengt Svantesson, Johnny Öberg, Ahmed Hemani, Peeter Ellervee et Mattias O’Nils. « A Comparison of Six Languages for System Level Description of Telecom Applications ». Dans Electronic Chips & ; Systems Design Languages, 181–92. Boston, MA : Springer US, 2001. http://dx.doi.org/10.1007/978-1-4757-3326-6_15.

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Cook, Francis, Nathan Messer et Andy Carpenter. « High Level Modelling in SDL and VHDL+ ». Dans Electronic Chips & ; Systems Design Languages, 193–203. Boston, MA : Springer US, 2001. http://dx.doi.org/10.1007/978-1-4757-3326-6_16.

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Actes de conférences sur le sujet "Electronic chips"

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Lentine, A. L., K. W. Goossen, J. A. Walker, J. E. Cunningham, W. Y. Jan, T. K. Woodward, A. V. Krishnamoorthy et al. « High throughput opto-electronic VLSI switching chips ». Dans Spatial Light Modulators. Washington, D.C. : Optica Publishing Group, 1997. http://dx.doi.org/10.1364/slmo.1997.sma.3.

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As the demand for telecommunications services continues to increase, the need to switch large bandwidths of data becomes important. While purely electronic solutions are possible, photonic solutions, using the integration of electronics with optical I/O (smart pixels), provides the potential for smaller physical volume, lower latency, lower power dissipation, and lower cost. We describe initial results from two opto-electronic switching chips, one with 1024 differential optical inputs and 1024 differential optical outputs with individual channels tested above 600 Mb/s and a second with 512 differential optical inputs and outputs with individual channels tested up to 900 Mb/s. The technology for the chip consists of flip-chip bonding of 850 nm GaAs/AlGaAs multiple quantum well (MQW) detectors and modulators onto silicon CMOS with substrate removal to allow access to the optical devices [1]
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Wee, Lo Chea, Tan Sze Yee, Gan Sue Yin et Goh Cin Sheng. « Investigation of Die Tilting of Packages with Single and Multi-chips ». Dans ISTFA 2018. ASM International, 2018. http://dx.doi.org/10.31399/asm.cp.istfa2018p0429.

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Abstract Advanced package technology often includes multi-chips in one package to accommodate the technology demand on size & functionality. Die tilting leads to poor device performance for all kinds of multi-chip packages such as chip by chip (CbC), chip on chip (CoC), and the package with both CbC and CoC. Traditional die tilting measured by optical microscopy and scanning electron microscopy has capability issue due to wave or electron beam blocking at area of interest by electronic components nearby. In this paper, the feasibility of using profilemeter to investigate die tilting in single and multi-chips is demonstrated. Our results validate that the profilemeter is the most profound metrology for die tilting analysis especially on multi-chip packages, and can achieve an accuracy of <2μm comparable to SEM.
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Wang, Peng, F. Patrick McCluskey et Avram Bar-Cohen. « Isothermalization of an IGBT Power Electronic Chip ». Dans ASME 2010 International Mechanical Engineering Congress and Exposition. ASMEDC, 2010. http://dx.doi.org/10.1115/imece2010-41019.

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Rapid increases in the power ratings and continued miniaturization of power electronic semiconductor devices have pushed chip heat fluxes well beyond the range of conventional thermal management techniques. The heat flux of power electronic chips for hybrid electric vehicles is now at the level of 100 to 150W/cm2 and is projected to increase to 500 W/cm2 in next generation vehicles. Such heat fluxes lead to higher and less uniform IGBT chip temperature, significantly degrading the device performance and system reliability. Maintaining the maximum temperature below a specified limit, while isothermalizing the surface of the chip, have become critical issues for thermal management of power electronics. In this work, a hybrid cooling system design, which combines microchannel liquid cooling and thermoelectric solid-state cooling, is proposed for thermal management of a 10mm × 10mm IGBT chip. The microchannel heat sink is used for global cooling of the chip while the embedded thermo-electric cooler is employed for isothermalization of the chip. A detailed package level 3D thermal model is developed to explore the potential application of this concept, with an attention focused on isothermalization and temperature reduction of IGBT chip associated with variations in thermoelectric cooler sizes, thermoelectric materials, cooling system designs, and trench structures in the DBC substrate. It is found that a thin-film superlattice TEC can deliver a superior cooling performance by eliminating more than 90% of the temperature non-uniformity on 100∼200 W/cm2 IGBT chips.
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Erdahl, Dathan S., Sheng Liu et I. Charles Ume. « Application of a Novel Flip Chip Solder Joint Inspection System to Chips on an FR-4 Substrate ». Dans ASME 2000 International Mechanical Engineering Congress and Exposition. American Society of Mechanical Engineers, 2000. http://dx.doi.org/10.1115/imece2000-2262.

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Abstract Because the trend in electronic interconnection technology is toward the development of solder bump technologies, that include flip chips, chip scale packages, multi-chip modules (MCMs), and ball grid array (BGA) packages, solder bump inspection methods must be developed to allow rapid, accurate, and high resolution on-line inspection of joint quality. Although traditional methods can detect some manufacturing defects, they do not actually test the mechanical quality of the connection. A novel solder-joint inspection system has been developed based on laser ultrasound and interferometric techniques. A pulsed laser generates ultrasound on the chip’s surface and the whole chip is excited into vibration modes. An interferometer is used to measure the vibration displacement of the chip’s surface. Solder joints with different qualities cause different vibration responses, acting as constraints on the system. The system was used to inspect the quality of solder joints on a group of flip chips mounted on FR-4 substrates, and the results show the ability of the system to detect defects such as missing solder balls, cracked chips, and gross misalignment.
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Bodson, M. « Electronic chips for electric motor control ». Dans Proceedings of 16th American CONTROL Conference. IEEE, 1997. http://dx.doi.org/10.1109/acc.1997.611796.

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Hashish, Mohamed. « Singulation of Electronic Packages With Abrasive Waterjets ». Dans ASME 2005 International Mechanical Engineering Congress and Exposition. ASMEDC, 2005. http://dx.doi.org/10.1115/imece2005-79659.

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Abrasive waterjets were used for the first time to commercially singulate electronic chips such as those used for flash memory cards found in digital cameras, cell phones, and USB storage devices. Cutting these components requires high cutting speed, high edge quality, accuracy, and precision. For example, a minimal accuracy needed is about 0.1-mm and a minimum Cpk of 1.33. A relatively small AWJ (~ 0.38 mm) was successfully used to accurately cut chips at speeds of 20 mm/s to 60 mm/s. It was determined that the use of machine vision is critical to meeting the accuracy requirements. The cutting process consisted of piercing starting holes and then cutting shaped pattern cuts to contour the chip components. Drilling holes was performed without delamination and the cutting speed was optimized to meet the intricate chip geometry. Because of the relatively high volume of components to be cut, requiring around the clock duty, process and machine reliability are of critical importance. This paper discusses the results and observation of the cutting process as well as the performance of the system.
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Shirota, Yusuke, Shiyo Yoshimura et Tatsunori Kanai. « Electronic Paper Display update scheduler for extremely low power non-volatile embedded systems ». Dans 2015 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS XVIII). IEEE, 2015. http://dx.doi.org/10.1109/coolchips.2015.7158661.

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Brusberg, Lars, Jürgen Matthies, Jason R. Grenier, Jeffrey S. Clark, Betsy J. Johnson et Chad C. Terwilliger. « Slim Push-Pull Fiber Array Connector for Optical Chips ». Dans Optical Fiber Communication Conference. Washington, D.C. : Optica Publishing Group, 2023. http://dx.doi.org/10.1364/ofc.2023.th1a.4.

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Bhowmik, H., et K. W. Tou. « Air Cooling Study of Transient Natural Convection Heat Transfer From Simulated Electronic Chips ». Dans ASME 2004 International Mechanical Engineering Congress and Exposition. ASMEDC, 2004. http://dx.doi.org/10.1115/imece2004-59503.

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Experiments are performed to study the heat transfer characteristics during the power-on transient period from an array of 4 × 1 discrete heat sources in a vertical rectangular channel using air as the working fluid. The heat flux ranges from 1000 W/m2 to 5000 W/m2. For 2 mm protrusion of the heater, the effect of heat fluxes and chip numbers are investigated and observed that the transient Nul strongly depends on the number of chips. Correlations are presented for individual chips as well as for overall data in the transient regime.
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Tuzla, Kemal, A. F. Cokmez-Tuzla, T. J. Crowley et John C. Chen. « COOLING OF ELECTRONIC CHIPS IN LIQUID NITROGEN ». Dans International Heat Transfer Conference 9. Connecticut : Begellhouse, 1990. http://dx.doi.org/10.1615/ihtc9.470.

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Rapports d'organisations sur le sujet "Electronic chips"

1

Maren, Aliianna J. Signal Processing Chips/Electronics. Fort Belvoir, VA : Defense Technical Information Center, novembre 1994. http://dx.doi.org/10.21236/ada298833.

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Patel, Sanjay V. Orthogonal Chip Based Electronic Sensors for Chemical Agents. Fort Belvoir, VA : Defense Technical Information Center, avril 2012. http://dx.doi.org/10.21236/ada564305.

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Alan Ludwiszewski. Silicon Based Solid Oxide Fuel Cell Chip for Portable Consumer Electronics -- Final Technical Report. Office of Scientific and Technical Information (OSTI), juin 2009. http://dx.doi.org/10.2172/958075.

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Scanning electron microscope analyses of four core chips from the following four North Slope wells : Long Island #1 ; Alaska State F-1 ; Topagoruk Test Well #1 ; and Colville #1. Alaska Division of Geological & Geophysical Surveys, 1988. http://dx.doi.org/10.14509/19234.

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