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Lee, Chieh-feng. « Packaging solution for VLSI electronic photonic chips ». Thesis, Massachusetts Institute of Technology, 2007. http://hdl.handle.net/1721.1/42155.
Texte intégralRésumé :
Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Materials Science and Engineering, 2007.Includes bibliographical references.
As the demand of information capacity grows, the adoption of optical technology will increase. The issue of resistance and capacitance is limiting the electronic transmission bandwidth while fiber optic delivers data at the speed of light and is only limited by scattering as well as absorption. Electronic-photonic convergence is needed for communication systems to meet the performance requirement. Hence, an increasing number of Very-Large-Scale Integration (VLSI) electronic photonic chips are going to be designed and utilized. However, packaging for the chip is one of the major challenges for optoelectronic industry to overcome due to its high cost and lack of standards. This thesis examines the trend in semiconductor technology and also in the package performance requirement. A transceiver platform to meet the future information capacity demand is proposed by reviewing several materials and devices of current state. Lastly, the package design is demonstrated with the analysis of cost, performance, and materials.
by Chieh-feng Lee.
M.Eng.
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Ributzka, Juergen. « Toward a software pipelining framework for many-core chips ». Access to citation, abstract and download form provided by ProQuest Information and Learning Company ; downloadable PDF file, 98 p, 2009. http://proquest.umi.com/pqdweb?did=1889024501&sid=1&Fmt=2&clientId=8331&RQT=309&VName=PQD.
Texte intégral
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Sarkar, Souradip. « Multiple clock domain synchronization for network on chips ». Online access for everyone, 2007. http://www.dissertations.wsu.edu/Thesis/Fall2007/S_Sarkar_112907.pdf.
Texte intégral
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Qi, Ji. « System-level design automation and optimisation of network-on-chips in terms of timing and energy ». Thesis, University of Southampton, 2015. https://eprints.soton.ac.uk/386210/.
Texte intégralRésumé :
As system complexity constantly increases, traditional bus-based architectures are less adaptable to the increasing design demands. Specifically in on-chip digital system designs, Network-on-Chip (NoC) architectures are promising platforms that have distributed multi-core co-operation and inter-communication. Since the design cost and time cycles of NoC systems are growing rapidly with higher integration, systemlevel Design Automation (DA) techniques are used to abstract models at early design stages for functional validation and performance prediction. Yet precise abstractions and efficient simulations are critical challenges for modern DA techniques to improve the design efficiency. This thesis makes several contributions to address these challenges. We have firstly extended a backbone simulator, NIRGAM, to offer accurate system level models and performance estimates. A case study of developing a one-to-one transmission system using asynchronous FIFOs as buffers in both the NIRGAM simulator and a synthesised gate-level design is given to validate the model accuracy by comparing their power and timing performance. Then we have made a second contribution to improve DA techniques by proposing a novel method to efficiently emulate non-rectangular NoC topologies in NIRGAM and generating accurate energy and timing performance. Our proposed method uses time regulated models to emulate virtual non-rectangular topologies based on a regular Mesh. The performance accuracy of virtual topologies is validated by comparing with corresponding real NoC topologies. The third contribution of our research is a novel task-mapping scheme that generates optimal mappings to tile-based NoC networks with accurate performance prediction and increased execution speed. A novel Non-Linear Programming (NLP) based mapping problem has been formulated and solved by a modified Branch and Bound (BB) algorithm. The proposed method predicts the performance of optimised mappings and compares it with NIRGAM simulations for accuracy validation.
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Choi, Jinseong. « Modeling of power supply noise in large chips using the finite difference time domain method ». Diss., Georgia Institute of Technology, 2002. http://hdl.handle.net/1853/14977.
Texte intégral
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Thacker, Hiren Dilipkumar. « Probe Modules for Wafer-Level Testing of Gigascale Chips with Electrical and Optical I/O Interconnects ». Diss., Georgia Institute of Technology, 2006. http://hdl.handle.net/1853/11597.
Texte intégralRésumé :
The use of optical input/output (I/O) interconnects, in addition to electrical I/Os, is a promising approach for achieving high-bandwidth, chip-to-board communications required for future high-performance gigascale chip-based systems. While numerous efforts are underway to investigate the integration of optoelectronics and silicon microelectronics, virtually no work has been reported relating to testing of such chips. The objective of this research is to explore methods that enable wafer-level testing of gigascale chips having electrical and optical I/O interconnects. A major challenge in achieving this is to develop probe modules which would allow high-precision, temporary interconnection of a multitude of electrical and optical I/Os, in a chip-size area, to automated test equipment. A probe module would need to do this in a rapid, step-and-repeat manner across all the chips on the wafer. In this work, two candidate probe modules were devised, batch-fabricated on Si using microfabrication techniques, and successfully demonstrated. The first probe module consists of compliant electrical probes (10^3 probes/cm^2) fabricated alongside grating-in-waveguide optical probes. The second module consists of micro-opto-electro-mechanical-systems (MOEMS)-based microsocket probes (10^4 probes/cm^2) to interface a chip with polymer pillar-based electrical and optical I/Os. High-density through-wafer interconnects are an essential attribute in both probe substrates for transferring electrical and optical signals to the substrate back-side. Fabrication and characterization of metal-clad, metal-filled, and polymer-filled through-wafer interconnects as well as process integration with probe substrate fabrication are described and numerous possible redistribution schemes are explicated. Chips with optical and electrical I/Os are an emerging technology, and one that test engineers are likely to encounter in the near future. The contributions of this thesis are to help understand and address the issues relating to joint electrical and optical testing during manufacturing.
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Gdhaidh, Farouq A. S. « Heat Transfer Characteristics of Natural Convection within an Enclosure Using Liquid Cooling System ». Thesis, University of Bradford, 2015. http://hdl.handle.net/10454/7824.
Texte intégralRésumé :
In this investigation, a single phase fluid is used to study the coupling between natural convection heat transfer within an enclosure and forced convection through computer covering case to cool the electronic chip. Two working fluids are used (water and air) within a rectangular enclosure and the air flow through the computer case is created by an exhaust fan installed at the back of the computer case. The optimum enclosure size configuration that keeps a maximum temperature of the heat source at a safe temperature level (85℃) is determined. The cooling system is tested for varying values of applied power in the range of 15−40𝑊.
The study is based on both numerical models and experimental observations. The numerical work was developed using the commercial software (ANSYS-Icepak) to simulate the flow and temperature fields for the desktop computer and the cooling system. The numerical simulation has the same physical geometry as those used in the experimental investigations. The experimental work was aimed to gather the details for temperature field and use them in the validation of the numerical prediction.
The results showed that, the cavity size variations influence both the heat transfer process and the maximum temperature. Furthermore, the experimental results
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compared favourably with those obtained numerically, where the maximum deviation in terms of the maximum system temperature, is within 3.5%. Moreover, it is seen that using water as the working fluid within the enclosure is capable of keeping the maximum temperature under 77℃ for a heat source of 40𝑊, which is below the recommended electronic chips temperature of not exceeding 85℃. As a result, the noise and vibration level is reduced. In addition, the proposed cooling system saved about 65% of the CPU fan power.
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Gdhaidh, Farouq Ali S. « Heat transfer characteristics of natural convection within an enclosure using liquid cooling system ». Thesis, University of Bradford, 2015. http://hdl.handle.net/10454/7824.
Texte intégralRésumé :
In this investigation, a single phase fluid is used to study the coupling between natural convection heat transfer within an enclosure and forced convection through computer covering case to cool the electronic chip. Two working fluids are used (water and air) within a rectangular enclosure and the air flow through the computer case is created by an exhaust fan installed at the back of the computer case. The optimum enclosure size configuration that keeps a maximum temperature of the heat source at a safe temperature level (85°C) is determined. The cooling system is tested for varying values of applied power in the range of 15-40W. The study is based on both numerical models and experimental observations. The numerical work was developed using the commercial software (ANSYS-Icepak) to simulate the flow and temperature fields for the desktop computer and the cooling system. The numerical simulation has the same physical geometry as those used in the experimental investigations. The experimental work was aimed to gather the details for temperature field and use them in the validation of the numerical prediction. The results showed that, the cavity size variations influence both the heat transfer process and the maximum temperature. Furthermore, the experimental results ii compared favourably with those obtained numerically, where the maximum deviation in terms of the maximum system temperature, is within 3.5%. Moreover, it is seen that using water as the working fluid within the enclosure is capable of keeping the maximum temperature under 77°C for a heat source of 40W, which is below the recommended electronic chips temperature of not exceeding 85°C. As a result, the noise and vibration level is reduced. In addition, the proposed cooling system saved about 65% of the CPU fan power.
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Marusiak, David. « MOS CURRENT MODE LOGIC (MCML) ANALYSIS FOR QUIET DIGITAL CIRCUITRY AND CREATION OF A STANDARD CELL LIBRARY FOR REDUCING THE DEVELOPMENT TIME OF MIXED-SIGNAL CHIPS ». DigitalCommons@CalPoly, 2014. https://digitalcommons.calpoly.edu/theses/1363.
Texte intégralRésumé :
Many modern digital systems use forms of CMOS logical implementation due to the straight forward design nature of CMOS logic and minimal device area since CMOS uses fewer transistors than other logic families. To achieve high-performance requirements in mixed-signal chip development and quiet, noiseless circuitry, this thesis provides an alternative toCMOSin the form of MOS Current Mode Logic (MCML). MCML dissipates constant current and does not produce noise during value changing in a circuit CMOS circuits do. CMOS logical networks switch during clock ticks and with every device switching, noise is created on the supply and ground to deal with the transitions. Creating a noiseless standard cell library with MCML allows use of circuitry that uses low voltage switching with 1.5V between logic levels in a quiet or mixed-signal environment as opposed to the full rail to rail swinging of CMOS logic. This allows cohesive implementation with analog circuitry on the same chip due to constant current and lower switching ranges not creating rail noise during digital switching. Standard cells allow for the Cadence tools to automatically generate circuits and Cadence serves as the development platform for the MCML standard cells.
The theory surrounding MCML is examined along with current and future applications well-suited for MCML are researched and explored with the goal of highlighting valid candidate circuits for MCML. Inverters and NAND gates with varying current drives are developed to meet these specialized goals and are simulated to prove viability for quiet, mixed-signal applications. Analysis and results show that MCML is a superior implementation choice compared toCMOSfor high speed and mixed signal applications due to frequency independent power dissipation and lack of generated noise during operation. Noise results show rail current deviations of 50nA to 300nA during switching over an average operating current of 20µA to 80µA respectively. The multiple order of magnitude difference between noise and signal allow the MCML cells to dissipate constant power and thus perform with no noise added to a system. Additional simulated results of a 31-stage ring oscillator result in a frequency for MCML of 1.57GHz simulated versus the 150.35MHz that MOSIS tested on a fabricated 31-stage CMOS oscillator. The layouts designed for the standard cell library conform to existing On Semiconductor ami06 technology dimensions and allow for design of any logical function to be fabricated. The I/O signals of each cell operate at the same input and output voltage swings which allow seamless integration with each other for implementation in any logical configuration.
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Hansson, Martin. « Low-Power Multi-GHz Circuit Techniques for On-chip Clocking ». Licentiate thesis, Linköping : Linköping University, 2006. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-7545.
Texte intégral
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Frey, Alexander [Verfasser]. « Fully Electronic CMOS DNA Sensor Chip / Alexander Frey ». Aachen : Shaker, 2011. http://d-nb.info/1080765115/34.
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Tabasnikov, Aleksandr. « Development of a high temperature sensor suitable for post-processed integration with electronics ». Thesis, University of Edinburgh, 2018. http://hdl.handle.net/1842/28971.
Texte intégralRésumé :
Integration of sensors and silicon-based electronics for harsh environment applications is driven by the automotive industry and the maturity of semiconductor processes that allow embedding sensitive elements onto the same chip without sacrificing the performance and integrity of the electronics. Sensor devices post-processed on top of electronics by surface micromachining allow the addition of extra functionality to the fabricated ICs and creating a sensor system without significant compromise of performance. Smart sensors comprised of sensing structures integrated with silicon carbide-based electronics are receiving attention from more industries, such as aerospace, defense and energy, due to their ability to operate in very demanding conditions. This thesis describes the design and implementation of a novel, integrated thin film temperature sensor that uses a half-bridge arrangement to measure thin film platinum sensitive elements. Processes have been developed to fabricate temperature insensitive thin film tantalum nitride resistors which can be combined with the platinum elements to form the temperature transducing bridge. This circuit was designed to be integrated with an existing silicon carbide-based instrumentation amplifier by post-CMOS processing and to be initially connected to the bond pads of the amplifier input and output ports. Thin films fabricated using the developed TaN and Pt processes have been characterized using resistive test structures and crystallographic measurements of blanket thin film layer samples, and the relationship between the measurement results obtained has been analyzed. An initial demonstration of temperature sensing was performed using tantalum nitride and platinum thin film resistor element chips which were fabricated on passivated silicon substrates and bonded into high temperature packages. The bridge circuit was implemented by external connections through a printed circuit board and the bridge output was connected to a discrete instrumentation amplifier to mimic the integrated amplifier. The temperature response of the circuit measured at the output of the amplifier was found to have sensitivity of 844 μV·°C–1 over the temperature range of 25 to 100 °C. Two integrated microfabrication process flows were evaluated in this work. The initial process provided a very low yield for contact resistance structures between TaN and Pt layers, which highlighted problems with the thin film platinum deposition process. Multiple improvement options have been identified among which removal of the dielectric layer separating TaN and Pt layers and thicker Pt film were considered and a redesign of both layout and the process flow has resulted in improved yield of platinum features produced directly on top of TaN features. Temperature sensitivity of the integrated sensor devices was found to depend significantly on parasitic elements produced by thin film platinum step coverage, the values of which were measured by a set of resistive test structures. A new microfabrication design has enabled the production of a group of integrated temperature sensors that had a sensitivity of 150.84 μV·°C–1 in the temperature range between 25 and 200 °C on one of the fabricated wafers while the best fabricated batch of sensors had a sensitivity of 1079.2 μV·°C–1.
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Bengtsson, Carl Johan. « SmartMedia-controller på chip ». Thesis, Linköping University, Department of Electrical Engineering, 2002. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-1127.
Texte intégralRésumé :
This report deals with the design of a controller for SmartMedia™ flash memory cards, based on a hardware description found in the SmartMedia™ Interface Library - SMIL.
The design was made on logic gate level, using standard cells in OrCAD Capture. After simulation of the design in PSpice A/D, it was exported as an EDIF netlist, which was used to make a chip layout in L-Edit, a layout tool for making integrated circuits. The layout was made using a method called Standard Place and Route - SPR, where the layout tool places standard cells from a library and connects them according to the EDIF netlist.
A netlist which could be simulated in PSpice was extracted from the finished chip layout to verify that the function of the design was the same as before the transition from schematic to layout.
The standard cells in the library used to make the chip layout have to meet certain criteria in order for both SPR and extraction to work and this is also discussed.
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Yeo, Hyunwook. « Stress Analysis for Chip Scale Packages with Embedded Active Devices under Thermal Cycling ». PDXScholar, 2014. http://pdxscholar.library.pdx.edu/open_access_etds/1782.
Texte intégralRésumé :
One of the main challenges in the electronics manufacturing and packaging development is how to integrate more functions inside the same or even smaller size. To meet the demand for higher integration, the interest toward passive and active component embedding has been increasing during the past few years. One of the main reasons for the growing interest toward embedded active components, in addition to demand for higher packaging density, is the need for better electrical performance of the component assemblies. However, it is little known how embedded IC and passives affect the reliability of IC packaging.
Solder joints have been used in the electronic industry as both structural and electrical interconnections between electronic packages and printed circuit boards (PCB). When solder joints are under thermal cyclic loading, mismatch in coefficients of thermal expansion (CTE) between the printed circuit boards and the solder balls creates thermal strains and stresses on the joints, which may finally result in cracking. Consequently, the mechanical interconnection is lost, leading to electrical failures (such as hard/intermittent open, parametric failure), which in turn causes malfunction of the circuit or whole system.
When a die is embedded into a substrate, Young's modulus of the die is larger than one of the core of the substrate and the CTEs of the die is smaller than those of the substrate. As a result, mismatch in coefficients of thermal expansions (CTE) between the substrate with the embedded device and the solder balls may increase.
In the present study, the stress of chip scale packages (CSP) with an embedded die under thermal cycling conditions is evaluated using the finite element method. The viscoplastic model for solders including matrix dislocation mechanism and grain boundary sliding model developed by Yi et al. (2002) is employed.
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Coapes, Graeme. « Neural networks-on-chip for hybrid bio-electronic systems ». Thesis, University of Newcastle upon Tyne, 2016. http://hdl.handle.net/10443/3478.
Texte intégralRésumé :
By modelling the brains computation we can further our understanding of its function and develop novel treatments for neurological disorders. The brain is incredibly powerful and energy e cient, but its computation does not t well with the traditional computer architecture developed over the previous 70 years. Therefore, there is growing research focus in developing alternative computing technologies to enhance our neural modelling capability, with the expectation that the technology in itself will also bene t from increased awareness of neural computational paradigms. This thesis focuses upon developing a methodology to study the design of neural computing systems, with an emphasis on studying systems suitable for biomedical experiments. The methodology allows for the design to be optimized according to the application. For example, di erent case studies highlight how to reduce energy consumption, reduce silicon area, or to increase network throughput. High performance processing cores are presented for both Hodgkin-Huxley and Izhikevich neurons incorporating novel design features. Further, a complete energy/area model for a neural-network-on-chip is derived, which is used in two exemplar case-studies: a cortical neural circuit to benchmark typical system performance, illustrating how a 65,000 neuron network could be processed in real-time within a 100mW power budget; and a scalable highperformance processing platform for a cerebellar neural prosthesis. From these case-studies, the contribution of network granularity towards optimal neural-network-on-chip performance is explored.
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Tang, Zhenming. « Interfacial reliability of Pb-free flip-chip BGA package ». Diss., Online access via UMI:, 2008.
Trouver le texte intégralRésumé :
Thesis (Ph. D.)--State University of New York at Binghamton, Thomas J. Watson School of Engineering and Applied Science, Department of Mechanical Engineering, 2008.Includes bibliographical references.
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Llopart, Cudié Xavier. « Design and characterization of 64K pixels chips working in single photon processing mode ». Doctoral thesis, Mittuniversitetet, Institutionen för informationsteknologi och medier, 2007. http://urn.kb.se/resolve?urn=urn:nbn:se:miun:diva-45.
Texte intégralRésumé :
Progress in CMOS technology and in fine pitch bump bonding has made possible the development of high granularity single photon counting detectors for X-ray imaging. This thesis studies the design and characterization of three pulse processing chips with 65536 square pixels of 55 μm x 55 μm designed in a commercial 0.25 μm 6-metal CMOS technology. The 3 chips share the same architecture and dimensions and are named Medipix2, Mpix2MXR20 and Timepix. The Medipix2 chip is a pixel detector readout chip consisting of 256 x 256 identical elements, each working in single photon counting mode for positive or negative input charge signals. The preamplifier feedback provides compensation for detector leakage current on a pixel by pixel basis. Two identical pulse height discriminators are used to define an energy window. Every event falling inside the energy window is counted with a 13-bit pseudo-random counter. The counter logic, based in a shift register, also behaves as the input/output register for the pixel. Each cell also has an 8-bit configuration register which allows masking, test-enabling and 3-bit individual threshold adjust for each discriminator. The chip can be configured in serial mode and readout either serially or in parallel. Measurements show an electronic noise ~160 e- rms with a gain of ~9 mV/ke-. The threshold spread after equalization of ~120 e- rms brings the full chip minimum detectable charge to ~1100 e-. The analog static power consumption is ~8 μW per pixel with Vdda=2.2 V. The Mpix2MXR20 is an upgraded version of the Medipix2. The main changes in the pixel consist of: an improved tolerance to radiation, improved pixel to pixel threshold uniformity, and a 14-bit counter with overflow control. The chip periphery includes new threshold DACs with smaller step size, improved linearity, and better temperature dependence. Timepix is an evolution of the Mpix2MXR20 which provides independently in each pixel information of arrival time, time-over-threshold or event counting. Timepix uses as a time reference an external clock (Ref_Clk) up to 100 MHz which is distributed all over the pixel matrix during acquisition mode. The preamplifier is improved and there is a single discriminator with 4-bit threshold adjustment in order to reduce the minimum detectable charge limit. Measurements show an electrical noise ~100 e- rms and a gain of ~16.5 mV/ke-. The threshold spread after equalization of ~35 e- rms brings the full chip minimum detectable charge either to ~650 e- with a naked chip (i.e. gas detectors) or ~750 e- when bump-bonded to a detector. The pixel static power consumption is ~13.5 μW per pixel with Vdda=2.2 V and Ref_Clk=80 MHz. This family of chips have been used for a wide variety of applications. During these studies a number of limitations have come to light. Among those are limited energy resolution and surface area. Future developments, such as Medipix3, will aim to address those limitations by carefully exploiting developments in microelectronics.Framstegen inom CMOS-teknologin och tekniken för bump bondning har möjliggjort utveckling av högupplösande bilddetektorer för detektering av enskilda röntgenfotoner eller laddade partiklar. Denna avhandling behandlar design och karakterisering av tre pulsräknande utläsningskretsar med 65536 kvadratiska bildelement med storleken 55 x 55 um2. De tre kretsarna, benämnda Medipix2, Mpix2MXR20 och Timepix, delar samma arkitektur och dimensioner. Medipix2 är en utläsningskrets för avbildning med 256 x 256 identiska bildelement som räknar enskilda fotoner utgående från positiva eller negativa laddningspulser. Förförstärkarens återkoppling kompenserar individuellt för läckströmmen i varje bildelement. Ett energifönster kan definieras med hjälp av två identiska diskriminatorkretsar. Varje händelse som faller inom energifönstret räknas i en 13-bitars pseudo-random räknare. Räknaren, utformad som ett skiftregister, fungerar också som in/utregister för varje bildelement. Kretsen kan läsas ut antingen seriellt eller parallellt. Det elektroniska bruset har uppmätts till ~160 e- rms vid en förstärkning av ~9 mV/ke-. Spridningen i tröskelspänning efter justering är ~120 e- rms vilket ger en minsta detekterbar laddningspuls över hela kretsen på ~1100 e-. Den statiska effektförbrukningen i del analoga delen är ~8 mW per bildelement vid Vdda=2,2 V. Mpix2MXR20 är en uppdaterad version av Medipix2. De huvudsakliga förändringarna är: bättre strålningshärdighet, jämnare tröskelvärden och en 14- bitsräknare med overflow. Periferin innehåller också nya DA-omvandlare med mindre steg, förbättrad linjäritet och mindre temperaturberoende. Timepix är en vidareutveckling av Mpix2MXR20 som medger detektering av ankomsttid, time-over-threshold eller pulsräkning individuellt i varje bildelement. Timepix utnyttjar en extern klocka (Ref_Clk) med frekvenser upp till 100 MHz som distribueras över hela bildmatrisen. Förförstärkaren är förbättrad och en enkel diskriminator med 4 bitars tröskeljustering används för att minimera lägsta detekterbara laddningspuls. Mätningar visar ett elektroniskt brus på ~100 e- rms och förstärkningen 16,5 mV/ke-. Med en tröskelspridning på 35 e- rms blir minsta detekterbara laddning för den nakna kretsen (t.ex. i en gasfylld detektor) ~650 eoch för en bondad detektor ~750 e-. Den statiska effektförbrukningen är ~13,5 mV per bildelement vid Vdda=2,2 V och Ref_Clk= 80 MHz. Den här kretsfamiljen har använts i ett antal olika applikationer. Under dessa studier har ett antal begränsningar konstaterats. Bland dessa märks begränsad energiupplösning och begränsad detektorarea. Framtida utvecklingsprojekt, t.ex. Medipix3, kommer att inriktas på att avhjälpa dessa begränsningar genom att utnyttja den senaste utvecklingen på mikroelektronikområdet.
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Helsby, Stephen John. « The integration of fibre optics for atom chips ». Thesis, University of Southampton, 2008. https://eprints.soton.ac.uk/63326/.
Texte intégralRésumé :
This thesis reports on the progress made towards the integration of fibre optics components for the atom chip, a device developed to manipulate matter on the atomic scale for the purpose of quantum information processing, novel applications, and fundamental research. Following in the direction of the electronics industry, miniaturisation has resulted in exquisite control of cold atoms above surfaces, allowing the vision of a matter wave toolbox to come closer to fruition. However, although the size of the components necessary for guiding atoms via magnetic or electrostatic fields has been greatly reduced, there is still a need to scale down the optical components. The development of these cavities is detailed in this thesis, from early use of evaporated gold coated mirrors to the fully integral solution of photorefractive Bragg gratings. In addition to a thorough analysis of the optical properties of these fibre gap cavities, experimental results indicate that these gap cavity devices can be constructed with the sensitivity necessary for single atom detection.
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Laprise, Emmanuelle. « Design and implementation of optoelectronic-VLSI chips for short reach optical interconnects ». Thesis, McGill University, 2001. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=32963.
Texte intégralRésumé :
The challenges encountered while designing the silicon ASICs for three short reach optical interconnects will be described. Many of the difficulties encountered at the chip level will be analyzed. These will include how to route the large lines required to power the transceivers, how to reduce the large number of individually controlled analog signals, and how to group the transceivers when doing the top level floorplan. Silicon chip features can also be useful to meet the system-level challenges. A method that facilitates on-chip random data generation and verification will be proposed. A method that can facilitate the synchronization of two optical sub-systems, using dual-port fifos, will be analyzed. On-chip test features that facilitate pre-hybridization, post-hybridization and system testing will be analyzed. Optical scan chains are one of the test features that will be presented. Their use in performing in-system and built-in-self-tests will be contemplated.
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Hollis, Timothy M. « Circuit and modeling solutions for high-speed chip-to-chip communication / ». Diss., CLICK HERE for online access, 2007. http://contentdm.lib.byu.edu/ETD/image/etd1721.pdf.
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Lewis, Gareth Neil. « Towards an integrated atom chip ». Thesis, University of Southampton, 2009. https://eprints.soton.ac.uk/66601/.
Texte intégralRésumé :
The field of atom chips is a relatively new area of research which is rapidly becoming of great interest to the scientific community. It started out as a small branch of cold atom physics which has quickly grown into a multidisciplinary subject. It now encompasses topics from fundamental atomic and quantum theory, optics and laser science, to the engineering of ultra sensitive sensors. In this thesis the first steps are taken towards a truly integrated atom chip device for real world applications. Multiple devices are presented that allow the trapping, cooling, manipulation and counting of atoms. Each device presents a new component required for the integration and miniaturisation of atom chips into a single device, capable of being used as a sensor. Initially, a wire trap was created capable of trapping and splitting a cloud of BoseEinstein condensate (BEC) for use in atom interferometry. Using this chip a BEC has been successfully created, trapped and coherent splitting of this cloud has been achieved. Subsequently, the integration and simplification of the initial trapping process was approached. In all the experiments to date, atoms are initially collected from a warm vapour by a magneto-optical trap (MOT). This thesis presents a new approach in which microscopic pyramidal MOTs’ are integrated into the chip itself. This greatly reduces the number of optical components and helps to simplify the process significantly. Also presented is a method for creating a planar-concave micro-cavity capable of single atom detection. One such cavity consists of a concave mirror fabricated in silicon and the planar tip of an optical fibre. The performance of the resonators is highly dependent on the surface roughness and shape profile of the concave mirrors therefore a detailed study into the fabrication technique and its effects on these parameters was undertaken. Using such cavities single atom detection has been shown to be possible. These cavities have also been sccessfully integrated into an atom wire guide. Finally a co-sputtered amorphous silicon/titanium (a-Si/Ti) nanocomposite material was created and studied for its use as a novel structural material. This material is potentially suitable for integrated circuitry (IC)/Micro-electromechanical- systems (MEMS) integration. The material’s electrical and structural properties were investigated and initial results suggest that a-Si/Ti has the potential to be a compelling structural material for future IC/MEMS integration. To build all of these devices, a full range of standard microfabrication techniques was necessary as well as some non standard processes that required considerable process development such as the electrochemical deposition. This thesis presents a tool box of fabrication techniques for creating various components capable of different tasks that can be integrated into a single device. Each component has been successfully demonstrated in laboratory conditions. This represents a significant step toward a real world atom chip device.
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Corey, Steven D. « Automatic measurement-based characterization of off-chip interconnect circuitry using lumped elements / ». Thesis, Connect to this title online ; UW restricted, 1997. http://hdl.handle.net/1773/6008.
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Venton, Jennifer Lynne. « Flip chip on flex for low cost electronics assembly ». Thesis, Georgia Institute of Technology, 2000. http://hdl.handle.net/1853/17285.
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Oulmane, Mourad. « On-Chip global interconnect optimization ». Thesis, McGill University, 2001. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=33985.
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We present a practical yet accurate approach for dealing with the problem of inserting repeaters along on-chip interconnect lines to meet delay and transition time requirements. This approach is based on the fact that the transition time and the delay at the far end of an interconnect segment are, respectively, independent and linearly dependent on the driving repeater's input transition time, as long as the ratio of the output to input transition time does not exceed a pre-defined value. In this context, we first derive simple closed form expressions for the optimal repeater spacing and sizing. Then, we propose a bottom-up "pseudo" hierarchical quadratic programming method for inserting and sizing repeaters in RC interconnects. This method, unlike Van Ginneken's [30], although largely based on it, is able to account for transition times at every potential repeater insertion point along the RC line of interest. The resulting technique can be readily incorporated in a more general RC network optimization scheme (through repeater insertion) where, eventually, wire sizing can be formulated either as an objective or a constraint.Accurate moment matching techniques for computing the RC delays and transition times are used in addition to an accurate CMOS inverter/repeater delay model that takes into account short channel effects that are prevalent in deep submicron (DSM) technologies. In particular, a new delay metric, based on the first two moments of the impulse response of the interconnect RC circuit, is derived. Also, a new empirical ramp approximation that takes into account the inherent asymmetry of signals in signal distribution networks in DSM technologies is presented.
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yin, jian. « High Temperature SiC Embedded Chip Module (ECM) with Double-sided Metallization Structure ». Diss., Virginia Tech, 2005. http://hdl.handle.net/10919/30076.
Texte intégralRésumé :
The work reported in this dissertation is intended to propose, analyze and demonstrate a technology for a high temperature integrated power electronics module, for high temperature (e.g those over 200oC) applications involving high density and low stress.
To achieve this goal, this study has examined some existing packaging approaches, such as wire-bond interconnects and solder die-attach, flip-chip and pressure contacts. Based on the survey, a high temperature, multilayer 3-D packaging technology in the form of an Embedded Chip Module (ECM) is proposed to realize a lower stress distribution in a mechanically balanced structure with double-sided metallization layers and material CTE match in the structure.
Thermal and thermo-mechanical analysis on an ECM is then used to demonstrate the benefits on the cooling system, and to study the material and structure for reducing the thermally induced mechanical stress. In the thermal analysis, the high temperature ECM shows the ability to handle a power density up to 284 W/in3 with a heat spreader only 2.1x2.1x0.2cm under forced convection. The study proves that the cooling system can be reduced by 76% by using a high temperature module in a room temperature environment.
Furthermore, six proposed structures are compared using thermo-mechanical analysis, in order to obtain an optimal structure with a uniform low stress distribution. Since pure Mo cannot be electroplated, the low CTE metal Cr is proposed as the stress buffering material to be used in the flat metallization layers for a fully symmetrical ECM structure. Therefore, a chip area stress as low as 126MPa is attained.
In the fabrication process, the high temperature material glass and a ceramic adhesive are applied as the insulating and sealing layers. Particularly, the Cr stress buffering layer is successfully electroplated in the high temperature ECM by means of the hard chrome plating process. The flat metallization layer is accomplished by using a combined structure with Cr and Cu metallization layers.
The experimental evaluations, including the electrical and thermal characteristics of the ECM, have been part of in the study. The forward and reverse characteristics of the ECM are presented up to 250oC, indicating proper device functionality. The study on the reverse characteristics of the ECM indicates that the large leakage current at high temperature is not due to the package surrounding the chip, but chiefly caused by the Schottky junction and the chip passivation layer. Finally, steady-state and transient measurements are conducted in terms of the thermal measurements. The steady-state thermal measurement is used to demonstrate the cooling system reduction. To obtain the thermal parameters of the different layers in the high temperature ECM, the transient thermal measurement is applied to a single chip ECM based on the temperature cooling-down curve measurement.Ph. D.
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Morris, Randy W. Jr. « PROPEL : Power & ; Area-Efficient, Scalable Opto-Electronic Network-on-Chip ». Ohio University / OhioLINK, 2009. http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1244146228.
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Morris, Randy W. « PROPEL power & ; area-efficient, scalable opto-electronic network-on-chip / ». Ohio : Ohio University, 2009. http://www.ohiolink.edu/etd/view.cgi?ohiou1244146228.
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Parri, Jonathan. « A Framework for Selection and Integration of Custom Instructions for Hybrid System-on-Chips ». Thesis, University of Ottawa (Canada), 2010. http://hdl.handle.net/10393/28739.
Texte intégralRésumé :
Traditionally, common processor augmentation solutions have involved the addition of coprocessors or the datapath integration of custom instructions within extensible processors as Instruction Set Extensions (ISE). Rarely is the hybrid option of using both techniques explored. Much research already exists concerning the mutually exclusive identification and selection of custom hardware blocks from hardware/software partitioning techniques. The question of how to best select and use this hardware within a user system where both coprocessors and datapath augmentations are possible and are mutually inclusive remains. Here a system with both types of these custom instructions is denoted as a hybrid SoC.
In this work, both the coprocessor and internal datapath custom instruction design decisions are modeled within a design space exploration framework created to facilitate hybrid SoC development. We explore how to best select and integrate these instructions using available metrics and traditional combinatorial optimization techniques while packaging these ideas together into a complete toolchain framework. This framework is integrated into industry design flow tools in an attempt to achieve significant performance gains over existing methodologies.
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Rolston, David Robert Cameron. « The design, layout, and characterization of VLSI optoelectronic chips for free-space optical interconnects / ». Thesis, McGill University, 2000. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=36832.
Texte intégralRésumé :
The design and testing of very-large-scale-integrated optoelectronic (VLSI-OE) microchips will be described in the context of a free-space optical backplane system. The optical backplane has the potential for providing an enormous amount of bandwidth for telecommunication switching systems and massively parallel computing machines. A free-space optical backplane uses optical design techniques to relay beams of light from the surface of one microchip to the surface of another. By using light to interconnect microchips, the problems associated with high-speed electronic interconnects are avoided. By exploiting the 2-dimensional surface area of the microchips, large numbers of parallel optical interconnections are possible using minute optoelectronic devices patterned on the surface of the chips. By using appropriate optical designs and microchip layouts, massively parallel high-bandwidth interconnects can be implemented within a volume comparable with standard electronic interconnects such as buses and backplanes.This thesis will begin by describing a specific VLSI-OE chip architecture as well as two free-space optical designs used to interconnect VLSI-OE chips. Details of the design and layout of four separate VLSI-OE chips will then be given and the results of optical and electrical testing of these chips will follow. Finally, the topic of global synchronization will then be considered. Synchronization among many VLSI-OE chips in a multiple-node system requires special attention. A novel approach of providing synchronized clock signals to a multitude of distance points will be discussed.
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Wu, Wei-Chung. « On-chip charge pumps ». Diss., Georgia Institute of Technology, 2001. http://hdl.handle.net/1853/13451.
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Joung, Yeun-Ho. « Electroplating bonding technology for chip interconnect, wafer level packaging and interconnect layer structures ». Diss., Available online, Georgia Institute of Technology, 2004:, 2003. http://etd.gatech.edu/theses/available/etd-04052004-180025/unrestricted/joung%5Fyeun-ho%5F200312%5Fphd.pdf.
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Tang, Chi Wang. « Properties and selection of materials for flip chip packages with low-K die / ». View abstract or full-text, 2007. http://library.ust.hk/cgi/db/thesis.pl?MECH%202007%20TANG.
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Akambi, Aboudou S. « Low cost test fixture for self-resonant frequency measurements of passive chip components ». abstract and full text PDF (free order & ; download UNR users only), 2005. http://0-gateway.proquest.com.innopac.library.unr.edu/openurl?url_ver=Z39.88-2004&rft_val_fmt=info:ofi/fmt:kev:mtx:dissertation&res_dat=xri:pqdiss&rft_dat=xri:pqdiss:3209953.
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Mesgarzadeh, Behzad. « Circuit Techniques for On-Chip Clocking and Synchronization ». Licentiate thesis, Linköping : Linköpings universitet, 2006. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-7505.
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Zhang, Zhuqing. « Study on the curing process of no-flow and wafer level underfill for flip-chip applications ». Diss., Available online, Georgia Institute of Technology, 2004:, 2003. http://etd.gatech.edu/theses/available/etd-04072004-180247/unrestricted/zhang%5Fzhuqing%5F200312%5Fphd.pdf.
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Loh, Tzu Liang. « Integrated microfluidics, heaters, and electronic sensors for Lab-on-a-Chip applications ». Thesis, Massachusetts Institute of Technology, 2005. http://hdl.handle.net/1721.1/32355.
Texte intégralRésumé :
Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Mechanical Engineering, 2005.Includes bibliographical references (leaves 123-125).
Microfluidics, microfabricated suspended heaters and electronic field effect sensors have been successfully integrated on a single device chip. This integration enables spatial cycling of as little as 11nL of reagents over different thermally isolated temperature zones, to be coupled with the field effect sensing capabilities, for label-free detection of biomolecules such as DNA. The microfluidic valves provide control over reagent flow, and flow rates of up to 1.8nLs⁻¹ have been demonstrated with the on-chip pumps. Initial characterization of the suspended heaters was successfully carried out using thermochromic crystals. Functionality of the heaters was shown and a rough calibration was obtained. The subsequent implementation of temperature measurement using fluorescent dyes, enabled real-time spatial temperature mapping. This method demonstrated the capability of monitoring fluid temperatures in microfluidic channels with 5ÌC accuracy at 2[mu]m² resolution. Thermal isolation of the suspended heaters was clearly observed from the steep gradients in the spatial temperature profiles captured. Finally, localized boiling of water in the microfluidic channels was achieved, with only 30mW supplied to the heaters. In order to evaluate the sensors, tests were carried out to determine its sensitivity to surface charge. Buffer solutions of different pH were injected, and the sensors have been able to measure pH values ranging from 2.2 - 7.4 and demonstrate sensitivity of up to 38.8mV per pH unit change. Highly charged poly-electrolytes were also investigated as model systems to validate sensor detection of charged biomolecules.
(cont.) The adsorption and layer-by-layer deposition of multiple poly-electrolyte layers to the sensor surface have been successfully detected. This device paves the way for future integration of multiple microfluidic compo- nents, for lab-on-a-chip applications.
by Tzu Liang Loh.
S.M.
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Sun, Yangyang. « Study on the Nanocomposite Underfill for Flip-Chip Application ». Diss., Georgia Institute of Technology, 2006. http://hdl.handle.net/1853/13975.
Texte intégralRésumé :
Underfill material is a special colloidal dispersion system with silicon dioxide particles in the organic liquid. It is used to improve the reliability of integrated circuits (IC) packaging in the microelectronics. In order to successfully synthesize the nanocomposite underfill meeting the requirements of the chip package, it is necessary to have a fundamental understanding about the particle stability in the non-aqueous liquid and the relationship between materials properties and interphase structure in the composite. The results of this thesis contribute to the knowledge of colloidal dispersion of nanoparticles in organic liquid by systematically investigating the effects of particle size, particle surface chemistry and surface tension, and liquid medium polarity upon the rheological and thermal mechanical properties of underfill materials. The relaxation and dielectric properties studies indicate that the polymer molecular chain motion and polarization in the interphase region can strongly influence the material properties of nanocomposite, and so a good interaction between particle and polymer matrix is key. With this study, a potential nanocomposite underfill can be synthesized with low viscosity, low thermal expansion, and high glass transition temperature. The excellent transmittance of nanoparticles leads to further investigation of their ability as reinforcing filler in the photo-curable polymer.
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Biswas, Dhruv. « A system-on-a chip testing methodology ». Thesis, University of Ottawa (Canada), 2005. http://hdl.handle.net/10393/26854.
Texte intégralRésumé :
In this thesis, we present a system-on-a chip testing methodology. The system consists of a wrapper, test access mechanism and the cores under test. The cores include the ISCAS sequential and combinational benchmark circuits. At the gate level, stuck at fault model is used to detect faults. The wrapper separates the circuit under test from other cores. The test access mechanism transports the test patterns or test vectors to the desired circuit under test and then transports the responses back to the output pin of the SOC. The faults are then injected using the fault simulator that generates test for the circuit under test. Out of the many TAM design methods, we implemented the TAM as a plain signal transport medium, which is shared by all the cores in the system-on-chip. Once the dedicated TAM lines are set to the circuit under test, fault simulation is done. Each circuit in an SOC is independently tested for its fault coverage. The isolation of the circuit under test from the others is taken care by the program running in the background. We were able to simulate the whole SOC testing and get satisfactory fault coverage for the circuits under tests.
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Chaib, J. P. (Jean Paul). « Chip shaping and channel coding for CDMA ». Thesis, McGill University, 1997. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=26772.
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This thesis considers waveform shaping and error control coding methods to improve the performance and capacity of an asynchronous DS-CDMA communications system. The uplink of the IS-95 cellular CDMA standard is an example of such a system. In this work, we develop a criterion to measure the merits of a waveform shaping filter from the points of view of interference reduction and bandwidth occupancy. This criterion allows us to derive quasi optimal waveforms. It is shown, for example, that the pulse shaping filter of the IS-95 standard is close to optimal.We also show, in the first part of this thesis, that pseudo random sequence spreading is an inefficient way of expanding bandwidth. Indeed, we prove that the optimal sharing of bandwidth spreading between PN sequences and error control coding is obtained when all the spreading is due to the error control code. The role of PN sequences for user separation is not diminished, while the system benefits from the added coding gain.
In order to realize as much as possible of the potential coding gain, good very low rate codes are needed. The second part of this thesis focuses on the design of specific low rate error control codes for CDMA systems. We consider a new coding scheme, based on the combination of trellis codes and first-order Reed-Muller codes. We develop two families of codes based on this scheme, and study their performance both analytically and through simulations. We find the performance of our codes to be superior to that of other families of very low rate codes, such as the orthogonal, biorthogonal, and superorthogonal convolutional codes, and the error control code specified in the IS-95 standard.
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Yan, Wei Johnson R. Wayne. « Process development of double bump flip chip with enhanced reliability and finite element analysis ». Auburn, Ala., 2005. http://repo.lib.auburn.edu/2005%20Summer/doctoral/YAN_WEI_15.pdf.
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Zhang, Zhuqing. « No-flow underfill materials for environment sensitive flip-chip process ». Thesis, Georgia Institute of Technology, 2001. http://hdl.handle.net/1853/19084.
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Codrescu, Lucian. « Atlas : a dynamically parallelizing chip-multiprocessor for gigascale integration ». Diss., Georgia Institute of Technology, 2000. http://hdl.handle.net/1853/15519.
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Moadeli, Mahmoud. « Quarc : an architecture for efficient on-chip communication ». Thesis, University of Glasgow, 2010. http://theses.gla.ac.uk/1991/.
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The exponential downscaling of the feature size has enforced a paradigm shift from computation-based design to communication-based design in system on chip development. Buses, the traditional communication architecture in systems on chip, are incapable of addressing the increasing bandwidth requirements of future large systems. Networks on chip have emerged as an interconnection architecture offering unique solutions to the technological and design issues related to communication in future systems on chip. The transition from buses as a shared medium to networks on chip as a segmented medium has given rise to new challenges in system on chip realm. By leveraging the shared nature of the communication medium, buses have been highly efficient in delivering multicast communication. The segmented nature of networks, however, inhibits the multicast messages to be delivered as efficiently by networks on chip. Relying on extensive research on multicast communication in parallel computers, several network on chip architectures have offered mechanisms to perform the operation, while conforming to resource constraints of the network on chip paradigm. Multicast communication in majority of these networks on chip is implemented by establishing a connection between source and all multicast destinations before the message transmission commences. Establishing the connections incurs an overhead and, therefore, is not desirable; in particular in latency sensitive services such as cache coherence. To address high performance multicast communication, this research presents Quarc, a novel network on chip architecture. The Quarc architecture targets an area-efficient, low power, high performance implementation. The thesis covers a detailed representation of the building blocks of the architecture, including topology, router and network interface. The cost and performance comparison of the Quarc architecture against other network on chip architectures reveals that the Quarc architecture is a highly efficient architecture. Moreover, the thesis introduces novel performance models of complex traffic patterns, including multicast and quality of service-aware communication.
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Han, Dongil. « Optimal constructs for chip level modeling ». Thesis, Virginia Polytechnic Institute and State University, 1986. http://hdl.handle.net/10919/94469.
Texte intégralRésumé :
Analysis and comparison of nine different Hardware Description Languages is presented. Comparison features are discussed and each language is analysed according to the comparison features, which are: sequencing mechanisms, applicability to generic structures, abstraction of data and operation, timing mode, communication mechanisms, and instantiation and interconnection of elements. Based on the analysis of the languages, optimal constructs for chip level modeling are extracted. Example descriptions of a microprocessor system MARK 2 are presented.M.S.
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Lu, Zhonghai. « Design and Analysis of On-Chip Communication for Network-on-Chip Platforms ». Doctoral thesis, KTH, Elektronik- och datorsystem, ECS, 2007. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-4290.
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Due to the interplay between increasing chip capacity and complex applications, System-on-Chip (SoC) development is confronted by severe challenges, such as managing deep submicron effects, scaling communication architectures and bridging the productivity gap. Network-on-Chip (NoC) has been a rapidly developed concept in recent years to tackle the crisis with focus on network-based communication. NoC problems spread in the whole SoC spectrum ranging from specification, design, implementation to validation, from design methodology to tool support. In the thesis, we formulate and address problems in three key NoC areas, namely, on-chip network architectures, NoC network performance analysis, and NoC communication refinement. Quality and cost are major constraints for micro-electronic products, particularly, in high-volume application domains. We have developed a number of techniques to facilitate the design of systems with low area, high and predictable performance. From flit admission and ejection perspective, we investigate the area optimization for a classical wormhole architecture. The proposals are simple but effective. Not only offering unicast services, on-chip networks should also provide effective support for multicast. We suggest a connection-oriented multicasting protocol which can dynamically establish multicast groups with quality-of-service awareness. Based on the concept of a logical network, we develop theorems to guide the construction of contention-free virtual circuits, and employ a back-tracking algorithm to systematically search for feasible solutions. Network performance analysis plays a central role in the design of NoC communication architectures. Within a layered NoC simulation framework, we develop and integrate traffic generation methods in order to simulate network performance and evaluate network architectures. Using these methods, traffic patterns may be adjusted with locality parameters and be configured per pair of tasks. We propose also an algorithm-based analysis method to estimate whether a wormhole-switched network can satisfy the timing constraints of real-time messages. This method is built on traffic assumptions and based on a contention tree model that captures direct and indirect network contentions and concurrent link usage. In addition to NoC platform design, application design targeting such a platform is an open issue. Following the trends in SoC design, we use an abstract and formal specification as a starting point in our design flow. Based on the synchronous model of computation, we propose a top-down communication refinement approach. This approach decouples the tight global synchronization into process local synchronization, and utilizes synchronizers to achieve process synchronization consistency during refinement. Meanwhile, protocol refinement can be incorporated to satisfy design constraints such as reliability and throughput. The thesis summarizes the major research results on the three topics.QC 20100525
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Malherbe, Victor. « Multi-scale modeling of radiation effects for emerging space electronics : from transistors to chips in orbit ». Thesis, Aix-Marseille, 2018. http://www.theses.fr/2018AIXM0753/document.
Texte intégralRésumé :
En raison de leur impact sur la fiabilité des systèmes, les effets du rayonnement cosmique sur l’électronique ont été étudiés dès le début de l’exploration spatiale. Néanmoins, de récentes évolutions industrielles bouleversent les pratiques dans le domaine, les technologies standard devenant de plus en plus attrayantes pour réaliser des circuits durcis aux radiations. Du fait de leurs fréquences élevées, des nouvelles architectures de transistor et des temps de durcissement réduits, les puces fabriquées suivant les derniers procédés CMOS posent de nombreux défis. Ce travail s’attelle donc à la simulation des aléas logiques permanents (SEU) et transitoires (SET), en technologies FD-SOI et bulk Si avancées. La réponse radiative des transistors FD-SOI 28 nm est tout d’abord étudiée par le biais de simulations TCAD, amenant au développement de deux modèles innovants pour décrire les courants induits par particules ionisantes en FD-SOI. Le premier est principalement comportemental, tandis que le second capture des phénomènes complexes tels que l’amplification bipolaire parasite et la rétroaction du circuit, à partir des premiers principes de semi-conducteurs et en accord avec les simulations TCAD poussées.Ces modèles compacts sont alors couplés à une plateforme de simulation Monte Carlo du taux d’erreurs radiatives (SER) conduisant à une large validation sur des données expérimentales recueillies sous faisceau de particules. Enfin, des études par simulation prédictive sont présentées sur des cellules mémoire et portes logiques en FD-SOI 28 nm et bulk Si 65 nm, permettant d’approfondir la compréhension des mécanismes contribuant au SER en orbite des circuits intégrés modernesThe effects of cosmic radiation on electronics have been studied since the early days of space exploration, given the severe reliability constraints arising from harsh space environments. However, recent evolutions in the space industry landscape are changing radiation effects practices and methodologies, with mainstream technologies becoming increasingly attractive for radiation-hardened integrated circuits. Due to their high operating frequencies, new transistor architectures, and short rad-hard development times, chips manufactured in latest CMOS processes pose a variety of challenges, both from an experimental standpoint and for modeling perspectives. This work thus focuses on simulating single-event upsets and transients in advanced FD-SOI and bulk silicon processes.The soft-error response of 28 nm FD-SOI transistors is first investigated through TCAD simulations, allowing to develop two innovative models for radiation-induced currents in FD-SOI. One of them is mainly behavioral, while the other captures complex phenomena, such as parasitic bipolar amplification and circuit feedback effects, from first semiconductor principles and in agreement with detailed TCAD simulations.These compact models are then interfaced to a complete Monte Carlo Soft-Error Rate (SER) simulation platform, leading to extensive validation against experimental data collected on several test vehicles under accelerated particle beams. Finally, predictive simulation studies are presented on bit-cells, sequential and combinational logic gates in 28 nm FD-SOI and 65 nm bulk Si, providing insights into the mechanisms that contribute to the SER of modern integrated circuits in orbit
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Liu, Xingsheng. « Processing and Reliability Assessment of Solder Joint Interconnection for Power Chips ». Diss., Virginia Tech, 2001. http://hdl.handle.net/10919/26691.
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Circuit assembly and packaging technologies for power electronics have not kept pace with those for digital electronics. Inside those packaged power devices as well as the state-of-the-art power modules, interconnection of power chips is accomplished with wirebonds. Wirebonds in power devices and modules are prone to resistance, noise, parasitic oscillations, fatigue and eventual failure. Furthermore, there has been an increase demand for higher power density and better efficiency for power converters. Power semiconductor suppliers have been concentrating on improving device structure, density, and process technology to lower the on-resistance of MOSFETs and voltage drop of IGBTs. Recent advances made in power semiconductor technology are pushing packaging technology to the limits for performance of these power systems since the resistance and parasitics contribution by the package and the wirebonds are roughly the same as that on the silicon. In recent years, an integrated systems approach to standardizing power electronics components and packaging techniques in the form of power electronics building blocks has emerged as a new concept in the area of power electronics. As a result, it has been envisioned that the packaging of three-dimensional high-density multichip modules (MCMs) can meet the requirement for future power electronics systems. However, the conventional wirebond interconnected power devices are excluded from three-dimensional MCMs because of their large size, limited thermal management, and incompatible processing techniques. On the other hand, advanced solder joint area-array technologies, such as flip-chip technology, has emerged in microelectronics industry due to increased speed, higher packaging density, and performance, improved reliability and low cost these technologies offer. With all these benefits to offer, solder joint area-array technology has yet to be implemented for power electronics packaging. Therefore, the first objective of this study is to design and develop a solder joint area-array interconnection technique for power chips. Solder joint reliability is a major concern for area array technologies and power chip interconnection, thus the second objective of this study is to evaluate solder joint reliability, investigate the fatigue failure behavior of solder joint and improve solder joint reliability by developing a new solder bumping process for improved solder joint geometry, underfilling solder joint with encapsulant and applying flexible substrate in the assembly. The third objective is the implementation of solder joint interconnection technique in developing chip-scale power packages and a three-dimensional integrated power electronics module structure.
Solder joint area array interconnection for power chips has been designed with the considerations of parasitic resistance and inductance reduction, current handling capability, thermal management, reliability improvement and manufacturability. A new solder joint fabrication process, which is able to produce high standoff hourglass-shaped solder joint that consists of an inner cap, middle ball and outer cap, as well as the conventional solder bumping process have been successfully developed for power chips by using stencil printing. This solder bumping technology is compatible with the existing surface-mount assembly operations and potentially low cost. The fabricated solder joints have been characterized for their structure integrity, mechanical strength and electrical performances.
Solder joint reliability has been improved by optimizing solder joint geometry, underfilling flipped power chip and utilizing compliant substrate. Solder joint reliability was evaluated using accelerated temperate cycling and adhesion tests. The interfaces of the triple-stacked solder joints were examined using scanning electron microscopy (SEM) and energy dispersive X-ray analysis (EDX) for the integrity of the joint. Acoustic microscopy imaging (nondestructive evaluation) was utilized to examine the quality of the bonded interfaces and to detect cracks and other defects before and during accelerated fatigue tests. Adhesion strength of both single bump barrel-shaped and stacked hourglass-shaped solder joints to bonding pads was characterized and analyzed. It was found that stacked hourglass-shaped solder joint have higher fracture stress than barrel-shaped solder joint. This verifies that hourglass-shaped solder joint has lower stress singularity at the interface between the solder bump and the silicon die as well as at the interface between the solder bump and substrate than barrel-shaped solder joint, especially around the corners of the interfaces. Furthermore, the adhesion strength of barrel-shaped solder joint decreases much faster than that of high standoff hourglass-shaped solder joint under temperature cycling, which indicates that the latter has high reliability than the former. Our accelerated temperature cycling test clearly shows that solder joint fatigue failure process consists of three phases: crack initiation, crack propagation and catastrophic failure. Solder joint geometry, underfilling and substrate flexibility were proved to affect solder joint reliability. The effects of solder joint shape and standoff height on reliability have been systematically studied experimentally for the first time. Our experimental results indicated that both hourglass shape and great standoff height could improve solder joint fatigue lifetime, with standoff height being the more effective factor. The fatigue lifetime of high standoff hourglass-shaped solder joint is improved mainly by prolonged crack propagation time, with slight improvement in crack initiation time. Experimental data suggested that shape is the dominant factor affecting crack initiation time while standoff height is the major factor influencing crack propagation time. Underfilling and flexible substrate improved the lifetime of both barrel and hourglass-shaped solder joints. The effect of underfill on solder joint reliability is well known in microelectronics packaging field. However, for the first time, it is reported in this study that flex substrate could improve solder joint reliability. It has been found that flex substrate bucks during temperature cycling and thus reduces thermal strain in solder joints, which in turn improves solder joint fatigue lifetime.
Chip scale packaging can enable a few very important concepts and advantages in power electronics packaging. It offers high silicon to package footprint ratio, provides a known good die solution to power chips, improves electrical as well as thermal performance and creates an opportunity for power component standardization. Two kinds of chip-scale power packages have been developed in this research. One is called cavity down flip chip on flex; the other is termed Die Dimensional Ball Grid Array (D2BGA). Both utilize solder joint as chip-level interconnection. Electrical tests show that the VCE(sat) of the high speed IGBT chip-scale packages is improved by 20% to 30% by eliminating the device¡¯s wirebonds and other external interconnections, such as leadframe. Double-sided cooling is realized in these CSPs. Temperature cycling test shows that the CSPs are reliable.
Integrated power electronics modules (IPEMs) are envisioned as integrated power modules consisting of power semiconductor devices, power integrated circuits, sensors, and protection circuits for a wide range of power electronics applications, such as inverters for motor drives and converters for power processing equipment. We have developed a three-dimensional approach, termed flip chip on flex (FCOF), for packaging high-performance IPEMs. The new concept is based on the use of solder joint (D2BGA chip scale package), not bonding wires, to interconnect power devices. This packaging approach has the potential to produce modules having superior electrical and thermal performance and improved reliability. We have demonstrated the feasibility of this approach by constructing half-bridge converters (consisting of two IGBTs, two power diodes, and a simple gate driver circuitry) which have been successfully tested at power levels over 30 kW. Switching tests have shown that parasitic inductance of the FCOF module has been reduced by 40% to 50% over conventional wire bond power modules. Better thermal management can be achieved in this three-dimensional power module structure. Compared with the state-of-the-art half-bridge power modules, the volume of the half-bridge FCOF power module is reduced by at least 65%. Reliability test shows that this flip chip on flex power module structure is potentially more reliable than wire bond power module.Ph. D.
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Roh, Jeongjin. « Mixed-signal signature analysis for systems-on-a-chip ». Access restricted to users with UT Austin EID Full text (PDF) from UMI/Dissertation Abstracts International, 2001. http://wwwlib.umi.com/cr/utexas/fullcit?p3035971.
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Luo, Shijian. « Study on adhesion of underfill materials for flip chip packaging ». Diss., Georgia Institute of Technology, 2002. http://hdl.handle.net/1853/10112.
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Shen, Meigen. « Concurrent chip and package design for radio and mixed-signal systems ». Doctoral thesis, Stockholm, 2005. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-476.
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